JPH05304220A - Resin sealed semiconductor device - Google Patents

Resin sealed semiconductor device

Info

Publication number
JPH05304220A
JPH05304220A JP13450892A JP13450892A JPH05304220A JP H05304220 A JPH05304220 A JP H05304220A JP 13450892 A JP13450892 A JP 13450892A JP 13450892 A JP13450892 A JP 13450892A JP H05304220 A JPH05304220 A JP H05304220A
Authority
JP
Japan
Prior art keywords
conductive film
film
conductive
semiconductor device
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13450892A
Other languages
Japanese (ja)
Inventor
Akihiro Hosoya
明宏 細谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP13450892A priority Critical patent/JPH05304220A/en
Publication of JPH05304220A publication Critical patent/JPH05304220A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a resin sealed semiconductor device in which stress to be exerted on a crossing part of upper and lower conductive films by sealing resin is lessened and a chip is downsized without sacrifice of reliability of the conductive film. CONSTITUTION:Crossing part of a first conductive film 3 formed on a semiconductor substrate and a second conductive film 5 formed thereon through an interlayer insulation film is isolated from other parts and the first conductive film 3 is connected through through holes 7, 8 made through the interlayer insulation film with an isolated part 53 of the second conductive film 5 which is connected with an isolated part 33 of the first conductive film 3 thus crossing the conductive films while converting the layers. This structure facilitates sliding of each of the conductive films 3, 5 and lessens stress of resin.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は樹脂封止型の半導体装置
に関し、特に配線用導体膜の応力緩和を図った半導体装
置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device, and more particularly to a semiconductor device in which stress in a conductor film for wiring is relaxed.

【0002】[0002]

【従来の技術】従来、樹脂封止型の半導体装置では、配
線用導体膜が原因とされる応力が生じている。例えば、
半導体装置のチップ周辺部における電源線とグランド線
の交叉を例にとって説明する。図6は平面図、図7はそ
のD−D線断面図であり、これらの図に示すように、半
導体基板1の一主面に半導体素子領域1Aが形成され、
第1の層間絶縁膜2を介してアルミニウム等でグランド
配線用の第1の導電膜3を形成し、更に酸化膜などの第
2の層間絶縁膜4を介して電源配線用の第2の導電膜5
を形成し、リンシリケートガラス,シリコンナイトライ
ド膜等の保護用絶縁膜6で覆っている。第2の導電膜5
の一部には電源用ボンディングパッド51が形成され、
前記保護用絶縁膜6をエッチングした窓を透して露呈さ
れている。
2. Description of the Related Art Conventionally, in a resin-sealed semiconductor device, a stress caused by a wiring conductor film has been generated. For example,
The crossing of the power supply line and the ground line in the peripheral portion of the semiconductor device chip will be described as an example. FIG. 6 is a plan view, and FIG. 7 is a cross-sectional view taken along the line D-D. As shown in these drawings, a semiconductor element region 1A is formed on one main surface of the semiconductor substrate 1,
A first conductive film 3 for ground wiring is formed of aluminum or the like through the first interlayer insulating film 2, and a second conductive film for power wiring is formed through a second interlayer insulating film 4 such as an oxide film. Membrane 5
And is covered with a protective insulating film 6 such as phosphorus silicate glass or silicon nitride film. Second conductive film 5
A power supply bonding pad 51 is formed on a part of
The protective insulating film 6 is exposed through a window obtained by etching.

【0003】このような樹脂封止型の半導体装置は、温
度サイクル試験等でモールド樹脂等の応力により、保護
用絶縁膜や層間絶縁膜にクラックが発生することが明ら
かにされている。特に、第1及び第2の導電膜3,5が
交叉される箇所では、樹脂からの応力が顕著に作用し、
この応力が原因とされてこの交差箇所でのクラックが著
しいものとされている。このため、従来ではアルミニウ
ム等で形成される導電膜にスリットを入れたり(特公昭
63−046981号)、或いは導電膜に隣接してダミー用の導
電膜を形成したりして応力の緩和を図っていた。
In such a resin-encapsulated semiconductor device, it has been clarified in a temperature cycle test or the like that cracks occur in the protective insulating film and the interlayer insulating film due to the stress of the mold resin or the like. In particular, the stress from the resin acts remarkably at the location where the first and second conductive films 3 and 5 intersect.
Due to this stress, cracks at this intersection are significant. For this reason, conventionally, a slit is formed in a conductive film formed of aluminum or the like (Japanese Patent Publication No.
No. 63-046981), or a conductive film for dummy is formed adjacent to the conductive film to reduce the stress.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、導電膜
にスリットを入れる対策では、導電膜の断面積が低減さ
れて電流密度が高くなり、発熱や耐性等の信頼性上の問
題が生じる。又、ダミー用の導電膜を形成する対策で
は、ダミー用導電膜を延設するための領域を確保する必
要があり、チップサイズの小型化の障害になるという問
題がある。本発明の目的は、導電膜の信頼性を低下する
ことなくチップの小型化を可能にした樹脂封止型半導体
装置を提供することにある。
However, as a measure for forming slits in the conductive film, the cross-sectional area of the conductive film is reduced and the current density is increased, which causes reliability problems such as heat generation and resistance. Further, in the countermeasure for forming the dummy conductive film, it is necessary to secure a region for extending the dummy conductive film, which is a problem in that it is an obstacle to downsizing the chip size. It is an object of the present invention to provide a resin-encapsulated semiconductor device that enables miniaturization of a chip without lowering reliability of a conductive film.

【0005】[0005]

【課題を解決するための手段】本発明は、半導体基板上
に形成された第1の導電膜と、この上に層間絶縁膜を介
して形成された第2の導電膜との交叉する部分をそれぞ
れ他の部分から分離させ、層間絶縁膜に形成したスルー
ホールを介して第1の導電膜を第2の導電膜の分離部分
に接続し、第2の導電膜を第1の導電膜の分離部分に接
続して各導電膜を互いに層変換して交叉する。
According to the present invention, a portion where a first conductive film formed on a semiconductor substrate and a second conductive film formed on the semiconductor film via an interlayer insulating film cross each other is provided. The first conductive film is separated from the other parts respectively, and the first conductive film is connected to the separated part of the second conductive film through the through hole formed in the interlayer insulating film, and the second conductive film is separated from the first conductive film. The conductive films are connected to each other and converted into layers to cross each other.

【0006】[0006]

【作用】即ち、本発明者がモールド樹脂封止された半導
体装置に加わる応力につき評価を行った結果、応力は半
導体装置のチップ周辺部に集中することや、形成される
導電膜の幅が狭いほど保護膜や層間絶縁膜にクラックが
発生しないことが判明した。これは幅の狭い導電膜の方
が膜自身の発生応力が小さいことによるほか、導電膜自
身がスライドしやすいことによるものであり、この効果
は上層の導電膜ほど顕著となる。このことから、本発明
では半導体基板上に形成される導電膜を極力スライドし
やすい構造としている。
That is, the present inventor evaluated the stress applied to the semiconductor device sealed with the mold resin, and as a result, the stress was concentrated on the peripheral portion of the chip of the semiconductor device and the width of the conductive film formed was narrow. It was found that the protective film and the interlayer insulating film did not crack so much. This is because the conductive film having a narrow width has a smaller stress generated in the film itself and the conductive film itself slides more easily, and this effect becomes more remarkable as the conductive film in the upper layer. From this, in the present invention, the conductive film formed on the semiconductor substrate has a structure in which sliding is as easy as possible.

【0007】[0007]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の第1実施例を示す平面図であり、図
2は図1のA−A線断面図、図3は図1のB−B線断面
図である。これらの図に示すように、本実施例はチップ
コーナー部での電源線やグランド線などの幅広配線導電
膜の交叉部に本発明を適用したものである。図1〜図3
において、半導体基板1上に第1の層間絶縁膜2が形成
され、この上に第1の導電膜3が形成される。又、この
上には第2層間絶縁膜4が形成され、この上に第2の導
電膜5が形成される。この第2の導電膜5上には保護用
絶縁膜6が被着される。ここで、前記第1の導電膜3は
グランド配線用とされ、チップのコーナ部に沿って形成
される。又、第2の導電膜5はここでは電源配線用とさ
れ、その一端部に電源用ボンディングパッド51が形成
され、他端部52は電源配線として素子領域に接続され
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a plan view showing a first embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA of FIG. 1, and FIG. 3 is a sectional view taken along the line BB of FIG. As shown in these figures, in the present embodiment, the present invention is applied to the intersections of the wide wiring conductive films such as the power supply lines and the ground lines at the chip corners. 1 to 3
In, the first interlayer insulating film 2 is formed on the semiconductor substrate 1, and the first conductive film 3 is formed thereon. Further, a second interlayer insulating film 4 is formed on this, and a second conductive film 5 is formed on this. A protective insulating film 6 is deposited on the second conductive film 5. Here, the first conductive film 3 is for ground wiring and is formed along the corner portion of the chip. Further, the second conductive film 5 is used here for power supply wiring, a power supply bonding pad 51 is formed at one end thereof, and the other end 52 is connected to the element region as power supply wiring.

【0008】ここで、前記第1の導電膜3と第2の導電
膜5との交叉部においては、それぞれの重なる部分3
3,53を他の部分から分離し、この分離部分33,5
3を第2の層間絶縁膜4に設けたスルーホール7,8を
介して相互に電気接続することで、各導電膜3,5が互
いに入れ換えられた状態で接続される。即ち、第2の導
電膜5で形成された電源用ボンディングパッド51はス
ルーホール8を介して第1導電膜3の分離部分33に接
続され、この分離部分33から再びスルーホール8を介
して電源配線用の第2の導電膜52へ接続される。又、
グランド配線用の第1の導電膜31はスルーホール7を
介して第2の導電膜5の分離部分53に接続され、この
分離部分53から再びスルーホール7を介して他のグラ
ンド配線用の第1の導電膜32に接続される。尚、前記
第1及び第2の導電膜3,5はここではアルミニウム材
で形成され、幅 100μm,厚さ 0.7μmである。又、第
1の層間絶縁膜2はBPSG膜で 0.5μm厚、第2の層
間絶縁膜4はプラズマ酸化膜で 0.7μm厚,保護用絶縁
膜6はプラズマ窒化膜で 1.0μmの膜厚である。
Here, at the intersection of the first conductive film 3 and the second conductive film 5, respective overlapping portions 3 are formed.
3,53 is separated from other parts, and these separated parts 33,5
By electrically connecting 3 to each other through the through holes 7 and 8 provided in the second interlayer insulating film 4, the conductive films 3 and 5 are connected to each other in an exchanged state. That is, the power supply bonding pad 51 formed of the second conductive film 5 is connected to the separation portion 33 of the first conductive film 3 through the through hole 8, and the power supply is again supplied from the separation portion 33 through the through hole 8. It is connected to the second conductive film 52 for wiring. or,
The first conductive film 31 for ground wiring is connected to the separated portion 53 of the second conductive film 5 through the through hole 7, and from this separated portion 53 again through the through hole 7 for the other ground wiring. 1 is connected to the conductive film 32. The first and second conductive films 3 and 5 are made of an aluminum material here, and have a width of 100 μm and a thickness of 0.7 μm. The first interlayer insulating film 2 is a BPSG film having a thickness of 0.5 μm, the second interlayer insulating film 4 is a plasma oxide film having a thickness of 0.7 μm, and the protective insulating film 6 is a plasma nitride film having a thickness of 1.0 μm. .

【0009】したがって、この構成によれば、第1及び
第2の導電膜3,5は、その交叉部において互いに導電
膜が入れ換えられているため、この部分が他から離され
てスライドし易いものとなっている。このため、保護用
絶縁膜や層間絶縁膜でのクラックの発生が抑制される。
これにより、従来は30μm以上の幅の導電膜が交叉され
た場合に生じた応力が原因とされてクラックが生じてい
たが、本発明では 100μm幅の導電膜を交叉させてもク
ラックの発生が防止できる。
Therefore, according to this structure, since the conductive films of the first and second conductive films 3 and 5 are exchanged with each other at the intersecting portions, this portion is separated from the other and easily slides. Has become. Therefore, the occurrence of cracks in the protective insulating film and the interlayer insulating film is suppressed.
As a result, in the past, cracks were generated due to the stress generated when conductive films having a width of 30 μm or more were crossed, but in the present invention, cracks are generated even when conductive films having a width of 100 μm are crossed. It can be prevented.

【0010】図4は本発明の第2実施例を示す平面図で
あり、図5は図4のC−C線断面図である。前記実施例
では、第1及び第2の導電膜3,5の交叉部でのみ相互
に導電膜を入れかえているため、電源線と平行な方向
(図3に示される図1のB−B線断面方向)は第2の導
電膜5に段差を生じないが、グランド線と平行な方向
(図2に示される図1のA−A線断面方向)においては
第2の導電膜5のみが存在するため配線段差による第2
の導電膜への応力が大きくなる。
FIG. 4 is a plan view showing a second embodiment of the present invention, and FIG. 5 is a sectional view taken along line CC of FIG. In the above-mentioned embodiment, since the conductive films are exchanged only at the intersections of the first and second conductive films 3 and 5, the direction parallel to the power supply line (the line BB in FIG. 1 shown in FIG. 3) is used. Although the second conductive film 5 does not have a step in the cross-sectional direction), only the second conductive film 5 exists in the direction parallel to the ground line (the cross-sectional direction of the line AA in FIG. 1 shown in FIG. 2). Second due to wiring step
The stress on the conductive film is increased.

【0011】このため、この実施例においては第1の導
電膜3で構成されるグランド配線部分31,32の上に
第2の層間絶縁膜4を介して第2の導電膜54,55を
形成し、これをダミー配線として構成している。このダ
ミー配線54,55を形成することにより第2の導電膜
5には配線段差が生じなくなり、第2の導電膜5にかか
る応力が低減される。尚、ダミー配線54,55は、第
1の導電膜31,32上にのみ形成される為、万一ダミ
ー配線下の第2の層間絶縁膜4にクラックが生じても何
ら半導体装置の電気特性に影響を与えることはない。
Therefore, in this embodiment, the second conductive films 54 and 55 are formed on the ground wiring portions 31 and 32 formed of the first conductive film 3 with the second interlayer insulating film 4 interposed therebetween. However, this is configured as a dummy wiring. By forming the dummy wirings 54 and 55, no wiring step is formed in the second conductive film 5, and the stress applied to the second conductive film 5 is reduced. Since the dummy wirings 54 and 55 are formed only on the first conductive films 31 and 32, even if a crack occurs in the second interlayer insulating film 4 below the dummy wirings, the electrical characteristics of the semiconductor device will not be affected. Does not affect.

【0012】[0012]

【発明の効果】以上説明したように本発明は、樹脂封止
型の半導体装置において下層の配線層と上層の配線層が
層間絶縁膜を介して交叉する部分のみ配線層を相互に層
変換させ、上下の配線層がモールド樹脂等の応力により
スライドしやすくしたので、層間絶縁膜及び保護用絶縁
膜にクラックがはいりにくくなり、配線の信頼性を著し
く向上させることができる。
As described above, according to the present invention, in the resin-sealed semiconductor device, the wiring layers are mutually converted only at the portions where the lower wiring layer and the upper wiring layer intersect with each other through the interlayer insulating film. Since the upper and lower wiring layers are easily slid by the stress of the molding resin or the like, cracks are less likely to be formed in the interlayer insulating film and the protective insulating film, and the reliability of the wiring can be significantly improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例の要部の平面図である。FIG. 1 is a plan view of an essential part of a first embodiment of the present invention.

【図2】図1のA−A線断面図である。FIG. 2 is a sectional view taken along the line AA of FIG.

【図3】図1のB−B線断面図である。FIG. 3 is a sectional view taken along line BB of FIG.

【図4】本発明の第2実施例の要部の平面図である。FIG. 4 is a plan view of an essential part of a second embodiment of the present invention.

【図5】図4のC−C線断面図である。5 is a cross-sectional view taken along the line CC of FIG.

【図6】従来の半導体装置のコーナ部の平面図である。FIG. 6 is a plan view of a corner portion of a conventional semiconductor device.

【図7】図6のD−D線断面図である。7 is a cross-sectional view taken along the line DD of FIG.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 第1の層間絶縁膜 3 第1の導電膜 4 第2の層間絶縁膜 5 第2の導電膜 6 保護絶縁膜 7,8 スルーホール 33,53 分離部分 1 Semiconductor Substrate 2 First Interlayer Insulating Film 3 First Conductive Film 4 Second Interlayer Insulating Film 5 Second Conductive Film 6 Protective Insulating Film 7,8 Through Hole 33,53 Separation Part

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に形成された第1の導電膜
と、この上に層間絶縁膜を介して形成された第2の導電
膜とを備えて樹脂で封止される半導体装置において、前
記第1及び第2の導電膜の交叉する部分をそれぞれ分離
させ、前記層間絶縁膜に形成したスルーホールを介して
第1の導電膜を第2の導電膜の分離部分に接続し、第2
の導電膜を第1の導電膜の分離部分に接続して各導電膜
を互いに層変換して交叉したことを特徴とする樹脂封止
型半導体装置。
1. A semiconductor device comprising a first conductive film formed on a semiconductor substrate and a second conductive film formed thereon via an interlayer insulating film and sealed with a resin, The intersecting portions of the first and second conductive films are separated from each other, and the first conductive film is connected to the separated portion of the second conductive film through the through hole formed in the interlayer insulating film.
The conductive film of (1) is connected to the separated portion of the first conductive film, and the conductive films are layer-converted and crossed, and the resin-encapsulated semiconductor device.
JP13450892A 1992-04-28 1992-04-28 Resin sealed semiconductor device Pending JPH05304220A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13450892A JPH05304220A (en) 1992-04-28 1992-04-28 Resin sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13450892A JPH05304220A (en) 1992-04-28 1992-04-28 Resin sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH05304220A true JPH05304220A (en) 1993-11-16

Family

ID=15129967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13450892A Pending JPH05304220A (en) 1992-04-28 1992-04-28 Resin sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH05304220A (en)

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