JPS61194864A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61194864A JPS61194864A JP3567685A JP3567685A JPS61194864A JP S61194864 A JPS61194864 A JP S61194864A JP 3567685 A JP3567685 A JP 3567685A JP 3567685 A JP3567685 A JP 3567685A JP S61194864 A JPS61194864 A JP S61194864A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- capacitive element
- metal film
- power source
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 239000010410 layer Substances 0.000 abstract description 25
- 239000003990 capacitor Substances 0.000 abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 239000002344 surface layer Substances 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000010276 construction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 230000005856 abnormality Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置に関し、特に半導体集積回路中に形
成される容邑素子構造の改良に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and more particularly, to an improvement in an element structure formed in a semiconductor integrated circuit.
ＩＣやＬＳＩ等の半導体装置では、］・ランジスタ等の
能動素子の外に抵抗や容量素子等の受動素子が含まれ、
これら受動素子の占有面積がかなりの比重を占める。特
に容量素子は他の素子に比較して大きな面積を必要とす
るため、集積度の向上を阻害する要因になっている。In semiconductor devices such as ICs and LSIs, passive elements such as resistors and capacitive elements are included in addition to active elements such as transistors.
The area occupied by these passive elements occupies a considerable proportion. In particular, capacitive elements require a larger area than other elements, which is a factor that hinders the improvement of the degree of integration.
第２図は従来の半導体ＩＡＷにおける容量素子の構造を
示ず断面図である。同図において１はＰ型シリコン基板
である。該シリコン基板１の表層にはＮ型不純物領域２
が形成され、又その表面はシリコン酸化膜３を介してア
ルミニウム等の金属膜からなるキャパシタ電極４が形成
されている。そしてＮ型不鈍物領１ｊ１２、キャパシタ
電ｔａｉ４、および両者に挟まれたシリコン酸化膜３に
よって容ｌ素子が構成されている。FIG. 2 is a cross-sectional view showing the structure of a capacitive element in a conventional semiconductor IAW. In the figure, 1 is a P-type silicon substrate. An N-type impurity region 2 is formed on the surface layer of the silicon substrate 1.
is formed, and a capacitor electrode 4 made of a metal film such as aluminum is formed on its surface with a silicon oxide film 3 interposed therebetween. A capacitive element is constituted by the N-type inert region 1j12, the capacitor electrode tai4, and the silicon oxide film 3 sandwiched between them.
なお、例えば０ＭＯ８の場合には、容量素子の片方の電
極となる不純物領域はとしてウェル領域を用いることが
多い。Note that, for example, in the case of 0MO8, a well region is often used as the impurity region that becomes one electrode of the capacitive element.
上記従来の構造からなる容量素子の場合、その容畠を大
きくしようとすれば不純物領域２の面積を大きくしなけ
ればならず、既述のしたように集積度が低下さざるを得
ない問題がある。In the case of the capacitive element having the above-mentioned conventional structure, if the capacity is to be increased, the area of the impurity region 2 must be increased, and as mentioned above, there is a problem that the degree of integration is inevitably reduced. be.
また、容量素子を構成する不純物領Ｒ２にアルミニウム
配線層を接続する場合、不純物領域２がウェル領域のよ
うに深いときには問題ないが、拡散深さが浅いときには
コンタクト部でアルミニウムが不純物領［２を突抜けて
拡散する等の異状を生じる問題がある。Furthermore, when connecting an aluminum wiring layer to the impurity region R2 constituting the capacitive element, there is no problem when the impurity region 2 is deep like a well region, but when the diffusion depth is shallow, the aluminum in the contact region connects to the impurity region [2]. There is a problem that abnormalities such as penetration and diffusion occur.
本発明は上記事情に鑑みてなされたもので、チップサイ
ズの拡大を伴うことなく大容量の容量素子を形成でき、
且つ配線の異状をも防止できる半導体装置を提供するも
のである。The present invention has been made in view of the above circumstances, and enables the formation of a large-capacity capacitive element without increasing the chip size.
Moreover, it is an object of the present invention to provide a semiconductor device that can also prevent wiring abnormalities.
本発明による半導体￥ｉｆｆは、各種の素子が形成され
た半導体基板と、該半導体基板上に絶縁膜を介して形成
された第一の金属膜パターンと、該第一の金ｌ！！膜パ
ターン上に絶縁膜を介して形成された第二の金属膜パタ
ーンとを具備し、前記第一の金属膜パターン、前記第二
の金ＩＩ！膜パターン及び両金属膜パターン間の絶縁膜
が容量素子を構成していることを特徴とするものである
。The semiconductor \iff according to the present invention includes a semiconductor substrate on which various elements are formed, a first metal film pattern formed on the semiconductor substrate via an insulating film, and the first gold l! ! a second metal film pattern formed on the film pattern via an insulating film, the first metal film pattern, the second gold II! This is characterized in that the film pattern and the insulating film between both metal film patterns constitute a capacitive element.
本発明において、前記第一および第二の金属膜パターン
はキャパシタ電極として機能するもので、このうち第一
の金属膜パターンとしては半導体装置における金属配線
層を用いることができる。但し、キャパシタＮ極として
は電位が一定である必要があるから、金属配線層を用い
る場合にはＭ源電位または接地電位に接続された配線層
を用いるのが望ましい。In the present invention, the first and second metal film patterns function as capacitor electrodes, and the first metal film pattern can be a metal wiring layer in a semiconductor device. However, since the potential of the capacitor N pole needs to be constant, when a metal wiring layer is used, it is desirable to use a wiring layer connected to the M source potential or the ground potential.
上記のように、本発明では容量素子を半導体基板中に形
成された素子の上に積層して形成できるため、チップサ
イズを拡大することなく大容量の容量素子を形成でき、
従って集積度の向上を図ることができる。As described above, in the present invention, a capacitive element can be formed by stacking it on an element formed in a semiconductor substrate, so a large capacitive element can be formed without increasing the chip size.
Therefore, it is possible to improve the degree of integration.
また、本発明ではキャパシタＮ極に拡散層を用いていな
いため、従来のように他の配線層とのコンタクト部分で
電極の突抜は等の配線異状を生じることはない。Further, in the present invention, since a diffusion layer is not used for the N electrode of the capacitor, wiring abnormalities such as poking of the electrode at the contact portion with other wiring layers do not occur as in the conventional case.
（発明の実施例）
第１図は本発明の一実施例になる半導体装置の要部を示
す断面図である。同図において、１１はＰ型シリコン基
板であり、図示しない領域にはトランジスタ等の種々の
素子が形成されている。また、シリコン基板１］の表層
には図示しないこれらの素子に電ａ電位を供給するため
のＮ＋型拡散配線層１３が形成されている。シリコン基
板１１の表面はシリコン酸化喚１３で覆われ、該シリコ
ン酸化膜上にはアルミニウム蒸ＩＭパターンからなる電
源配ＷＡＩｌｉ１４が形成されている。該電源配線層１
４は、コンタクトホールを介して前記拡散配線層１２に
オーミックコンタクトされ、また池端部は図示しないポ
ンディングパッドに接続されている。更に、電源配線層
１４の上にはＣＶＤ−・５ｉＯｚｌｔｌｉ５を介してア
ルミニウム蒸着膜パターンからなるキャパシタ電極１６
が形成されている。(Embodiment of the Invention) FIG. 1 is a sectional view showing a main part of a semiconductor device according to an embodiment of the invention. In the figure, 11 is a P-type silicon substrate, and various elements such as transistors are formed in regions not shown. Furthermore, an N+ type diffusion wiring layer 13 is formed on the surface layer of the silicon substrate 1 for supplying an electric potential to these elements (not shown). The surface of the silicon substrate 11 is covered with a silicon oxide film 13, and a power wiring WAIli 14 made of an aluminum vapor IM pattern is formed on the silicon oxide film. The power supply wiring layer 1
4 is in ohmic contact with the diffusion wiring layer 12 through a contact hole, and its end portion is connected to a bonding pad (not shown). Further, on the power supply wiring layer 14, a capacitor electrode 16 made of an aluminum vapor deposited film pattern is formed via CVD-5iOzltli5.
is formed.
上記実施例において、電源配線層１４、ｃＶＤ−８ｉＱ
２膜１５及びキャパシタ電１４１ｉ１６が容量素子を構
成している。電源配線１１４には常に一定の電源電位（
ＶｃｃまたはＶＤＤ）が供給されるから、該配線層１４
を用いて容量素子を構成しでも正常なコンデンサ機能を
得ることができろ。In the above embodiment, the power supply wiring layer 14, cVD-8iQ
The two films 15 and the capacitor electrode 141i16 constitute a capacitive element. The power supply wiring 114 always has a constant power supply potential (
Vcc or VDD), the wiring layer 14
It is possible to obtain normal capacitor function even if a capacitor is constructed using .
このように容量素子をシリコン基板中の拡散配線層を用
いずにｆａ層して構成したため、上記実施例の半導体装
置ではシリコン基板１１に形成されるトランジスタの集
積度を犠牲にすることなく大官ωのコンデンサを形成で
き、チップサイズの縮小および集積度の増大を図ること
ができる。Since the capacitive element is configured as an FA layer without using a diffusion wiring layer in the silicon substrate, the semiconductor device of the above embodiment can be used in large scale without sacrificing the integration degree of the transistor formed on the silicon substrate 11. A capacitor of ω can be formed, and the chip size can be reduced and the degree of integration can be increased.
なお、上記実施例では電源配線層を用いて容量素子を構
成したが、接地配線層その伯の電像が一定な配線層を用
いても良く、また別個にキャパシタ電極を形成してもよ
い。In the above embodiments, the capacitor element is constructed using a power supply wiring layer, but a wiring layer having a constant electric pattern may be used instead of the ground wiring layer, or a capacitor electrode may be formed separately.
〔発明の効果〕
以上詳述したように、本発明の半導体装置によればチッ
プサイズの拡大を伴うことなく大容量の容量素子を形成
でき、且つ従来のように容量素子と配線とのコンタクト
部分における異状をも回避できる等、顕著な効果が１９
られるものである。[Effects of the Invention] As detailed above, according to the semiconductor device of the present invention, a large-capacity capacitive element can be formed without increasing the chip size, and the contact portion between the capacitive element and the wiring can be formed without increasing the chip size. There are 19 remarkable effects, such as being able to avoid abnormalities in
It is something that can be done.
第１図は本発明の一実施例になる半導体装置の要部を示
す断面図、第２図は従来の半導体装置における容量素子
部分の構造を示す断面図である。
１１・・・Ｐ型シリコン基板、１２・・・拡散配線層、
１３・・・シリコン酸化膜、１４・・・電源配線層、１
５−ＣＶＤ−８ｉ ０２ ＰＩＡ、１６−＄ｔバシタ電
極出願人代理人 弁理士 鈴江武彦
第１図
第２図FIG. 1 is a sectional view showing a main part of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the structure of a capacitive element portion in a conventional semiconductor device. 11... P-type silicon substrate, 12... Diffusion wiring layer,
13... Silicon oxide film, 14... Power wiring layer, 1
5-CVD-8i 02 PIA, 16-$t Vacita Electrode Applicant Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2
Claims (1)
上に絶縁膜を介して形成された第一の金属膜パターンと
、該第一の金属膜パターン上に絶縁膜を介して形成され
た第二の金属膜パターンとを具備し、前記第一の金属膜
パターン、前記第二の金属膜パターン及び両金属膜パタ
ーン間の絶縁膜が容量素子を構成していることを特徴と
する半導体装置。A semiconductor substrate on which various elements are formed, a first metal film pattern formed on the semiconductor substrate with an insulating film interposed therebetween, and a first metal film pattern formed on the first metal film pattern with an insulating film interposed therebetween. 1. A semiconductor device comprising: two metal film patterns, the first metal film pattern, the second metal film pattern, and an insulating film between the two metal film patterns forming a capacitive element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3567685A JPS61194864A (en) | 1985-02-25 | 1985-02-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3567685A JPS61194864A (en) | 1985-02-25 | 1985-02-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61194864A true JPS61194864A (en) | 1986-08-29 |
Family
ID=12448482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3567685A Pending JPS61194864A (en) | 1985-02-25 | 1985-02-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61194864A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6282749U (en) * | 1985-11-13 | 1987-05-27 |
-
1985
- 1985-02-25 JP JP3567685A patent/JPS61194864A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6282749U (en) * | 1985-11-13 | 1987-05-27 |
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