KR100329614B1 - Capacitor Formation Method of Semiconductor Device - Google Patents
Capacitor Formation Method of Semiconductor Device Download PDFInfo
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- KR100329614B1 KR100329614B1 KR1019980024907A KR19980024907A KR100329614B1 KR 100329614 B1 KR100329614 B1 KR 100329614B1 KR 1019980024907 A KR1019980024907 A KR 1019980024907A KR 19980024907 A KR19980024907 A KR 19980024907A KR 100329614 B1 KR100329614 B1 KR 100329614B1
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- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
Abstract
본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로, 하부전극의 표면 및 절연층을 질소분위기에서 플라즈마처리한 다음, 구리를 MOCVD(metal organic chemical vapor deposition, 이하 MOSCVD 라 함) 방법으로 상기 하부전극 표면에만 선택적으로 증착시키면 상기 구리가 요철모양으로 형성되어 전하저장전극의 표면적을 증가시켜 정전용량을 증대시킬 수 있고, 상기 구리를 형성한 다음 별도의 도핑공정을 필요로 하지 않기 때문에 공정을 단순화시키는기술이다.The present invention relates to a method for forming a capacitor of a semiconductor device, wherein the surface of the lower electrode and the insulating layer are plasma-treated in a nitrogen atmosphere, and then copper is metal oxide chemical vapor deposition (MOCVD). By selectively depositing only on the copper, the copper is formed in an uneven shape to increase the surface area of the charge storage electrode, thereby increasing the capacitance, and since the copper is formed, a separate doping process is not required. to be.
Description
본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로서, 특히 도전층으로 하부전극을 형성하고, 상기 하부전극 상부에 선택적 증착 특성을 갖는 구리를 MOCVD 방법으로 요철모양을 갖도록 형성함으로써 전하저장전극의 표면적을 증가시켜 캐패시터의 정전용량을 증가시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor of a semiconductor device, and in particular, by forming a lower electrode as a conductive layer, and forming copper having a selective deposition characteristic on the lower electrode to have an uneven shape by MOCVD. A technique of increasing the capacitance of a capacitor by increasing it.
일반적으로, 반도체소자의 고집적화가 1G DRAM급 이상으로 증가됨에 따라 캐패시터의 고정전용량이 요구되고 있다. 이를 해결하기 위해 캐패시터의 유전상수가 높은 물질을 사용하거나 유전체막의 두께를 얇게 하거나 하부전하저장전극의 표면적을 증대시키는 방법 등이 대두되고 있다.In general, as the high integration of semiconductor devices is increased to 1G DRAM or more, a fixed capacitance of a capacitor is required. In order to solve this problem, a method of using a material having a high dielectric constant of a capacitor, reducing the thickness of a dielectric film, or increasing the surface area of a lower charge storage electrode has emerged.
도시되진 않았지만 종래기술에 따른 반도체소자의 캐패시터 형성방법을 살펴보면 다음과 같다.Although not shown, a method of forming a capacitor of a semiconductor device according to the related art is as follows.
먼저, 반도체기판 상에 소자분리 산화막과 게이트산화막을 형성하고, 게이트전극과 소오스/드레인전극으로 구성되는 모스 전계효과 트랜지스터와 비트라인을 형성하고 전체표면을 평탄화시킨다.First, a device isolation oxide film and a gate oxide film are formed on a semiconductor substrate, and a MOS field effect transistor including a gate electrode and a source / drain electrode and a bit line are formed to planarize the entire surface.
다음, 전체표면에 층간절연막을 형성하고, 상기 소오스/드레인전극 중 전하저장전극 콘택으로 예정되어 있는 부분을 노출시키는 전하저장전극 콘택홀을 형성하고, 상기 콘택홀을 통하여 상기 소오스/드레인전극과 접속되는 전하저장전극 콘택 플러그를 형성한 후, 상기 전하저장전극 콘택 플러그와 접속되는 하부전극을 형성한다.Next, an interlayer insulating film is formed on the entire surface, and a charge storage electrode contact hole is formed to expose a portion of the source / drain electrode, which is intended as a charge storage electrode contact, and is connected to the source / drain electrode through the contact hole. After the charge storage electrode contact plug is formed, a lower electrode connected to the charge storage electrode contact plug is formed.
그 다음, 상기 하부전극 상부에 메타-스테이블 다결정실리콘(meta-stable poly silicon, 이하 MPS 라 함)을 형성한 후, 유전체막과 상부전극을 형성하여 캐패시터를 형성한다. 여기서, 상기 MPS 는 통상적으로 실리콘막 상에만 형성될 수 있는 물질층이다.Next, after forming meta-stable polysilicon (MPS) on the lower electrode, a dielectric film and an upper electrode are formed to form a capacitor. Here, the MPS is typically a material layer that can be formed only on the silicon film.
상기와 같은 종래기술에 따른 반도체소자의 캐패시터 형성방법은, 하부전극을 형성한 다음, 표면적을 증가시키기 위하여 요철모양을 갖는 MPS 를 형성하였으나, 상기 MPS를 형성한 후 표면적에서의 결점(depletion)을 없애기 위해서 인화수소(phosphine)를 이용한 어닐링공정을 실시해야 하는 불편함이 있고, 상기 어닐링공정으로 인한 디펙트(defect)가 발생되는 문제점이 있다.In the method of forming a capacitor of a semiconductor device according to the prior art as described above, after forming a lower electrode, an MPS having an irregular shape is formed to increase the surface area, but after forming the MPS, defects in surface area are formed. In order to eliminate, there is an inconvenience of performing an annealing process using hydrogen phosphine, and there is a problem that a defect occurs due to the annealing process.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 하부전극 상부에 선택적 증착 특성을 갖는 구리를 요철모양을 형성함으로써 전하저장전극의 표면적을 증가시켜 정전용량을 증가시키는 동시에 공정을 단순화시키는 반도체소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art, by forming a concave-convex shape of the copper having a selective deposition characteristic on the lower electrode to increase the surface area of the charge storage electrode to increase the capacitance and at the same time the semiconductor device to simplify the process It is an object of the present invention to provide a method for forming a capacitor.
도 1 및 도 2 는 본 발명에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도.1 and 2 are cross-sectional views showing a method of forming a capacitor of a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>
10 : 반도체기판 20 : 층간절연막10 semiconductor substrate 20 interlayer insulating film
30 : 하부전극 40 : 구리30: lower electrode 40: copper
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 캐패시터 형성방법은,In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention,
반도체기판 상에 하부전극을 형성하는 공정과,Forming a lower electrode on the semiconductor substrate;
상기 하부전극의 표면을 질소 플라즈마처리하는 공정과,Nitrogen plasma treatment of the surface of the lower electrode;
상기 하부전극 상부에만 구리를 선택적으로 증착하여 상기 하부전극의 표면에 요철모양 형성함으로써 표면적을 증가시키는 공정을 포함하는 것을 특징으로한다.And selectively depositing copper only on the lower electrode to increase the surface area by forming irregularities on the surface of the lower electrode.
이하, 첨부된 도면을 참고로 하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.
도 1 및 도 2 는 본 발명에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도이다.1 and 2 are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the present invention.
먼저, 반도체기판(10)에 소자분리 산화막(도시안됨), 게이트산화막(도시안됨), 게이트전극(도시안됨), 소오스/드레인 영역(도시안됨) 및 비트라인(도시안됨) 등의 하부구조물을 형성한 다음, 전체표면 상부에 층간절연막(20)을 형성한다.First, a lower structure such as an isolation layer (not shown), a gate oxide (not shown), a gate electrode (not shown), a source / drain region (not shown), and a bit line (not shown) are formed on the semiconductor substrate 10. After the formation, an interlayer insulating film 20 is formed over the entire surface.
다음, 상기 반도체기판(10)에서 전하저장전극 콘택으로 예정되는 부분을 노출시키는 전하저장전극 콘택홀을 형성하고, 상기 전하저장전극 콘택홀의 측벽에 절연막 스페이서(도시안됨)를 형성한다.Next, a charge storage electrode contact hole is formed in the semiconductor substrate 10 to expose a predetermined portion of the charge storage electrode contact, and an insulating layer spacer (not shown) is formed on the sidewall of the charge storage electrode contact hole.
그 다음, 상기 전하저장전극 콘택홀을 매립하는 도전층을 전체표면상부에 형성하고, 상기 도전층을 하부전극용 마스크(도시안됨)를 사용하여 식각함으로써 하부전극(30)을 형성한다. 이때, 상기 도전층은 실리콘으로 형성된 것이다.Next, a conductive layer filling the charge storage electrode contact hole is formed on the entire surface, and the lower electrode 30 is formed by etching the conductive layer using a mask for a lower electrode (not shown). In this case, the conductive layer is formed of silicon.
다음, 상기 하부전극(30) 표면을 750 ∼ 1000 ℃의 질소가스 분위기에서 어닐링공정을 실시하거나, 질소가스로 플라즈마처리한다. 상기와 같은 공정은 외부로 노출된 실리콘인 하부전극(30)과 층간절연막(20) 중에서 상기 하부전극(30)에만 구리가 선택 증착될 수 있도록 하는 것이다.Next, an annealing process is performed on the surface of the lower electrode 30 in a nitrogen gas atmosphere at 750 to 1000 ° C., or is plasma treated with nitrogen gas. In the above process, copper may be selectively deposited only on the lower electrode 30 among the lower electrode 30 and the interlayer insulating layer 20, which are silicon exposed to the outside.
그 다음, 상기 하부전극(30) 상부에 구리(40)를 130 ∼ 170 ℃의 온도에서 MOCVD방법으로 형성한다. 이때, 상기 구리(40)는 다결정실리콘과 같은 형태로 성장되며, 표면 이동에 의해 작은 그레인(grain)들이 뭉쳐지는 성장과정을 갖는다. 그로 인하여 상기 하부전극(30) 상부에만 굴곡이 심한 요철모양으로 증착되어 전하저장전극의 표면적을 늘릴 수 있다. 또한, 상기 구리(40)는 도전성이 우수하기 때문에 도핑공정이 따로 필요없다. (도 2참조)Then, copper 40 is formed on the lower electrode 30 by the MOCVD method at a temperature of 130 to 170 ℃. In this case, the copper 40 is grown in the form of polycrystalline silicon, and has a growth process in which small grains are aggregated by surface movement. Therefore, the surface of the charge storage electrode can be increased by being deposited in the shape of the irregularities of the bend only in the upper portion of the lower electrode 30. In addition, since the copper 40 has excellent conductivity, a doping process is not necessary. (See Fig. 2)
그 후, 후속 공정으로 유전막 및 상부전극을 형성하여 캐패시터를 형성한다.Thereafter, a dielectric film and an upper electrode are formed in a subsequent process to form a capacitor.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 캐패시터 형성방법은, 하부전극의 표면 및 절연층을 질소분위기에서 플라즈마처리한 다음, 구리를 MOCVD 방법으로 상기 하부전극 표면에만 선택적으로 증착시키면 상기 구리가 요철모양으로 형성되어 전하저장전극의 표면적을 증가시켜 정전용량을 증대시킬 수 있고, 상기 구리를 형성한 다음 별도의 도핑공정을 필요로 하지 않기 때문에 공정을 단순화시키는 이점이 있다.As described above, in the method of forming a capacitor of a semiconductor device according to the present invention, the surface of the lower electrode and the insulating layer are plasma-treated in a nitrogen atmosphere, and then copper is selectively deposited only on the surface of the lower electrode by MOCVD. It is formed in a concave-convex shape to increase the surface area of the charge storage electrode to increase the capacitance, and there is an advantage of simplifying the process because it does not require a separate doping process after forming the copper.
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US5110752A (en) * | 1991-07-10 | 1992-05-05 | Industrial Technology Research Institute | Roughened polysilicon surface capacitor electrode plate for high denity dram |
JPH06151750A (en) * | 1992-11-09 | 1994-05-31 | Mitsubishi Electric Corp | Semiconductor memory device and manufacture thereof |
US5338209A (en) * | 1993-05-13 | 1994-08-16 | The Whitaker Corporation | Electrical interface with microwipe action |
KR980005364A (en) * | 1996-06-25 | 1998-03-30 | 김광호 | Uneven metal film and its formation method, uneven electrode and manufacturing method of capacitor using same |
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Publication number | Priority date | Publication date | Assignee | Title |
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US5110752A (en) * | 1991-07-10 | 1992-05-05 | Industrial Technology Research Institute | Roughened polysilicon surface capacitor electrode plate for high denity dram |
JPH06151750A (en) * | 1992-11-09 | 1994-05-31 | Mitsubishi Electric Corp | Semiconductor memory device and manufacture thereof |
US5338209A (en) * | 1993-05-13 | 1994-08-16 | The Whitaker Corporation | Electrical interface with microwipe action |
KR980005364A (en) * | 1996-06-25 | 1998-03-30 | 김광호 | Uneven metal film and its formation method, uneven electrode and manufacturing method of capacitor using same |
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