JP3034377B2 - Method for manufacturing capacitor electrode in semiconductor device - Google Patents

Method for manufacturing capacitor electrode in semiconductor device

Info

Publication number
JP3034377B2
JP3034377B2 JP4119086A JP11908692A JP3034377B2 JP 3034377 B2 JP3034377 B2 JP 3034377B2 JP 4119086 A JP4119086 A JP 4119086A JP 11908692 A JP11908692 A JP 11908692A JP 3034377 B2 JP3034377 B2 JP 3034377B2
Authority
JP
Japan
Prior art keywords
film
polysilicon
polysilicon film
rough
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4119086A
Other languages
Japanese (ja)
Other versions
JPH05315566A (en
Inventor
弘樹 黒木
正樹 ▲吉▼丸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP4119086A priority Critical patent/JP3034377B2/en
Publication of JPH05315566A publication Critical patent/JPH05315566A/en
Application granted granted Critical
Publication of JP3034377B2 publication Critical patent/JP3034377B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置、特にD
RAM(Dynamic RANDAM Access
Memory)などにおけるキャパシタ部の電極の形
成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
RAM (Dynamic RANDAM Access)
And a method of forming an electrode of a capacitor portion in the memory section.

【0002】[0002]

【従来の技術】半導体素子、特にキャパシタを必要とす
るDRAMなどにおいて、表面に凹凸を有する粗面ポリ
シリコン膜をキャパシタの下部電極に使用すると、従来
のポリシリコン膜を使用した時に較べ表面の面積が増
え、2.5倍もの容量(Cs )が得られる。
2. Description of the Related Art In a semiconductor device, especially a DRAM requiring a capacitor, when a rough polysilicon film having an uneven surface is used for the lower electrode of the capacitor, the surface area is smaller than when a conventional polysilicon film is used. And a capacity (C s ) as much as 2.5 times can be obtained.

【0003】そのような粗面ポリシリコン膜の形成の従
来例を図2に示す。
FIG. 2 shows a conventional example of forming such a rough surface polysilicon film.

【0004】まず、図2(a)に示すように、半導体基
板1上に形成されたワード線や絶縁膜などの上にストレ
ージ電極としての第2ポリシリコン5を形成し、そのポ
リシリコン5をCVD(化学的気相成長)法で表面を粗
面化すると図2(b)に示すようにポリシリコン5上に
微小な凹凸が形成される。しかる後、この凹凸ポリシリ
コン5をストレージ電極へとパターニングし、さらにこ
の上にキャパシタ誘電膜を形成することにより、キャパ
シタ誘電膜の面積Sが増加し、凹凸がない場合に比較し
て2倍程度のCs が得られる。
First, as shown in FIG. 2A, a second polysilicon 5 as a storage electrode is formed on a word line or an insulating film formed on a semiconductor substrate 1, and the polysilicon 5 is formed. When the surface is roughened by a CVD (chemical vapor deposition) method, fine irregularities are formed on the polysilicon 5 as shown in FIG. Thereafter, the uneven polysilicon 5 is patterned into a storage electrode, and a capacitor dielectric film is further formed thereon, so that the area S of the capacitor dielectric film increases, which is about twice as large as that in the case where there is no unevenness. of C s is obtained.

【0005】以上の製法において、ポリシリコン5を形
成したらその処理装置(チャンバー)から一旦基板を取
り出し、次にCVD装置内にその基板を入れて前述した
ようにその表面を粗面化する。つまり、デポジションを
2回行う。これを通称2段デポと称している。
In the above-described manufacturing method, once the polysilicon 5 is formed, the substrate is once taken out of the processing apparatus (chamber), and then the substrate is put in a CVD apparatus to roughen the surface as described above. That is, deposition is performed twice. This is commonly called a two-stage depot.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、以上に
述べた粗面ポリシリコン膜の2段デポにおいては、下層
のポリシリコン膜あるいはアモルファスシリコン膜成膜
後、前述したように一度その処理装置であるLPCVD
(減圧CVD)炉から取り出し、その後再度LPCVD
炉で粗面ポリシリコン膜を成膜しなければならなかっ
た。
However, in the above-described two-stage deposition of a rough polysilicon film, after the lower polysilicon film or the amorphous silicon film is formed, the processing apparatus is once used as described above. LPCVD
(Low pressure CVD) Take out of furnace, then LPCVD again
A rough polysilicon film had to be formed in a furnace.

【0007】また粗面ポリシリコン膜表面の凹凸の形状
は熱処理により変化するので、LPCVD炉から取り出
す時のバッチ内での熱処理の不均一性が凹凸の変化をも
たらし、キャパシタ容量のバラツキが大きくなると云う
問題があった。
Further, since the shape of the irregularities on the surface of the rough polysilicon film changes due to the heat treatment, non-uniformity of the heat treatment in the batch at the time of taking out from the LPCVD furnace causes a change in the irregularities, and the variation in the capacitance of the capacitor increases. There was a problem.

【0008】この発明は以上述べた粗面ポリシリコン膜
の2段デポのスループットの問題点と、凹凸の不均一性
の問題点を向上させることを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to improve the problem of the throughput of the two-step deposition of the rough polysilicon film and the problem of the unevenness of the unevenness described above.

【0009】[0009]

【課題を解決するための手段】この発明は前記目的達成
のため、粗面ポリシリコン膜形成において、LPCVD
法にて膜としてすき間のない、アモルファスシリコン膜
あるいはポリシリコン膜を成膜し、同一チャンバー内で
前記アモルファスシリコン膜あるいはポリシリコン膜上
にシリコン窒化膜、あるいはシリコン酸窒化膜を形成
し、この膜の上に同一炉内で粗面ポリシリコン膜を成膜
するようにした。
In order to achieve the above object, the present invention provides a method for forming a rough polysilicon film by LPCVD.
An amorphous silicon film or a polysilicon film is formed as a film by a method, and a silicon nitride film or a silicon oxynitride film is formed on the amorphous silicon film or the polysilicon film in the same chamber. , A rough polysilicon film was formed in the same furnace.

【0010】また粗面ポリシリコン成膜後、粗面ポリシ
リコン膜上にシリコン窒化膜あるいはシリコン酸窒化膜
を形成し、その後炉の真空引き、N2 パージ、常圧復
帰、アンロードするようにしたものである。
After forming the rough polysilicon, a silicon nitride film or a silicon oxynitride film is formed on the rough polysilicon film, and then the furnace is evacuated, purged with N 2 , returned to normal pressure, and unloaded. It was done.

【0011】[0011]

【作用】この発明は、前述したように、同一炉内でシリ
コン窒化膜を堆積するようにしたので、従来の粗面ポリ
シリコン膜2段デポにくらべ、一度炉から出す必要がな
くなり、約3時間のスループット向上が期待できる。ま
た下層ポリシリコン膜の膜厚を変化させることにより、
上部粗面ポリシリコン膜形成条件に依存せず所望の膜厚
の下部電極形成が可能となる。
According to the present invention, as described above, since the silicon nitride film is deposited in the same furnace, it is not necessary to remove the silicon nitride film from the furnace once, as compared with the conventional two-stage rough polysilicon film deposition. An improvement in time throughput can be expected. Also, by changing the thickness of the lower polysilicon film,
A lower electrode having a desired thickness can be formed regardless of the conditions for forming the upper rough surface polysilicon film.

【0012】[0012]

【実施例】本発明の実施例の製造工程を図1に示し、以
下に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The manufacturing process of an embodiment of the present invention is shown in FIG. 1 and will be described below.

【0013】まず、図1(a)に示すように、シリコン
基板1を950℃、WetO2 雰囲気中で絶縁膜である
酸化膜2を形成する。その上にSiH4 を用いたLPC
VD法にて反応温度620℃、反応圧力0.2Torr
でポリシリコン膜3を堆積する。これはアモルファスシ
リコン膜でもかまわない。次に同一チャンバー内にSi
2 Cl2 /NH3 ガスを導入し、ポリシリコン膜3の
表面にシリコン窒化膜4を10〜20Åの厚さ形成す
る。
First, as shown in FIG. 1A, an oxide film 2 as an insulating film is formed on a silicon substrate 1 at 950 ° C. in a WetO 2 atmosphere. LPC using SiH 4 on it
Reaction temperature 620 ° C, reaction pressure 0.2 Torr by VD method
To deposit a polysilicon film 3. This may be an amorphous silicon film. Next, place Si in the same chamber.
An H 2 Cl 2 / NH 3 gas is introduced to form a silicon nitride film 4 on the surface of the polysilicon film 3 to a thickness of 10 to 20 °.

【0014】次に図1(b)のように、前記工程で使用
した同一チャンバー内に再びSiH4 ガスを導入し反応
温度570℃、反応圧力0.2Torrでアモルファス
シリコン膜(粗面ポリシリコン膜5とするため)を堆積
する。この時シリコン窒化膜4が存在するので堆積した
アモルファスシリコン膜は下地のポリシリコン膜3ある
いはアモルファスシリコン膜の結晶性の影響を受けるこ
とはない。
Next, as shown in FIG. 1B, an SiH 4 gas is again introduced into the same chamber used in the above step, and an amorphous silicon film (rough silicon film) is formed at a reaction temperature of 570 ° C. and a reaction pressure of 0.2 Torr. 5). At this time, since the silicon nitride film 4 is present, the deposited amorphous silicon film is not affected by the crystallinity of the underlying polysilicon film 3 or amorphous silicon film.

【0015】次に同一炉内で熱処理を5〜80分行うこ
とにより、アモルファスシリコン膜表面に結晶粒が形成
され、凹凸をもった粗面ポリシリコン膜5となる。次に
前記炉内にSiH2 Cl2 /NH3 ガスを導入し、粗面
ポリシリコン膜5表面にシリコン窒化膜6を10〜10
0Å形成する。
Next, by performing heat treatment in the same furnace for 5 to 80 minutes, crystal grains are formed on the surface of the amorphous silicon film, and a rough polysilicon film 5 having irregularities is obtained. Next, a SiH 2 Cl 2 / NH 3 gas is introduced into the furnace, and a silicon nitride film 6 is
0 ° is formed.

【0016】次に図1(c)のように、真空引き、N2
パージ、大気圧復帰を行いチャンバーから取り出す。粗
面ポリシリコン膜5表面のシリコン窒化膜6をチャンバ
ーから取り出した後HF処理で除去する。次にn型不純
物を導入、拡散し、導電性をもたせキャパシタ下部電極
とする。
[0016] Then as shown in FIG. 1 (c), the vacuum, N 2
After purging and returning to the atmospheric pressure, the chamber is taken out of the chamber. After the silicon nitride film 6 on the surface of the rough polysilicon film 5 is taken out of the chamber, it is removed by HF treatment. Next, an n-type impurity is introduced and diffused to provide conductivity and form a capacitor lower electrode.

【0017】ここでシリコン窒化膜4は10〜20Åと
薄いので、キャパシタ電極の抵抗および容量に影響を及
ぼすことはない。
Here, since the silicon nitride film 4 is as thin as 10 to 20 °, it does not affect the resistance and capacitance of the capacitor electrode.

【0018】上記において、SiH2 Cl2 /NH3
スの代りに、Si2 2 Cl2 /NH3 /N2 Oを用
い、4および6の部分をシリコン酸窒化膜で形成しても
同等の結果が得られる。
In the above description, Si 2 H 2 Cl 2 / NH 3 / N 2 O is used instead of the SiH 2 Cl 2 / NH 3 gas, and the portions 4 and 6 are formed of a silicon oxynitride film. Is obtained.

【0019】[0019]

【発明の効果】以上説明したようにこの発明によれば、
同一炉内でシリコン窒化膜を堆積するようにしたので、
従来の粗面ポリシリコン膜2段デポにくらべ、一度炉か
ら出す必要がなくなり、約3時間のスループット向上が
期待できる。また下層ポリシリコン膜の膜厚を変化させ
ることにより、上部粗面ポリシリコン膜形成条件に依存
せず所望の膜厚の下部電極形成が可能となる。
As explained above, according to the present invention,
Since a silicon nitride film was deposited in the same furnace,
Compared with the conventional two-stage rough-surface polysilicon film deposition, there is no need to once remove from the furnace, and an improvement in throughput of about 3 hours can be expected. By changing the thickness of the lower polysilicon film, a lower electrode having a desired thickness can be formed without depending on the conditions for forming the upper rough surface polysilicon film.

【0020】また、アモルファスシリコン堆積、熱処理
による粗面ポリシリコン形成後、同一炉内で膜表面にシ
リコン窒化膜を形成するようにしたので、粗面ポリシリ
コン膜における表面からの結晶化が安定し(ストップす
る)、後工程での熱処理の影響がなく、特にチャンバー
から取り出す時の影響がなくなり、ウェハー間で均一性
のすぐれた粗面ポリシリコン膜形成が可能となる。
In addition, since the silicon nitride film is formed on the film surface in the same furnace after the formation of the amorphous silicon by the amorphous silicon deposition and the heat treatment, the crystallization from the surface of the rough polysilicon film is stabilized. (Stop), there is no influence of the heat treatment in the post-process, especially when taking out from the chamber, and it is possible to form a rough polysilicon film with excellent uniformity between wafers.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例FIG. 1 shows an embodiment of the present invention.

【図2】従来例FIG. 2 Conventional example

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 酸化膜 3 ポリシリコン膜あるいはアモルファスシリコン膜 4、6 シリコン窒化膜 5 粗面ポリシリコン膜 Reference Signs List 1 silicon substrate 2 oxide film 3 polysilicon film or amorphous silicon film 4, 6 silicon nitride film 5 rough polysilicon film

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平4−196435(JP,A) 特開 平5−304273(JP,A) 特開 平5−175456(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 27/108 H01L 21/318 H01L 21/822 H01L 21/8242 H01L 27/04 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-196435 (JP, A) JP-A-5-304273 (JP, A) JP-A-5-175456 (JP, A) (58) Field (Int.Cl. 7 , DB name) H01L 27/108 H01L 21/318 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 (a)半導体基板上に絶縁膜を形成し、
その上にポリシリコン膜あるいはアモルファスシリコン
膜からなる第1の膜を形成する工程、 (b)前記工程の処理装置から前記第1の膜が形成され
た半導体基板を取り出すことなく、同一処理装置内にて
前記第1の膜上にシリコン窒化膜からなる第2の膜を形
成する工程、 (c)さらに前記工程に引き続き同一処理装置内で前記
第2の膜の上に、アモルファスシリコン膜からなる第3
の膜を堆積して熱処理を行なうことにより、該第3の膜
をその表面が凹凸形状となるポリシリコン膜にする工
程、 以上の工程を含むことを特徴とする半導体素子における
キャパシタ電極の製造方法。
(A) forming an insulating film on a semiconductor substrate;
Forming a first film made of a polysilicon film or an amorphous silicon film thereon, and (b) removing the semiconductor substrate on which the first film is formed from the processing device in the above process without removing the semiconductor substrate on which the first film is formed. Forming a second film made of a silicon nitride film on the first film, (c) further comprising an amorphous silicon film on the second film in the same processing apparatus following the above step Third
Forming a third film into a polysilicon film having an uneven surface by depositing the film and performing a heat treatment. A method for manufacturing a capacitor electrode in a semiconductor device, comprising: .
【請求項2】 前記第2の膜として、シリコン窒化膜の
代わりにシリコン酸窒化膜を形成することを特徴とする
請求項1記載の半導体素子におけるキャパシタ電極の製
造方法。
2. The method according to claim 1, wherein a silicon oxynitride film is formed as the second film instead of the silicon nitride film.
JP4119086A 1992-05-12 1992-05-12 Method for manufacturing capacitor electrode in semiconductor device Expired - Fee Related JP3034377B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4119086A JP3034377B2 (en) 1992-05-12 1992-05-12 Method for manufacturing capacitor electrode in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4119086A JP3034377B2 (en) 1992-05-12 1992-05-12 Method for manufacturing capacitor electrode in semiconductor device

Publications (2)

Publication Number Publication Date
JPH05315566A JPH05315566A (en) 1993-11-26
JP3034377B2 true JP3034377B2 (en) 2000-04-17

Family

ID=14752549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4119086A Expired - Fee Related JP3034377B2 (en) 1992-05-12 1992-05-12 Method for manufacturing capacitor electrode in semiconductor device

Country Status (1)

Country Link
JP (1) JP3034377B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5763286A (en) * 1994-09-14 1998-06-09 Micron Semiconductor, Inc. Process for manufacturing a DRAM capacitor having an annularly-grooved, cup-shaped storage-node plate which stores charge on inner and outer surfaces
JP2992516B1 (en) 1998-09-04 1999-12-20 株式会社日立製作所 Method for manufacturing semiconductor device
US6498088B1 (en) 2000-11-09 2002-12-24 Micron Technology, Inc. Stacked local interconnect structure and method of fabricating same

Also Published As

Publication number Publication date
JPH05315566A (en) 1993-11-26

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