JP3159796B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor lower electrode mainly in a semiconductor device, especially in a DRAM (Dynamic Random Access Memory).

[0002]

2. Description of the Related Art Conventionally, a rough polysilicon film having irregularities on its surface has been used for a lower electrode of a capacitor of a DRAM. It is known that a storage capacity of up to 2.5 times can be obtained. This rough polysilicon film is formed at 560-580 ° C. and 0.05-0.5 ° C. using a normal LPCVD (low pressure chemical vapor deposition) apparatus.
This is performed using SiH ₄ gas under Torr conditions.

[0003]

However, in order to use the above-mentioned rough-surfaced polysilicon film as a capacitor electrode, it is necessary to diffuse impurities into the film after the rough-surfaced polysilicon film is formed so as to have conductivity. There is.

Further, in order to provide conductivity, SiH ₄ and P
Even when doped polysilicon or doped amorphous silicon is formed by simultaneously flowing H ₃ , there is a problem that the surface does not become rough and the capacity cannot be increased.

According to the present invention, LPCVD is performed to eliminate the above-described impurity diffusion step after the formation of the rough polysilicon film.
An object of the present invention is to mix impurities into the film during the formation of a rough polysilicon film by the method, to impart conductivity, and to use the film as a capacitor electrode.

[0006]

According to the present invention, there is provided a method for manufacturing a capacitor electrode for a DRAM, comprising the steps of:
According to the method D, a phosphorus-doped amorphous silicon film is deposited using PH ₃ and SiH _4, and the Si-doped amorphous silicon film is deposited thereon in the same furnace.
A non-doped amorphous silicon film is deposited using H ₄ , and then heat treatment is performed in the same furnace.
With irregularities of about 5 to 0.2 μm
BR> Yes.

[0007]

As described above, according to the present invention, the impurity is diffused in the film in the same furnace to provide conductivity, so that the conventional implantation and impurity diffusion steps are not required. Further, by forming an amorphous silicon film (or non-doped polysilicon) using only SiH _{4 as} an upper layer, a conductive film having irregularities on the surface can be formed. Further, the impurity concentration can be made uniform as compared with the conventional rough surface polysilicon electrode.

[0008]

FIG. 1 is a sectional view showing the steps of an embodiment of the present invention, which will be described below.

First, a silicon substrate 1 is heated at 950.degree.
Oxidation is performed with O ₂ to form an oxide film 2 having a thickness of 1000 °.
Next, a reaction temperature of 550 ° C. to 580 ° C. and a reaction pressure of 0.1 to 500 ° C. were obtained by LPCVD using SiH ₄ gas and PH ₃ gas.
0.5 Torr, SiH ₄ flow rate is 1000 SCCM, P
H ₃ is 1% of He base, flow rate is 150 SCCM, average deposition rate is 30 ° / min and thickness is 1000-3
A phosphorus-doped amorphous silicon film 3 having a thickness of 2,000 ° is formed. At this time, the phosphorus concentration of the phosphorus-doped amorphous silicon film 3 is 5 × 10 ²⁰ atm / cm ³ . afterwards,
In the same furnace, the amorphous silicon film 4 is formed on the phosphorus-doped amorphous silicon film 3 at a reaction pressure of 0.1 to 0.5 Torr using only SiH ₄ gas while maintaining the same furnace temperature.
(May be non-doped polysilicon) from 300 to 10
Deposited by 00 ° (FIG. 1A).

Thereafter, heat treatment is performed in the same furnace, at the same temperature, in a vacuum or in an N ₂ atmosphere. At this time, crystal grains grow due to migration of silicon atoms from the surface of the amorphous silicon film 4, and a phosphorus-doped rough surface polysilicon film 5 having irregularities with crystal grains of 0.05 to 0.2 μm on the surface is formed. (FIG. 1B).

Thereafter (or an oxide film may be formed on the surface of the phosphorus-doped rough polysilicon film 5),
The film 5 is heat-treated at 0 ° C. to 850 ° C. in an inert gas atmosphere such as N ₂ for 1 hour to 15 hours to crystallize the film 5. At this time,
Crystallization does not occur from the surface of the film 5, and the shape of the surface irregularities does not change.

Thereafter, the phosphorus-doped rough-surface polysilicon film 5 is used as a lower electrode of a capacitor, and a silicon oxide film / silicon nitride film 6 as a dielectric film 6 is formed thereon, and an upper electrode 7 is formed thereon. A capacitor part is manufactured (FIG. 1C).

[0013]

As described above, according to the present invention, impurities can be diffused in a film in the same furnace to have conductivity. That is, although film formation using PH ₃ and SiH ₄ has not been able to be roughened in the past, amorphous silicon (non-doped polysilicon may be laminated) only with SiH _{4 on} the upper layer enables roughening and conductivity. You can have sex. Therefore, the conventional implantation and impurity diffusion steps become unnecessary. In addition, since the surface has irregularities, the amount of accumulated charge as a capacitor is, of course, 2% smaller than that of the conventional phosphorus-doped polysilicon film.
~ 2.5 times. Further, the impurity concentration can be made uniform as compared with the conventional rough surface polysilicon electrode.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate 2 oxide film 3 phosphorus-doped amorphous silicon film 4 amorphous silicon film 5 phosphorus-doped rough polysilicon film 6 dielectric film 7 upper electrode

──────────────────────────────────────────────────続 き Continuation of the front page (72) The inventor ▲ Yoshi ▲ Masaki 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-5-315543 (JP, A (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/205 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (1)

(57) [Claims] A step of forming an amorphous silicon film with an impurity introduced on a semiconductor substrate at a desired temperature by using a CVD apparatus; and forming an impurity on the amorphous silicon film in the CVD apparatus at the temperature. A first heat treatment is performed in the CVD apparatus at the above temperature to form a silicon film having irregularities on the surface after forming the first silicon film into which the irregularities are not introduced. Performing a second heat treatment after the formation, and diffusing the impurities introduced into the amorphous silicon film into the silicon film having the irregularities on the surface.