JPH0786434A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0786434A JPH0786434A JP5231540A JP23154093A JPH0786434A JP H0786434 A JPH0786434 A JP H0786434A JP 5231540 A JP5231540 A JP 5231540A JP 23154093 A JP23154093 A JP 23154093A JP H0786434 A JPH0786434 A JP H0786434A
- Authority
- JP
- Japan
- Prior art keywords
- film
- impurities
- rough surface
- storage node
- polysilicon film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置の製造方法
の中で、特にＤＲＡＭ（Ｄｙｎａｍｉｃ Ｒａｎｄｏｍ
Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）のスタックド・キャパ
シタセル（Ｓｔｕｃｋｅｄ−Ｃａｐａｃｉｔｏｒ Ｃｅ
ｌｌ）構造の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a DRAM (Dynamic Random).
Stacked Capacitor Cell (Access Memory) (Stacked-Capacitor Ce)
11) The present invention relates to a method for manufacturing a structure.
【０００２】[0002]
【従来の技術】図２は、粗面ポリシリコンを用いたスタ
ック・キャパシタ構造を持つＤＲＡＭのメモリ・セルの
従来の製造方法の一例を示したものである。以下、図２
を用いて、詳細な説明をする。2. Description of the Related Art FIG. 2 shows an example of a conventional method of manufacturing a memory cell of a DRAM having a stack capacitor structure using rough surface polysilicon. Below, FIG.
Will be used for a detailed description.
【０００３】まず、図２（ａ）に示すように、シリコン
単結晶半導体基板（以下、基板と略す）１に、図示しな
いシリコン窒化膜（以下ＳｉＮ膜と称す）を耐酸化マス
クとして用いるＬＯＣＯＳ法（選択酸化法）により、フ
ィールド酸化膜２を形成し、アクティブ領域２１とフィ
ールド領域２２を分離する。その後、ゲート酸化膜（図
示しない）を生成させ、ゲート電極（一般にポリシリコ
ン）３を形成する。そしてゲート電極３の側壁にＣＶＤ
（化学的気相成長）シリコン酸化膜（以下、ＣＶＤ−Ｓ
ｉＯ2 膜と略す。）からなるサイドウォール４を公知の
エッチング技術でセルファライン的に形成し、それをマ
スクとしてリンなどの不純物をイオン注入することによ
り、基板１上にＭＯＳトランジスタのソース／ドレイン
部となる不純物拡散層（以下、Ｓ／Ｄ部と略す）５を形
成する。その後、基板１の全体に絶縁膜６としてＣＶＤ
−ＳｉＯ2 膜を堆積させ、Ｓ／Ｄ部５と電荷蓄積電極
（以下、ストレージ・ノードと略す）（後述の８）とを
接続するコンタクトホール（以下、セルコンと略す）７
をホトリソ（ホトリソグラフィ）・エッチング技術で形
成する。First, as shown in FIG. 2A, a silicon single crystal semiconductor substrate (hereinafter abbreviated as a substrate) 1 is provided with a silicon nitride film (hereinafter referred to as SiN film) (not shown) as an oxidation-resistant mask. The field oxide film 2 is formed by (selective oxidation method), and the active region 21 and the field region 22 are separated. After that, a gate oxide film (not shown) is formed, and a gate electrode (generally polysilicon) 3 is formed. And CVD on the side wall of the gate electrode 3.
(Chemical vapor deposition) Silicon oxide film (hereinafter referred to as CVD-S
Abbreviated as an iO 2 film. (4) is formed as a self-alignment by a known etching technique, and impurities such as phosphorus are ion-implanted using it as a mask to form an impurity diffusion layer serving as a source / drain portion of a MOS transistor on the substrate 1. (Hereinafter abbreviated as S / D portion) 5 is formed. After that, CVD is performed as an insulating film 6 on the entire substrate 1.
A contact hole (hereinafter abbreviated as Cercon) 7 for depositing a —SiO 2 film and connecting the S / D portion 5 and a charge storage electrode (hereinafter abbreviated as a storage node) (8 described later)
Are formed by a photolithography (photolithography) etching technique.
【０００４】続いて、図２（ｂ）に示すように、減圧Ｃ
ＶＤ（ＬＰＣＶＤ）法により、基板１上に多結晶シリコ
ン（ポリシリコン）膜８を５００Å〜１０００Å程度の
厚さ、堆積させる。そして一度大気に取り出す。Then, as shown in FIG. 2 (b), a reduced pressure C
A polycrystalline silicon (polysilicon) film 8 is deposited on the substrate 1 by VD (LPCVD) to a thickness of about 500 Å to 1000 Å. And take it out to the atmosphere once.
【０００５】次いで、図２（ｃ）のように、再びＬＰＣ
ＶＤ法により、（詳しくは、膜生成温度５７０〜５８０
℃，ガス圧力、０．２Ｔｏｒｒ程度，ガス流量ＳｉＨ4
２００ｓｃｃｍ程度，デポジット時間１５分程度，デポ
ジット後の熱処理時間１５分程度、このとき、熱処理温
度は膜生成温度と同一，ガスはＮ2 ，流量は任意とす
る）ポリシリコン膜８の上に、球形状のポリシリコン膜
（以下、粗面ポリシリコン膜と称す）９を生成させる。Then, as shown in FIG. 2C, the LPC is again used.
According to the VD method (specifically, the film formation temperature of 570 to 580
° C, gas pressure, about 0.2 Torr, gas flow rate SiH 4
About 200 sccm, deposit time about 15 minutes, heat treatment time after deposit about 15 minutes, the heat treatment temperature is the same as the film formation temperature, the gas is N 2 , and the flow rate is arbitrary) A shaped polysilicon film (hereinafter referred to as a rough surface polysilicon film) 9 is generated.
【０００６】さらに配線抵抗を下げる目的で、図２
（ｄ）のように、リンまたはヒ素などのイオン注入を施
し、Ｎ2 雰囲気で８５０℃程度の熱処理を施す。In order to further reduce the wiring resistance, FIG.
As shown in (d), ion implantation of phosphorus or arsenic is performed, and heat treatment is performed at about 850 ° C. in an N 2 atmosphere.
【０００７】その後、図２（ｅ）に示すように、ホトリ
ソ・エッチング技術によりストレージノード部８，９を
所定パターンに形成し、ＳｉＮ膜のような誘電体膜（図
（ｅ）中に、黒太線で図示）１０と、キャパシタの対向
電極となる上部ポリシリコン膜（以下、セルプレートと
略す）１１を各々ＬＰＣＶＤ法で形成し、ＤＲＡＭのス
タックド・キャパシタセルが得られる。つまり、このス
タック・キャパシタセルのストレージノード部は、通常
のポリシリコン膜８と粗面ポリシリコン膜９との２層構
造となっているのである。After that, as shown in FIG. 2E, the storage node portions 8 and 9 are formed in a predetermined pattern by a photolithographic etching technique, and a dielectric film such as a SiN film (black in the figure) is formed. A stacked capacitor cell of DRAM is obtained by forming an upper polysilicon film (hereinafter abbreviated as a cell plate) 11 serving as a counter electrode of a capacitor 11 by LPCVD method, respectively. That is, the storage node portion of this stack capacitor cell has a two-layer structure of the normal polysilicon film 8 and the rough surface polysilicon film 9.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、上述し
た粗面ポリシリコン膜を用いたスタックド・キャパシタ
構造では、次のような問題点があった。However, the stacked capacitor structure using the above-mentioned rough surface polysilicon film has the following problems.
【０００９】図２（ｄ）で、粗面ポリシリコン膜を生成
した後に、ヒ素またはリンのインプラ（インプランテー
ション：注入）を行うと、表面の凹凸の違いにより、ヒ
素またはリンの注入深さに大きな違いが生じる。これに
より、配線抵抗に大きなばらつきが生じ、所望のシート
抵抗が得られなくなる。ストレージ・ノード部８，９の
シート抵抗はポリシリコン膜８の抵抗で支配されてお
り、この部分に充分に不純物が注入されないのは大きな
問題となる。また派生的な影響としてはセルコンタクト
部７の高抵抗化、ストレージノード部の空乏化といった
問題がある。In FIG. 2D, when arsenic or phosphorus is implanted (implantation) after the rough surface polysilicon film is formed, the arsenic or phosphorus implantation depth may be changed due to the difference in surface roughness. It makes a big difference. As a result, a large variation occurs in the wiring resistance, and the desired sheet resistance cannot be obtained. The sheet resistance of the storage node portions 8 and 9 is dominated by the resistance of the polysilicon film 8, and it is a serious problem that impurities are not sufficiently injected into this portion. In addition, as a secondary effect, there is a problem that the resistance of the cell contact portion 7 is increased and the storage node portion is depleted.
【００１０】次に、不純物注入をイオン注入法で行うた
め、粗面ポリシリコン膜に直接、物理的なインプラダメ
ージが加わり、表面の凹凸形状が潰れてしまい表面積増
加という、粗面ポリシリコン膜の最大の効果が得られな
くなる。この凹凸の潰れは、イオン注入量が多いほど顕
著であり、低抵抗化するためにイオン注入ドーズ量を多
くすると、それだけ凹凸が潰れてしまうといったプロセ
スの矛盾を生じてしまう。Next, since the impurity implantation is carried out by the ion implantation method, the rough surface polysilicon film is directly subjected to physical implantation damage and the uneven shape of the surface is crushed to increase the surface area. The maximum effect cannot be obtained. The crushing of the unevenness becomes more remarkable as the ion implantation amount increases, and if the ion implantation dose amount is increased in order to reduce the resistance, the unevenness is crushed, resulting in a process contradiction.
【００１１】この発明は以上述べた問題点を除去するた
め、まず、ストレージノード部となる下層のポリシリコ
ン膜に不純物を導入し、その後粗面ポリシリコン膜を形
成して、その上に不純物を含んだ酸化膜（ＣＶＤ−Ｓｉ
Ｏ2 膜）を堆積させ、熱処理によりその酸化膜からの固
相拡散で前記粗面ポリシリコン膜に不純物を導入するこ
とにより、ストレージノード部への均一で充分な不純物
導入を行い、ストレージノード部の配線抵抗のばらつき
を小さくし、ストレージノードの空乏化を抑制し、ま
た、表面の凹凸状態を程良く保つようにし、良好なデバ
イス特性を得るスタックド・キャパシタセルを製造する
方法を提供することを目的とする。In order to eliminate the above-mentioned problems, the present invention first introduces impurities into a lower polysilicon film which will be a storage node portion, and thereafter forms a rough-surface polysilicon film, and then adds impurities onto it. Oxide film containing (CVD-Si
(O 2 film) is deposited and impurities are introduced into the rough-surface polysilicon film by solid-phase diffusion from the oxide film by heat treatment, so that uniform and sufficient introduction of impurities into the storage node part is performed. To provide a method of manufacturing a stacked capacitor cell in which variations in wiring resistance of the device are suppressed, depletion of a storage node is suppressed, and surface irregularities are maintained appropriately to obtain good device characteristics. To aim.
【００１２】[0012]
【課題を解決するための手段】この発明は前記目的達成
のため、ストレージノード部の下層となるポリシリコン
膜を生成した後に不純物の注入を１度行い、その後、粗
面ポリシリコン膜を生成し、その上にリンまたはヒ素を
高濃度に含んだＣＶＤ−ＳｉＯ2 膜を堆積させ、高温の
熱処理を施して、ＣＶＤ−ＳｉＯ2 膜からのリン（また
はヒ素）を粗面ポリシリコン膜中に固相拡散させるよう
にしたものである。In order to achieve the above-mentioned object, the present invention forms a polysilicon film as a lower layer of a storage node portion, then implants impurities once, and then forms a rough polysilicon film. Then, a CVD-SiO 2 film containing phosphorus or arsenic at a high concentration is deposited thereon, and high-temperature heat treatment is performed to solidify phosphorus (or arsenic) from the CVD-SiO 2 film in the rough surface polysilicon film. It is designed to cause phase diffusion.
【００１３】[0013]
【作用】本発明は前述したように、ストレージノード部
の下層ポリシリコン膜に一度不純物を導入し、その後、
粗面ポリシリコンを形成し、その上に不純物を含んだＣ
ＶＤ−ＳｉＯ2 膜を堆積させ、それからの固相拡散によ
って粗面ポリシリコン膜に不純物を注入するようにした
ので、粗面ポリシリコン膜にも均一に不純物が注入さ
れ、ストレージノード全体としても均一に不純物が注入
されることになり、配線抵抗を下げて、ストレージ・ノ
ードの空乏化を防止できる。また、不純物注入がイオン
注入法でなく、固相拡散によるから、粗面ポリシリコン
膜の表面の凹凸を潰すことはない。As described above, according to the present invention, impurities are once introduced into the lower polysilicon film of the storage node portion, and thereafter,
Rough surface polysilicon is formed and C containing impurities is formed on it.
Since the VD-SiO 2 film is deposited and the solid-phase diffusion from the VD-SiO 2 film is used to inject the impurities into the rough-surface polysilicon film, the impurities are evenly injected into the rough-surface polysilicon film, and the entire storage node is uniform. Impurities are injected into the semiconductor device, which lowers the wiring resistance and prevents depletion of the storage node. Further, since the impurity implantation is not by the ion implantation method but by solid phase diffusion, the irregularities on the surface of the rough surface polysilicon film are not crushed.
【００１４】[0014]
【実施例】図１は、本発明の一実施例の工程を示す断面
図である。以下、この図を参照して、一実施例の説明を
行うが、従来例の図２の（ｂ）までは、本実施例の場合
も全く同じであるため、図、説明共、省略する。従っ
て、図１の順序符号は（ｃ）から始める。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view showing a process of one embodiment of the present invention. Hereinafter, one embodiment will be described with reference to this figure. However, up to (b) of FIG. 2 of the conventional example is the same in this embodiment as well, and therefore the figure and description are omitted. Therefore, the order code in FIG. 1 starts from (c).
【００１５】図１（ｃ）に示すように、ストレージノー
ド部の下層のポリシリコン膜８に対して、まず、不純物
のドープをイオン注入で行う。ドープの条件はポリシリ
コン膜厚によっても異なってくるが、例えば、１０００
Åの膜厚の場合はヒ素（Ａｓ），４０ＫｅＶのエネルギ
ーで、５Ｅ１５ｃｍ-2程度のドーズ量が適当である。As shown in FIG. 1C, the polysilicon film 8 under the storage node portion is first doped with impurities by ion implantation. Although the doping conditions vary depending on the polysilicon film thickness, for example, 1000
In the case of a film thickness of Å, arsenic (As) and an energy of 40 KeV and a dose of about 5E15 cm -2 are suitable.
【００１６】続いて、図１（ｄ）に示すように、粗面ポ
リシリコン膜９を生成する。粗面ポリシリコン９の生成
条件は従来例に記したのと同じである。Then, as shown in FIG. 1D, a rough surface polysilicon film 9 is formed. The conditions for forming the rough surface polysilicon 9 are the same as those described in the conventional example.
【００１７】続いて、図１（ｅ）に示すように、粗面ポ
リシリコン膜９の上に、不純物としてリン（Ｐ）を含ん
だＣＶＤ−ＳｉＯ2 膜５１をＣＶＤ法で堆積させる。膜
厚は１０００〜２０００Å程度で、不純物濃度は、１６
ｗｔ％程度が適当である。その後、窒素雰囲気中で９０
０℃程度の熱処理を施し、ＣＶＤ−ＳｉＯ2 膜５１中に
含まれるリンを粗面ポリシリコン膜９に固相拡散させ
る。このとき、粗面ポリシリコン９を被膜しているＣＶ
Ｄ−ＳｉＯ2 膜５１は均一に被膜されているため、不純
物のリンも粗面ポリシリコン膜９に対して均一に拡散し
ていく。このため、粗面ポリシリコン膜９の不純物濃度
が均一になる。また、この熱処理により下層のポリシリ
コン８のアニール効果もある。熱処理後、フッ酸（Ｈ
Ｆ）溶液を用いてＣＶＤ−ＳｉＯ2 膜５１を完全に除去
する。Subsequently, as shown in FIG. 1E, a CVD-SiO 2 film 51 containing phosphorus (P) as an impurity is deposited on the rough surface polysilicon film 9 by the CVD method. The film thickness is about 1000 to 2000Å and the impurity concentration is 16
About wt% is appropriate. Then, in a nitrogen atmosphere, 90
A heat treatment is performed at about 0 ° C. to solid-phase diffuse phosphorus contained in the CVD-SiO 2 film 51 into the rough surface polysilicon film 9. At this time, the CV coating the rough surface polysilicon 9
Since the D-SiO 2 film 51 is uniformly coated, the impurity phosphorus also diffuses uniformly into the rough-surfaced polysilicon film 9. Therefore, the impurity concentration of the rough surface polysilicon film 9 becomes uniform. Further, this heat treatment has an effect of annealing the lower polysilicon layer 8. After heat treatment, hydrofluoric acid (H
F) The CVD-SiO 2 film 51 is completely removed using a solution.
【００１８】その後、図１（ｆ）に示すように、ホトリ
ソ・エッチング技術により従来同様ストレージノード部
８，９を形成し、ＳｉＮ膜のような誘電体膜（図（ｆ）
中に黒太線で図示）１０と、セルプレート１１を従来同
様、各々ＬＰＣＶＤ法で生成させて本実施例のＤＲＡＭ
のスタックド・キャパシタセルが得られる。Thereafter, as shown in FIG. 1F, the storage node portions 8 and 9 are formed by the photolithographic etching technique as in the conventional case, and a dielectric film such as a SiN film (FIG. 1F) is formed.
A black thick line 10) and a cell plate 11 are respectively formed by the LPCVD method as in the conventional case, and the DRAM of this embodiment is formed.
The stacked capacitor cell of is obtained.
【００１９】なお、この例では、下層ポリシリコン８へ
の不純物ドープを、ヒ素のインプラで行うと記したが、
この不純物ドープは、リンのインプラ、ＰＯＣｌ3 ガス
による熱拡散で行ってもかまわない。In this example, it is described that the lower polysilicon layer 8 is doped with impurities by arsenic implantation.
This impurity doping may be performed by phosphorus implantation or thermal diffusion using POCl 3 gas.
【００２０】[0020]
【発明の効果】以上、詳述したように、この発明の方法
では、粗面ポリシリコン膜を用いたＤＲＡＭのスタック
キャパシタにおいて、ストレージノードを構成するポリ
シリコンのうち、下層ポリシリコンには、イオン注入法
により充分な不純物ドープを行い、粗面ポリシリコン膜
にはリンを含んだＣＶＤ−ＳｉＯ2 からの固相拡散によ
る不純物ドープを行うようにしたので、ストレージノー
ド部が均一な不純物ドープとなり、配線抵抗の低下、そ
のばらつきの抑制、キャパシタの空乏化を抑制すること
ができる。更に粗面ポリシリコン膜への不純物ドープが
固相拡散に依るため、粗面粒の潰れが起きず、良好な凹
凸形状を保ち、キャパシタ面積の増加が期待できる。As described above in detail, according to the method of the present invention, in the stack capacitor of the DRAM using the rough surface polysilicon film, the lower layer polysilicon among the polysilicon forming the storage node is an ion. Sufficient impurity doping was performed by the implantation method, and the rough surface polysilicon film was doped with impurities by solid phase diffusion from CVD-SiO 2 containing phosphorus. It is possible to suppress a decrease in wiring resistance, suppression of variations in the resistance, and depletion of capacitors. Furthermore, since the impurity doping into the rough surface polysilicon film depends on the solid phase diffusion, the rough surface grains are not crushed, a good uneven shape is maintained, and an increase in the capacitor area can be expected.
【図１】本発明の実施例の工程説明図。FIG. 1 is a process explanatory diagram of an example of the present invention.
【図２】従来例の工程説明図。FIG. 2 is a process explanatory view of a conventional example.
１ 基板 ８ 下層ポリシリコン膜 ９ 粗面ポリシリコン膜 ５１ ＣＶＤ−ＳｉＯ2 膜1 Substrate 8 Lower Polysilicon Film 9 Rough Polysilicon Film 51 CVD-SiO 2 Film
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/822 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 21/822
Claims (2)
る、該キャパシタ部のストレージノード部の形成方法と
して、 （ａ）半導体基板上に、前記ストレージノード部の下層
となる第１の導電性膜を形成し、該第１の導電性膜に不
純物を導入する工程と、 （ｂ）前記不純物を導入した第１の導電性膜の上に、形
状が粗面となるよう第２の導電性膜を形成する工程と、 （ｃ）前記粗面の第２の導電性膜の上に、不純物を含ん
だ膜を堆積し、熱処理により、該不純物を含んだ膜から
の固相拡散により、前記粗面の第２の導電性膜に不純物
を導入する工程と、 （ｄ）該不純物を含んだ膜を除去する工程と、 を含むことを特徴とする半導体装置の製造方法。1. A method for forming a storage node portion of a capacitor portion in a semiconductor device having a capacitor portion includes: (a) forming a first conductive film as a lower layer of the storage node portion on a semiconductor substrate. A step of introducing impurities into the first conductive film, and (b) forming a second conductive film having a rough surface on the first conductive film containing the impurities. And (c) depositing a film containing impurities on the second conductive film on the rough surface, and subjecting the film to solid phase diffusion from the film containing impurities by heat treatment to form a film on the second conductive film on the rough surface. 2. A method of manufacturing a semiconductor device, comprising: a step of introducing an impurity into the conductive film of 2; and (d) a step of removing the film containing the impurity.
ポリシリコン膜とすることを特徴とする請求項１記載の
半導体装置の製造方法。2. Both the first and second conductive films,
The method for manufacturing a semiconductor device according to claim 1, wherein the method is a polysilicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5231540A JPH0786434A (en) | 1993-09-17 | 1993-09-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5231540A JPH0786434A (en) | 1993-09-17 | 1993-09-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0786434A true JPH0786434A (en) | 1995-03-31 |
Family
ID=16925103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5231540A Pending JPH0786434A (en) | 1993-09-17 | 1993-09-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0786434A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5798545A (en) * | 1994-12-28 | 1998-08-25 | Nippon Steel Corporation | Semiconductor storage device |
| US6194758B1 (en) | 1997-12-24 | 2001-02-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device comprising capacitor and method of fabricating the same |
| US6632721B1 (en) | 1999-07-06 | 2003-10-14 | Hitachi, Ltd. | Method of manufacturing semiconductor devices having capacitors with electrode including hemispherical grains |
-
1993
- 1993-09-17 JP JP5231540A patent/JPH0786434A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5798545A (en) * | 1994-12-28 | 1998-08-25 | Nippon Steel Corporation | Semiconductor storage device |
| US6194758B1 (en) | 1997-12-24 | 2001-02-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device comprising capacitor and method of fabricating the same |
| US6940116B2 (en) | 1997-12-24 | 2005-09-06 | Renesas Technology Corp. | Semiconductor device comprising a highly-reliable, constant capacitance capacitor |
| US7368776B2 (en) | 1997-12-24 | 2008-05-06 | Renesas Technology Corp. | Semiconductor device comprising a highly-reliable, constant capacitance capacitor |
| US7439132B2 (en) | 1997-12-24 | 2008-10-21 | Renesas Technology Corp. | Semiconductor device comprising capacitor and method of fabricating the same |
| US7754562B2 (en) | 1997-12-24 | 2010-07-13 | Renesas Technology Corp. | Semiconductor device comprising capacitor and method of fabricating the same |
| US7795648B2 (en) | 1997-12-24 | 2010-09-14 | Renesas Technology Corporation | Semiconductor device comprising capacitor and method of fabricating the same |
| US7816204B2 (en) | 1997-12-24 | 2010-10-19 | Renesas Technology Corp. | Semiconductor device comprising capacitor and method of fabricating the same |
| US8471321B2 (en) | 1997-12-24 | 2013-06-25 | Renesas Electronics Corporation | Semiconductor device comprising capacitor and method of fabricating the same |
| US8759891B2 (en) | 1997-12-24 | 2014-06-24 | Renesas Electronics Corporation | Semiconductor device comprising capacitor and method of fabricating the same |
| US6632721B1 (en) | 1999-07-06 | 2003-10-14 | Hitachi, Ltd. | Method of manufacturing semiconductor devices having capacitors with electrode including hemispherical grains |
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