JPH1093077A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent deterioration of MOSFET characteristics due to reduction of a gate capacity of a MOSFET caused by the increased thickness of a gate oxide film and which can eliminate such a drawback that a variation in the work function of a gate electrode causes variation in a voltage Vth or increase of a contact or sheet resistance by preventing interdiffusion of impurities, and a method for manufacturing the semiconductor device. SOLUTION: A semiconductor device has a gate electrode 20 of a tungsten polycide structure, using an N<+> -type polysilicon layer. N<+> -type polysilicon layer is made up of two films, at least one of which is made of polysililicon of grains having large diameters. The formation of the large grain-diameter polysilicon is carried out by depositing an amorphous silicon layer 16 at a temperature of 550 deg.C or less and then annealing the amorphous silicon layer 16 at a temperature of 800 deg.C or less for one hour or more.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the, N ⁺ -type semiconductor device and manufacturing method thereof having a gate electrode of polysilicon tungsten polycide structure using, and N ⁺ -type polysilicon of tungsten polycide structure using The present invention relates to a semiconductor device having a gate electrode and having a buried contact electrically connected to the gate electrode, and a method for manufacturing the same.

[0002]

BACKGROUND ART Tungsten silicide (WSi _x) and tungsten polycide (W polycide) formed by stacked structure of a polysilicon (Poly-Si) wiring structure is excellent in and thermal stability and low resistance Therefore, MOS
Widely used in devices, bipolar devices and the like. In particular, MOS devices are often used as gate electrodes because they have excellent threshold voltage (Vth) control while ensuring gate oxide film reliability. When the W polycide structure is used as the gate electrode, the polysilicon can be doped with an N-type impurity such as phosphorus because it can be doped at a high concentration and is thermally stable. It is common to use N ⁺ type.

[0003] As a method of depositing tungsten silicide, there are a sputtering method and a CVD method, but the CVD method is usually used because a film having excellent step coverage and low resistance can be formed. As a method of depositing tungsten silicide by such a CVD method, in particular, a CVD method under reduced pressure using SiH ₄ and WF ₆ as raw materials (reduced pressure chemical vapor deposition method, hereinafter referred to as reduced pressure CVD method). General.

As a structure for making contact between the gate electrode and the diffusion layer, a buried contact (Buried contact) is used.
Contact) is known. In order to form such a buried contact structure, first, FIG.
1A, a first polysilicon layer 3 is formed on a gate oxide film 2 formed on the surface of a silicon substrate 1, and the first polysilicon layer 3 and the gate oxide film 2 are etched to form a buried contact. An opening 4 is formed in the region.

[0005] Next, second layer polysilicon layer, to obtain a W polycide layer is deposited forming the WSi _x layer in this order, and further patterning the W polycide layer by etching, more as shown in FIG. 3 (b) Eye polysilicon layer 3,
Obtaining a gate electrode 7 of the W polycide structure consisting of the second layer polysilicon layer 5, WSi _x layer 6. Next, MOSFE
A diffusion layer region is formed when forming a T (MOS field effect transistor). After that, by heat treatment, FIG.
As shown in (c), the dopant in the polysilicon layer 5 and the dopant in the diffusion layer 8 are diffused and brought into contact with each other to obtain a buried contact 9 for electrically connecting the gate electrode 7 and the diffusion layer 8.

[0006]

[0007] Incidentally, in the semiconductor device formed by deposition of tungsten silicide (WSi _x) by a low pressure CVD method above, 1 × 10 ²⁰ pieces in WSi _x film formed by low pressure CVD / cm It is known that ^three or more fluorine atoms are contained.
However, when a high concentration of fluorine is contained in the gate electrode, fluorine diffuses into the gate oxide film by a high-temperature heat treatment at about 800 ° C. or more, and the thickness of the gate oxide film increases. Therefore, the gate capacitance of the MOSFET is reduced, the MOSFET characteristics are reduced, and the LSI operation is also reduced.

In the semiconductor device having the buried contact 9 shown in FIG. 3C, for example, the semiconductor device is a stack type SR in which thin film transistors (TFTs) are stacked.
If the AM and a capacitor which is stacked DRAM stacked, usually, the contact 10a of the polysilicon wiring 10 over WSi _x layer 6 as shown in FIG. 4 is formed. In this case, when the polysilicon wiring 10 in FIG. 4 is a P-type, and P-type impurity of N-type impurities and the polysilicon wire 10 in WSi _x layer 6 gate electrode 7 and diffusion layers 8 via the Are mutually diffused and compensate each other. When such compensation by interdiffusion occurs, the work function of the gate electrode 7 changes, so that Vth fluctuates and contact resistance and sheet resistance increase.

The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the gate capacitance of a MOSFET due to an increase in the thickness of a gate oxide film.
A semiconductor device in which MOSFET characteristics are prevented from deteriorating, and a method of manufacturing the same. Also, a work function of a gate electrode is prevented by preventing interdiffusion of impurities, so that Vth fluctuates and contact resistance and sheet resistance increase. An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which prevent inconvenience.

[0009]

Means for Solving the Problems Claim 1 of the present invention
In the semiconductor device according includes a gate electrode of a tungsten polycide structure using the N ⁺ -type polysilicon, N ⁺ -type polysilicon layer is formed on the two-layer structure, these two
At least one of the layers is formed of large-grain polysilicon, which is a means for solving the above-mentioned problem. According to this semiconductor device, since at least one of the N ⁺ -type polysilicon layers having the two-layer structure is formed of large-grain polysilicon, diffusion of fluorine from tungsten silicide in the tungsten polycide structure is suppressed. It is suppressed by large-grain polysilicon, which suppresses diffusion of fluorine into the gate oxide film.

According to a fourth aspect of the present invention, there is provided a semiconductor device having a gate electrode of a tungsten polycide structure using N ⁺ type polysilicon, and having a buried contact for electrically connecting the gate electrode to a diffusion layer. The solution to the above-mentioned problem is that an N ⁺ type polysilicon layer is formed in a two-layer structure, and at least one of the two layers is formed of large-grain polysilicon. According to this semiconductor device, since at least one of the N ⁺ -type polysilicon layers having a two-layer structure is formed of large-grain polysilicon, for example, a polysilicon wiring into which a P-type impurity is introduced is connected to the gate electrode. N, which occurs through tungsten silicide in a tungsten polycide structure when connected to
Inter-diffusion between the p-type impurity and the p-type impurity is suppressed by the large-grain polysilicon, thereby suppressing a change in the work function of the gate electrode and an increase in contact resistance and sheet resistance.

[0011] In these semiconductor devices, tungsten silicide is a CV having SiH ₄ as a source gas.
It is preferable that the tungsten silicide is formed by the method D. By forming the tungsten silicide by such a CVD method, the tungsten silicide becomes a film having excellent step coverage and low resistance. In these semiconductor devices,
It is preferable that the impurity concentration of the upper polysilicon layer in the N ⁺ type polysilicon layer is formed lower than the impurity concentration of the lower polysilicon layer. Thus, the impurity concentration of the upper polysilicon layer is lower than that of the lower polysilicon layer. By being formed lower than the impurity concentration of the polysilicon layer, diffusion of impurities from the N ⁺ type polysilicon layer to tungsten silicide can be suppressed.

7. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor device has a gate electrode of a tungsten polycide structure using N ⁺ type polysilicon.
^{As a} step of forming ⁺ -type polysilicon, a step of depositing amorphous silicon at a deposition temperature of 550 ° C. or lower by a CVD method, and annealing the amorphous silicon at a temperature of 800 ° C. or lower for 1 hour or more, thereby forming the amorphous silicon into large grains. And a step of performing solid phase growth on polysilicon having a diameter. According to the method of manufacturing a semiconductor device, the diffusion of fluorine from tungsten silicide in the tungsten polycide structure is suppressed by the large-grain polysilicon by increasing the diameter of the deposited amorphous silicon, thereby forming a gate oxide film. It is possible to suppress the diffusion of fluorine into the silicon.

According to a ninth aspect of the present invention, there is provided a semiconductor device having a gate electrode of a tungsten polycide structure using N ⁺ type polysilicon and having a buried contact for electrically connecting the gate electrode to a diffusion layer. In the method for manufacturing an apparatus, as a step of forming the N ⁺ type polysilicon, a step of depositing amorphous silicon at a deposition temperature of 550 ° C. or lower by a CVD method, and annealing the amorphous silicon at a temperature of 800 ° C. or lower for 1 hour or more. And a step of solid-phase growing the amorphous silicon into large-grain polysilicon. According to this method of manufacturing a semiconductor device, the deposited amorphous silicon is made to have a large particle size,
For example, when a polysilicon wiring in which a P-type impurity is introduced is connected to a gate electrode, interdiffusion between an N-type impurity and a P-type impurity caused through tungsten silicide in a tungsten polycide structure is suppressed by large-grain polysilicon. It becomes possible to do.

In the method of manufacturing a semiconductor device, it is preferable that after the amorphous silicon is deposited, phosphorus or arsenic is ion-implanted into the amorphous silicon before the amorphous silicon is annealed to be N ⁺ type. . By implanting the impurities in this way, the polysilicon layer obtained after the annealing can be further increased in grain size.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on a method for manufacturing a semiconductor device. (First Embodiment) In this embodiment, a method of manufacturing a semiconductor device provided with a gate electrode having a W polycide structure using N ⁺ type polysilicon will be described. As shown in FIG. 1A, first, for example, 950
LOCOS (Local Oxidation of
A field oxide film 12 serving as an element isolation region is formed by a silicon (Si) method. Next, a P-type well region (not shown) is formed by ion implantation or the like in a region where an NMOSFET (N-channel MOS field-effect transistor) is to be formed, and a buried layer (not shown) for preventing punch-through of the transistor is formed. (Not shown). further,
Ion implantation for adjusting the threshold voltage Vth of the transistor is performed to form the NMOS channel region 13.

Then, a gate is formed on the exposed surface of the silicon substrate 11 as shown in FIG. 1B by a thermal oxidation method (for example, a pyrogenic oxidation method in an atmosphere consisting of hydrogen and oxygen at 850 ° C.). The oxide film 14 is, for example, 8n
m. Subsequently, the polysilicon is reduced to a thickness of, for example, 50 nm at a deposition temperature of 620 ° C. by a CVD method under reduced pressure using SiH ₄ as a source gas (reduced pressure chemical vapor deposition, hereinafter referred to as reduced pressure CVD method). The first polysilicon layer 15 is deposited to be a lower polysilicon layer in the present invention.

Next, on this first polysilicon layer 15, a low pressure CVD method using SiH ₄ as a source gas is performed.
At a deposition temperature of 550 ° C., the amorphous silicon layer 16 is deposited to a thickness of, for example, 50 nm. Then, at 650 ° C,
Annealing is performed for 10 hours to crystallize the amorphous silicon layer 16, and as shown in FIG. 1C, solidify the amorphous silicon layer 16 into particles having a larger particle size than the particles forming the first polysilicon layer 15 formed earlier. A second polysilicon layer 17 is formed by phase growth.

Next, the first polysilicon layer 15 and the second polysilicon layer 17 are doped with phosphorus by performing a heat treatment at 830 ° C. in POCl ₃ , whereby the first polysilicon layer 15 and the second polysilicon layer 15 are doped. Each of the first polysilicon layers 17 is an N ⁺ type polysilicon layer.

[0019] Then, on the second layer polysilicon layer 17, depositing a WF ₆ / SiH ₄ by a low pressure CVD method using a raw material gas at a deposition temperature 380 ° C., a WSi _x layer 18 to a thickness of, for example, 70nm Form. In addition, S
By a CVD method using iH ₄ / O ₂ as a source gas, a SiO ₂ layer (not shown) having a thickness of 1
50nm to deposit formation, obtained first layer polysilicon layer 15, second layer polysilicon layer 17, WSi _x layer 18, made of SiO ₂ layer offset oxide film with a W polycide wiring layer (not shown).

Next, a resist pattern (not shown) is formed by a known lithography method, and the resist pattern is used as a mask to perform anisotropic etching using, for example, a fluorocarbon gas, as shown in FIG. Then, a gate electrode pattern 19 of SiO ₂ is formed.
Then, by anisotropic etching using the gate electrode patterns 19 of SiO ₂ as a mask (e.g., ECR etching using Cl ₂ / O ₂ gas), WSi _x layer 18, second layer polysilicon layer 17, first layer polysilicon layer 15 Is etched to form a gate electrode pattern 20 including the SiO ₂ gate electrode pattern 19 as shown in FIG.

[0021] Then, the As ⁺ an acceleration energy of 2
Ion implantation is performed under the conditions of 0 keV and a dose of 5 × 10 ¹³ / cm ² , and as shown in FIG.
That is, the NLDD region 21 is formed. Then, decompression C
An SiO ₂ layer (not shown) is deposited and formed to a thickness of 150 nm by the VD method, and then the SiO ₂ layer is anisotropically etched to form a sidewall 22. Subsequently, for example, As ⁺ is ion-implanted into the NMOS channel region 13 under the conditions of an acceleration energy of 20 keV and a dose of 3 × 10 ¹⁵ / cm ² , and the N-type source / drain region 23
To form

Next, the impurity is activated by RTA (Rapid Tharmal Anneal) under the conditions of 1000 ° C. for 10 seconds, and then the gate, source, drain, etc. are formed by using an interlayer insulating film formation, contact hole formation, wiring material such as Al. Wiring is performed to obtain a semiconductor device.

In the semiconductor device obtained in this manner, since the second polysilicon layer 17 is formed of large grain polysilicon, the WS in the W polycide structure is not used.
fluorine diffusion from i _x layer 18 is suppressed by the large grain polysilicon, thereby diffusion of fluorine into the gate oxide film 14 is suppressed, therefore the MOSFET due to the increase in the thickness of the gate oxide film 14 The gate capacitance is reduced and the MOSFET characteristics are prevented from deteriorating.
Further, since the WSi _x layer 18 is formed by low pressure CVD method using WF ₆ / SiH ₄ as a raw material gas, the WS
i _x layer 18 has a good step coverage, and low-resistance film.

Further, in such a method of manufacturing a semiconductor device, the diffusion of fluorine from W silicide in the W polycide structure is reduced by annealing the deposited amorphous silicon layer to increase the particle size. The diameter can be suppressed by polysilicon, whereby the diffusion of fluorine into the gate oxide film can be suppressed. Therefore, the gate capacitance of the MOSFET decreases due to the increase in the thickness of the gate oxide film 14, and the MOSFET characteristics deteriorate. Can be prevented.

In this semiconductor device, the first polysilicon layer 15 and the second polysilicon layer 17 are simultaneously doped with phosphorus to make them N ⁺ -type, but these are separately doped. Of course,
In this case, the N ⁺ -type layer is formed such that the impurity concentration of the upper polysilicon layer, that is, the second polysilicon layer 17 is lower than that of the lower polysilicon layer (first polysilicon layer 15). preferable for suppressing the diffusion of impurities into the WSi _x layer 18 from polysilicon layers 15 and 17.

(Second Embodiment) In this embodiment, a gate electrode having a W polycide structure using N ⁺ type polysilicon is provided, and a buried contact for electrically connecting the gate electrode to the diffusion layer is provided. A method for manufacturing a semiconductor device will be described. First, a field oxide film (not shown) is formed on the surface of the silicon substrate in the same manner as in the first embodiment, and then ion implantation is performed on a region where an NMOSFET (N-channel type MOS field effect transistor) is to be formed. A P-type well region (not shown) is formed by a method or the like, and a buried layer (not shown) for preventing punch-through of the transistor is formed. Further, ion implantation for adjusting the threshold voltage Vth of the transistor is performed, and N
A MOS channel region (not shown) is formed.

Next, a gate oxide film 31 is formed to a thickness of, for example, 8 nm on the exposed surface of the silicon substrate 30 as shown in FIG. 2A by the same thermal oxidation method as in the first embodiment. I do. Subsequently, polysilicon is deposited to a thickness of, for example, 50 nm at a deposition temperature of 620 ° C. by a low pressure CVD method using SiH ₄ as a source gas, and the first polysilicon layer 32 serving as a lower polysilicon layer in the present invention is formed. To form Then, by performing a heat treatment at 830 ° C. in POCl ₃ , the first polysilicon layer 32 is doped with phosphorus, whereby the first polysilicon layer 32 becomes an N ⁺ type polysilicon layer. As for doping of the first polysilicon layer 32 with phosphorus, a method of doping phosphorus at the time of CVD may be adopted instead of such a method of vapor phase diffusion.

Next, using the resist pattern formed by the coating technique and the lithography technique as a mask (not shown), the first polysilicon 32 is anisotropically etched using, for example, Cl ₂ / O ₂ as an etching gas. For example, the gate oxide film 31 is anisotropically etched using fluorocarbon as an etching gas, and an opening 33 is formed in a buried contact formation region as shown in FIG.
Then, as shown in FIG. 2 (c), an amorphous silicon layer 34 having a thickness of, for example, 50 nm is deposited on the first polysilicon layer 32 at a deposition temperature of 550 ° C. by a low pressure CVD method using SiH ₄ as a source gas. Deposited on Subsequently, for example, an acceleration energy of 1
Phosphorus is ion-implanted under the conditions of 0 keV and a dose of 3 × 10 ¹⁵ / cm ² . By such ion implantation, the amorphous silicon has a more amorphous structure.

Next, annealing is performed at 650 ° C. for 10 hours to crystallize the amorphous silicon layer 34, and solidify the amorphous silicon layer 34 into particles having a larger particle diameter than the particles forming the first polysilicon layer 32. The second polysilicon layer 35 is formed by growing. Subsequently, RTA is performed at 1000 ° C. for 10 seconds to diffuse phosphorus on the surface of the second polysilicon layer 35 into the polysilicon layer 35 and activate the same to activate the second polysilicon layer 35. Is set so that the impurity concentration is lower than the impurity concentration of the first polysilicon layer 32. Here, since phosphorus ions are implanted into the amorphous silicon layer 34 first, the second polysilicon layer 35 obtained after annealing is much more than the second polysilicon layer 17 of the first embodiment. It has a large particle size.

[0030] Next, FIG. 2 (d) in the same manner as the first embodiment as shown is deposited on the WSi _x layer 36, for example, 70nm thick, further SiO ₂ layer on top of this (not shown) Is deposited to a thickness of, for example, 150 nm, thereby forming the first polysilicon layer 32 and the second polysilicon layer 3.
5, obtained WSi _x layer 36, made of SiO ₂ layer offset oxide film with a W polycide wiring layer (not shown). Subsequently, a resist pattern (not shown) is formed by a known lithography method, and using this resist pattern as a mask, for example, anisotropic etching using a fluorocarbon-based gas is performed, as shown in FIG. _Two
The gate electrode pattern 37 is formed.

Next, as in the first embodiment, S
by anisotropic etching of the gate electrode pattern 37 and the mask iO ₂ (e.g. ECR etching using Cl ₂ / O ₂ gas), composed of WSi _x layer 36, second layer polysilicon layer 35, first layer polysilicon layer 32 The W polycide is etched and the SiO 2 is etched as shown in FIG.
A gate electrode pattern including the _second gate electrode pattern 37 is formed. At this time, the gate electrode pattern 38 is formed in the opening 33 in the formation region of the buried contact.
The silicon substrate 30 is dug in the position where there is no.

Subsequently, an NLDD region (not shown), a PLD
A D region (not shown) and a side wall (not shown) are formed, and for example, an A channel is formed in an NMOS channel region (not shown).
s ⁺ acceleration energy 20 keV, dose 3 × 10 ¹⁵
Ions are implanted under the condition of pcs / cm ² to form N-type source / drain regions (not shown). Next, as shown in FIG. 2 (f), SiO ₂ is deposited to a thickness of about 200 nm to form an interlayer insulating film 39, and the contact hole 4 is formed by a known lithography technique and anisotropic etching technique.
0 is formed.

Next, a reduced pressure C using SiH ₄ as a raw material gas.
At a deposition temperature of 620 ° C., polysilicon is deposited to a thickness of, for example, 50 nm by a VD method, and B ⁺ is added to the polysilicon at an acceleration energy of 10 keV and a dose of 4 × 1.
Ions are implanted under the condition of 0 ¹⁵ / cm ² . Subsequently, the P ⁺ -type polysilicon is ion-implanted and patterned by a known lithography technique and etching technique to form a P ⁺ -type polysilicon wiring 41.

Next, the impurity is activated by RTA at 1000 ° C. for 10 seconds. Then, in the buried contact portion, phosphorus (P) of the first-layer polysilicon 32 diffuses into the silicon substrate 30, whereby the first-layer polysilicon 32 and the source / drain regions (diffusion layers) 4 are diffused.
Thus, a buried contact 43 for electrically connecting the buried contacts 2 is obtained. Thereafter, a semiconductor device is obtained through various processing steps that are usually performed.

In the semiconductor device thus obtained, since the second polysilicon layer 35 is formed of large grain polysilicon, a P ⁺ type polysilicon wiring is formed on the gate electrode pattern 38. be connected, mutual diffusion being suppressed by large grain polysilicon with N-type impurities and P type impurities occur via WSi _x layer 36 in the W polycide structure, thus the work function of the gate electrode is changed And increase in contact resistance and sheet resistance is suppressed.

Further, since the WSi _x layer 36 as in the first embodiment is formed by low pressure CVD method using WF ₆ / SiH ₄ as a raw material gas, the WSi _x layer 36 is excellent in step coverage, In addition, the film has a low resistance.
The impurity concentration of the two-layer polysilicon layer 35, even more because it is formed lower than the impurity concentration of the first poly-silicon layer 32, the diffusion of impurities further suppressed from N ⁺ -type polysilicon layer into WSi _x layer 36 Can be

Further, in such a method of manufacturing a semiconductor device, by increasing the grain size of the deposited amorphous silicon, when the P ⁺ type polysilicon wiring 41 is connected to the gate electrode pattern 38, the mutual diffusion of N type impurities and P type impurities occur via WSi _x layer 36 in the polycide structure can be suppressed by large grain polysilicon, thus the work function may change the gate electrode, Ya contact resistance An increase in sheet resistance can be suppressed. Also, in this manufacturing method,
After depositing the amorphous silicon, since the N ⁺ -type by phosphorus ion implanted into the amorphous silicon layer 34 prior to annealing the amorphous silicon layer 34, further large polysilicon layer obtained after annealing The diameter can be increased.

[0038]

As described above, the semiconductor device according to the first aspect of the present invention has a structure in which at least one of the N ⁺ -type polysilicon layers having a two-layer structure is formed of large-grain polysilicon. Therefore, diffusion of fluorine from tungsten silicide in the tungsten polycide structure is suppressed by the large-grain polysilicon, whereby diffusion of fluorine into the gate oxide film is suppressed. Therefore,
The thickness of the gate oxide film does not increase due to the diffusion of fluorine into the gate oxide film.
It is possible to prevent the disadvantage that the gate capacitance of the SFET is reduced, the MOSFET characteristics are reduced, and the LSI operation is also reduced.

According to a fourth aspect of the present invention, since at least one of the N ⁺ -type polysilicon layers having a two-layer structure is formed of large-grain polysilicon, for example, a P-type impurity is introduced. When the polysilicon wiring is connected to the gate electrode, the interdiffusion between the N-type impurity and the P-type impurity caused through the tungsten silicide in the tungsten polycide structure is suppressed by the large-grain polysilicon, whereby the gate electrode , And increase in contact resistance and sheet resistance are suppressed.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
Since the deposited amorphous silicon has a large grain size, the diffusion of fluorine from tungsten silicide in the tungsten polycide structure is suppressed by the large grain size polysilicon, thereby suppressing the diffusion of fluorine to the gate oxide film. Reduction of gate capacitance in MOSFET and MO
It is possible to prevent a decrease in SFET characteristics and the like.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
Since the deposited amorphous silicon has a large grain size, for example, when a polysilicon wiring into which a P-type impurity is introduced is connected to a gate electrode, N-type impurities and P-type impurities generated through tungsten silicide in a tungsten polycide structure are generated. Interdiffusion with the type impurity can be suppressed by the large-grain polysilicon, whereby Vth changes due to a change in the work function of the gate electrode,
An increase in contact resistance and sheet resistance can be suppressed. In particular, the buried contact can be formed without increasing the number of steps, and the above-described effect can be obtained.

[Brief description of the drawings]

FIGS. 1A to 1F are cross-sectional views of essential parts for explaining a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.

FIGS. 2A to 2F are cross-sectional views of a main part for describing a second embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.

FIGS. 3A to 3C are cross-sectional views of a main part for explaining an example of a conventional method of manufacturing a semiconductor device in the order of steps.

FIG. 4 is a side sectional view showing a main part of an example of a conventional semiconductor device.

[Explanation of symbols]

11,30 silicon substrate 15, 32 first layer polysilicon layer (underlying the polysilicon layer) 16, 34 amorphous silicon layer 17, 34 second layer polysilicon layer (upper layer of the polysilicon layer) 18, 36 WSi _x layer 20, 38 gate electrode pattern (gate electrode) 42 source / drain region (diffusion layer) 43 buried contact

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[Procedure amendment]

[Submission date] November 5, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

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[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0029

[Correction method] Change

[Correction contents]

Next, annealing is performed at 650 ° C. for 10 hours to crystallize the amorphous silicon layer 34, and solidify the amorphous silicon layer 34 into particles having a larger particle diameter than the particles forming the first polysilicon layer 32. The second polysilicon layer 35 is formed by growing. Subsequently, RTA is performed at 1000 ° C. for 10 seconds to diffuse phosphorus on the surface of the second polysilicon layer 35 into the polysilicon layer 35 and activate the same to activate the second polysilicon layer 35. Is set so that the impurity concentration is lower than the impurity concentration of the first polysilicon layer 32. Here, since phosphorus ions are implanted into the amorphous silicon layer 34 first, the second polysilicon layer 35 obtained after annealing is much more than the second polysilicon layer 17 of the first embodiment. It has a large particle size. Further, due to such RTA, phosphorus on the surface of the second polysilicon layer 35 is removed from the opening 33.
And diffuses into the surface portion of the silicon substrate 30, thereby forming the impurity diffusion layer 44 in the surface portion of the silicon substrate 30.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction contents]

Next, the impurity is activated by RTA at 1000 ° C. for 10 seconds. Then, in the buried contact portion, the impurity in the source / drain region (diffusion layer) 42 diffuses into the silicon substrate 30, whereby the buried contact electrically connects the impurity region 44 and the source / drain region (diffusion layer) 42. Contact 43
Is obtained. Thereafter, a semiconductor device is obtained through various processing steps that are usually performed.

[Procedure amendment 4]

[Document name to be amended] Drawing

[Correction target item name] Figure 2

[Correction method] Change

[Correction contents]

FIG. 2

Claims (10)

[Claims] 1. A semiconductor device provided with a gate electrode having a tungsten polycide structure using N ⁺ -type polysilicon, wherein an N ⁺ -type polysilicon layer is formed in a two-layer structure, and at least one of these two layers is formed. A semiconductor device, wherein one layer is formed of large grain polysilicon. 2. The semiconductor device according to claim 1, wherein the tungsten silicide is formed by a CVD method using SiH ₄ as a source gas. 3. The semiconductor device according to claim 1, wherein an impurity concentration of an upper polysilicon layer in the two-layered N ⁺ type polysilicon layer is lower than an impurity concentration of a lower polysilicon layer. 13. The semiconductor device according to claim 1. Wherein a gate electrode of a tungsten polycide structure using the N ⁺ -type polysilicon and the semiconductor device having a buried contact electrically connecting the said gate electrode diffusion layer, the N ⁺ poly A semiconductor device, wherein a silicon layer is formed in a two-layer structure, and at least one of the two layers is formed of large-grain polysilicon. 5. The semiconductor device according to claim 2, wherein the tungsten silicide is formed by a CVD method using SiH ₄ as a source gas. 6. An impurity concentration of an upper polysilicon layer of the two-layered N ⁺ type polysilicon layer is lower than an impurity concentration of a lower polysilicon layer. 13. The semiconductor device according to claim 1. 7. A manufacturing method of a semiconductor device having a gate electrode of a tungsten polycide structure using the N ⁺ -type polysilicon, as the step of forming the N ⁺ -type polysilicon, at a deposition temperature 550 ° C. or less by CVD Depositing amorphous silicon and annealing the amorphous silicon at a temperature of 800 ° C. or less for 1 hour or more to solid-phase grow the amorphous silicon into large-grain polysilicon. Semiconductor device manufacturing method. As claimed in claim 8, wherein said N ⁺ -type polysilicon forming process, between the annealing step and the amorphous silicon to deposit the amorphous silicon and the N ⁺ -type by phosphorus or arsenic is ion-implanted into the amorphous silicon The method for manufacturing a semiconductor device according to claim 7, further comprising a step. 9. A method for manufacturing a semiconductor device, comprising: a gate electrode having a tungsten polycide structure using N ⁺ type polysilicon; and a buried contact for electrically connecting the gate electrode to a diffusion layer. As a step of forming N ⁺ -type polysilicon, a step of depositing amorphous silicon at a deposition temperature of 550 ° C. or lower by a CVD method, and annealing the amorphous silicon at a temperature of 800 ° C. or lower for 1 hour or more, thereby increasing the amorphous silicon. A method of solid phase growth on polysilicon having a grain size. 10. The method of forming an N ⁺ -type polysilicon, wherein between the step of depositing amorphous silicon and the step of annealing the amorphous silicon, phosphorus or arsenic is ion-implanted into the amorphous silicon to be N ⁺ -type. The method for manufacturing a semiconductor device according to claim 9, further comprising a step.