JP2006287238A - Flip-flop circuit and static ram employing it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit of a multilayer structure in which interconnection of an upper layer thin film transistor (TFT) and a lower layer transistor is formed with good yield. <P>SOLUTION: First TFT and second TFT are provided, respectively, on first and second transistors, an interconnect line of the gate of first transistor and the drain of the second transistor are connected electrically through the interconnect line of the gate of first TFT, the interconnect line of the gate of second transistor and the drain of the first transistor are connected electrically through the interconnect line of the gate of second TFT, the drain of the first TFT and the interconnect line of the gate of second TFT are connected electrically through a first interconnect line, and the drain of the second TFT and the interconnect line of the gate of first TFT are connected electrically through a second interconnect line. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit using an insulating gate type field effect transistor (TFT) formed on an insulating surface such as an insulating material such as glass or silicon oxide provided on a silicon wafer. The present invention relates to an integrated circuit using a multilayer transistor (also referred to as a multilayer semiconductor integrated circuit, a three-dimensional semiconductor integrated circuit, or a three-dimensional semiconductor integrated circuit). The present invention relates to a field effect transistor provided on a semiconductor surface, a transistor using a TFT as a second layer transistor, and a transistor using a TFT as a first layer and a second layer transistor.

  In recent years, in order to improve the integration degree of a semiconductor integrated circuit, a multilayer integrated circuit having a multilayer structure of the integrated circuit has been proposed. As such a multilayer integrated circuit, a first semiconductor element layer is formed on a single crystal substrate such as a silicon wafer, and a second semiconductor element layer is formed thereon using a TFT. It is. In this way, the area of the transistor can be halved compared to the prior art. Such a multilayer integrated circuit is not limited to the above example, and both the first layer and the second layer may be TFTs, and third and fourth semiconductor element layers may be provided. .

  However, the connection between the first layer transistor and the second layer transistor has not been considered so far. For example, when connecting the source (or drain) of the lower transistor and the gate wiring of the upper transistor, after forming the upper gate wiring, an interlayer insulator is formed on the gate wiring and etched. Thus, a contact hole is formed in the source of the lower transistor and the gate wiring of the upper transistor, and a wiring connecting the contacts is formed on the interlayer insulator.

That is, the process after the formation of the interlayer insulator of the lower-layer transistor is as follows.
1) Formation of active semiconductor layer and gate insulating film of upper transistor (TFT) 2) Formation of gate wiring of TFT 3) Formation of TFT source / drain 4) Formation of first interlayer insulator of TFT 5) Lower layer A contact hole to the source of the transistor.
6) Formation of contact hole to gate wiring of TFT.
7) Formation of first interlayer wiring (connecting source of lower layer transistor and gate wiring of TFT)
8) Formation of second interlayer insulator of TFT 9) Formation of contact hole to TFT source or drain and formation of second interlayer wiring (wiring extending from TFT source or drain)

In the above example, in steps 5) and 6), the contact between the source of the lower transistor and the gate wiring of the TFT cannot be formed at the same time. Whereas the interlayer insulator covering the TFT and the first interlayer insulator of the TFT must be etched, the contact hole of the TFT gate wiring only needs to etch the first interlayer insulator of the TFT, and the depth of the hole Then, a difference of about 0.3 to 1 μm is generated, which causes, for example, overetching of the gate wiring of the TFT and causes a decrease in yield in the etching process. For this reason, it was usually performed in two steps as described above.
The present invention has been made in view of such problems, and aims to simplify the process.

  In the present invention, either the source or drain of the lower transistor is brought into contact with the gate wiring of the upper transistor (TFT) to solve the above problem. In this case, one end of the gate wiring of the TFT is either the source or the drain of the lower transistor. In particular, the present invention is characterized in that the TFT wiring is made of a material mainly composed of aluminum, and a laser is used in a step of introducing impurities into the source / drain of the TFT or a step after the introduction. For example, there are a method in which an impurity is introduced into an active semiconductor layer of a TFT by means such as ion implantation and then laser annealing, or a method in which laser irradiation is performed in an atmosphere (diborane or phosphine) containing impurities (laser doping).

(Function)
The process for connecting the source of the lower layer transistor and the gate wiring of the TFT described above using the present invention is as follows.
1) Formation of active semiconductor layer and gate insulating film of upper transistor (TFT) 2) Formation of contact hole to source of lower transistor.
3) Formation of TFT gate wiring (= wiring to the source of lower layer transistor) 4) Formation of TFT source / drain 5) Formation of interlayer insulator of TFT 6) Formation of contact hole to source or drain of TFT.
7) Formation of second interlayer wiring (wiring extending from TFT source or drain)
Thus, the process of forming the contact hole and the interlayer insulator is omitted, and the yield is improved.

  According to the present invention, a multilayer semiconductor integrated circuit can be manufactured with high yield. The TFT used in the present invention is not limited to a simple structure as shown in the embodiments, but may have a low concentration drain (LDD) or may have various offset structures. Not too long. Further, the conductivity types of the lower and upper transistors may be different from each other as in the embodiment or may be the same.

FIG. 1 shows an example of the present invention (production process sectional view). First, a lower layer transistor was formed on the upper surface of the single crystal silicon wafer 101 by a known MOS process. That is, a field insulator 102, a gate thermal oxide film 103, an N ⁺ type polycrystalline silicon gate electrode 104, an N type source 105, a drain 106, and an interlayer insulator 107 were formed. The source / drain may have a low concentration drain (LDD). The interlayer insulator is formed to be as flat as possible by a CVD method or the like, and in some cases, the surface may be planarized by a chemical mechanical polishing (CMP) method. After such treatment, annealing was performed at 900 to 1100 ° C. for 1 to 5 hours in a nitrogen atmosphere to densify the surface of the interlayer insulator 107. (Fig. 1 (A))

  Thereafter, an amorphous silicon film was deposited in a thickness of 100 to 5000, preferably 300 to 1000 by plasma CVD or LPCVD, and allowed to stand in a reducing atmosphere at 550 to 600 ° C. for 4 to 24 hours for crystallization. This step may be performed by laser irradiation. Then, the silicon film crystallized in this manner was patterned and etched to form an active semiconductor layer 108 of the TFT. Further, annealing was performed at 900 to 1100 ° C. for 1 to 5 hours in an oxygen atmosphere, and a thermal oxide film 109 was formed on the surface. (Fig. 1 (B))

After that, the interlayer insulator 107 was etched to form contact holes in the source 105 and drain 106 of the lower transistor. Then, an aluminum (including 1 wt% Si or 0.1 to 0.3 wt% Sc (scandium)) film having a thickness of 1000 to 3 μm was formed by electron beam evaporation or sputtering. At this time, the following multi-stage film formation process (for example, Extended Abstracts of 1993 International Conference on Solid State Devices and Materials, Makuhari, 1993, pp 180-182) may be used. That is, first, aluminum was selectively formed in the contact hole portion by a CVD method using dimethyl aluminum hydride (DMAH, AlH (CH ₃ ) ₂ ). Then, when the contact hole was completely filled, aluminum was formed on the entire surface by sputtering. This process can be performed continuously in a multi-chamber system.

  After the aluminum film was formed in this way, this was patterned and etched to form the source wiring 110, drain wiring 111, and gate wiring 112 of the underlying transistor. Here, it should be noted that although not shown in FIG. 1, the drain wiring 111 of the lower transistor and the gate wiring 112 of the TFT are integrated. Therefore, at this stage, the drain of the lower transistor and the gate wiring of the TFT are electrically connected. (Figure 1 (C))

Then, by ion doping, impurities were implanted in a self-aligned manner into the active semiconductor layer 108 of the TFT using the gate wiring 112 as a mask to form a P-type source 113 and drain 114. Diborane (B ₂ H ₆ ) was used as a doping gas. Thereafter, irradiation with KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was performed to activate impurity ions introduced into the active layer. As the laser, a XeCl excimer laser (wavelength: 308 nm, pulse width: 50 nsec) may be used.

  Needless to say, other lasers may be used in addition to the excimer laser. As for the pulse laser, an infrared laser such as an Nd: YAG laser (preferably Q-switch pulse oscillation) or a visible laser such as a second harmonic thereof can be used. Moreover, you may irradiate a laser beam from the board | substrate side. In this case, it is necessary to select a laser beam that passes through the underlying silicon semiconductor film. In this way, the source 113 and the drain 114 were activated. (Figure 1 (D))

  Finally, a silicon oxide film having a thickness of 2000 to 1 μm, for example, 3000 μm, was formed as an interlayer insulator 115 on the entire surface by CVD. Further, contact holes were formed in the TFT source 113, drain 114, and source wiring 110 of the lower transistor, and aluminum wirings 116, 117, and 118 were formed to a thickness of 2000 to 1 μm, for example, 5000 mm. When, for example, titanium nitride is formed as a barrier metal between the aluminum wirings 116 to 118 and the portion in contact with the aluminum wirings 116 to 118, the reliability can be further improved. (Figure 1 (E))

In this way, a complementary configuration could be obtained. Importantly, even though the conventional complementary FETs are multi-layered, the gate electrode of the P-channel FET and the N-channel FET has been formed at the same time because the idea of the inverter is the center. However, according to the present invention, in the complementary FET, one gate electrode and the other source or drain wiring are formed of a metal material.
2 and 3 show an example of forming a flip-flop circuit using this embodiment. FIG. 2A shows the source / drain and gate wiring of the lower layer transistor. A cross character 200 at the upper left of the figure means a marker. The hatched portion in the figure represents the source / drain, and the thick line represents the gate wiring. That is, in FIG. 2A, the drains 201 and 202 of the lower layer transistor, the source 203, and the gate wirings 206 and 207 are shown. The source 203 becomes power supply lines 204 and 205 as they are, and is grounded. (Fig. 2 (A))

  FIG. 2B shows the source / drain (active semiconductor layer), gate wiring, contact position, and the like of the TFT. The hatched portion in the figure represents the source / drain, and the thick line represents the gate wiring. That is, in FIG. 2B, the drains 208 and 209 of the TFT, the source 210, and the gate wirings 213 and 214 are shown. The source 210 becomes the power supply lines 211 and 212 as they are and is connected to an external power source. The contact 215 is connected to the gate wiring 206 of the lower first transistor, the contact 216 is connected to the drain 202 of the lower second transistor, the contact 218 is connected to the gate wiring 207 of the lower second transistor, and the contact 217 is connected to the lower first transistor. Each of the transistors is connected to the drain 201 of one transistor. Further, since the contacts 215 and 216 and the contacts 217 and 218 are connected by the gate wirings 213 and 214 of the TFT, respectively, the gate wiring 206 of the lower first transistor, the drain 202 of the second transistor, and the lower layer The gate wiring 207 of the second transistor and the drain 201 of the first transistor are connected to each other.

FIG. 2C shows the positions of the source / drain wirings and contacts of the TFT. That is, in FIG. 2C, the drain 208 of the first TFT and the gate wiring 214 of the second TFT are connected by the contacts 221, 222 and the wiring 219. Similarly, the drain 209 of the second TFT and the first TFT The TFT gate wiring 213 is connected to the contacts 223 and 224 by the wiring 220. (Fig. 2 (C))
What is characteristic from FIG. 2 is that the channel of the lower-layer transistor and the channel of the TFT are arranged so as to form an angle of 60 to 120 °, so that useless space can be eliminated as much as possible. . In order to further increase the degree of integration, it is effective to make this angle 80 to 100 °, preferably 90 °.

  FIG. 3B is a superposition of FIGS. 2A and 2B. The overlap is intentionally shifted slightly so that the overlap occurs. FIG. 3C is obtained by further superimposing FIG. 2C on FIG. In this way, a flip-flop circuit as shown in FIG. 3A was obtained. Points A, B, C, D, E, F, G, and H in FIG. 3A are represented by 216 (223, 224), 215, 218, 217 (221, 222), 204, 205, and 211 in FIG. , 212 respectively.

FIG. 4 shows an example in which this embodiment is further developed and a static RAM (SRAM) using a CMOS flip-flop circuit is configured. A portion surrounded by a dotted line in the figure indicates an exclusive area of the SRAM 1-bit cell. FIG. 3D shows an SRAM unit circuit in which selection transistors are attached to the left and right of the flip-flop circuit of FIG. Similarly, the cell area can be further reduced by using the configuration of the present invention.
FIG. 4A shows the source / drain and gate wiring of the lower layer transistor of this SRAM circuit. The hatched portion in the figure represents the source / drain, and the thick line represents the gate wiring. That is, FIG. 2A shows drains 401 and 402 of lower layer transistors, sources 403 and 404 of selection transistors, gate wirings 405 and 406, and word lines (gate wirings of selection transistors) 407. The source of the lower transistor is kept at a potential of _VL . (Fig. 4 (A))

FIG. 4B shows the source / drain (active semiconductor layer), gate wiring, contact position, and the like of the TFT. The hatched portion in the figure represents the source / drain, and the thick line represents a gate wiring or the like. That is, FIG. 4B shows TFT drains 408 and 409, gate wirings 410 and 411, and selection transistor source wirings 412 and 413. The source of the TFT is kept at the potential of V _H as it is. The arrangement of the contacts of the gate wirings 410 and 411 is substantially the same as that shown in FIG. (Fig. 4 (B))

FIG. 4C shows the positions of the source / drain wirings and contacts of the TFT. That is, in FIG. 4C, the drain 408 of the first TFT and the gate wiring 411 of the second TFT are connected by the wiring 416, and similarly the drain 409 of the second TFT and the gate wiring of the first TFT. 410 is connected by a wiring 417. In addition, bit lines (source lines of selection transistors) 414 and 415 are also provided in this layer. (Fig. 4 (C))
FIG. 4D is a superposition of FIGS. 4A, 4B, and 4C. In this way, a 1-bit cell of SRAM is formed. The cell shown in FIG. 4 is laid out so as to minimize the area of 1 bit.

FIG. 5 shows an example of the present invention (production process sectional view). First, as in the first embodiment, a field insulator 502, a gate thermal oxide film 503, an N ⁺ type polycrystalline silicon gate electrode 504, a P type source 505, a drain 506, and an interlayer insulator 507 are formed on a single crystal silicon wafer 501. To form a lower-layer transistor.
Thereafter, an amorphous silicon film was deposited to a thickness of 100 to 5000, preferably 300 to 1000, and left to stand in a reducing atmosphere at 550 to 600 ° C. for 4 to 24 hours for crystallization. This step may be performed by laser irradiation. Then, the silicon film crystallized in this way was patterned and etched to obtain an active semiconductor layer 508 of the TFT. Further, annealing was performed at 900 to 1100 ° C. in an oxygen atmosphere for 1 to 5 hours, and a thermal oxide film 509 was formed on the surface. (Fig. 5 (A))

  After that, the interlayer insulator 507 was etched to form contact holes in the source 505 and the drain 506 of the lower transistor. Then, an aluminum (including 1 wt% Si or 0.1 to 0.3 wt% Sc (scandium)) film having a thickness of 1000 to 3 μm was formed by electron beam evaporation or sputtering. Then, a photoresist was formed on the surface by a known spin coating method, and patterning was performed by a known photolithography method. Then, the aluminum film was etched with phosphoric acid. In this way, the source wiring 510, drain wiring 511, and gate wiring 512 of the lower layer transistor were formed. Also in this case, the drain wiring 511 of the lower layer transistor and the gate wiring 512 of the TFT are integrated. Also, the photoresist masks 513, 514, and 515 remain on these aluminum wirings, and the side surfaces of the wirings are inside the side surfaces of the photoresist. (Fig. 5 (B))

  In this state, an N-type impurity (phosphorus in this case) is implanted into the TFT active semiconductor layer 508 in a self-aligned manner using the photoresist 515 as a mask by ion doping to form an N-type source 516 and drain 517. . Here, since the gate electrode 512 is inside the distance x with respect to the photoresist 515, as shown in FIG. The distance x can be increased or decreased by adjusting the etching time for aluminum wiring. As x, 0.3 to 5 μm was preferable. A TFT having such a structure is called an offset gate type TFT. (Fig. 5 (C))

  Thereafter, the photoresists 513 to 515 were peeled off, and irradiation with KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was performed to activate the impurity ions introduced into the active layer. Finally, a silicon oxide film having a thickness of 2000 to 1 μm, for example, 3000 μm, was formed as an interlayer insulator 518 on the entire surface by a CVD method. Further, contact holes were formed in the TFT source 516, the drain 517, and the source wiring 510 of the lower-layer transistor, and aluminum wirings 519, 520, and 521 were formed to a thickness of 2000 to 1 μm, for example, 5000 mm. (Fig. 5 (D))

In this embodiment, the TFT is an N-channel type. Originally, an N-channel TFT has high mobility, but when a negative voltage is applied to the gate electrode, the leakage current between the source and the drain increases, which causes practical difficulties. By using the offset type as in this example, the electric field strength in the vicinity of the drain could be relaxed and the above leakage current could be suppressed.
In the case of Example 1 (FIG. 1), a P-channel type was used as a TFT, but this has a problem in that a CMOS is formed in combination with an NMOS transistor having a low mobility and a high mobility on single crystal silicon. However, in this embodiment, the lower layer MOS transistor is a PMOS with a low mobility, and it is easy to balance the mobility.

FIG. 6 shows an example of the present invention (production process sectional view). First, in the same manner as in Example 1, a field insulator 602, a gate thermal oxide film, and an N ⁺ type polycrystalline silicon gate electrode 603 were formed on a single crystal silicon wafer 601. Then, low-concentration phosphorus ions were implanted to form low-concentration N-type impurity regions (low-concentration N-type drain, N-type LDD) 605 and 606.
Further, an insulating film was formed on the entire surface, and this was anisotropically etched to form a side wall 604 on the side surface of the gate electrode. Then, N-type source 608 and drain 607 were formed by implanting high-concentration arsenic ions using the sidewall as a mask. Here, the source 608 is kept at _VL as in the circuit of FIG. Further, an interlayer insulator 609 was formed to form a lower layer transistor. (Fig. 6 (A))

After that, the interlayer insulator 609 was etched to form a contact hole in the drain 607 of the lower transistor. Then, the drain wiring 610 of the lower transistor and the gate wiring 611 of the upper TFT were formed by an aluminum (including 1 wt% Si) film having a thickness of 3000 mm. (Fig. 6 (B))
Further, a silicon oxide film 612 having a thickness of 1200 mm was formed. This silicon oxide film functions as a gate insulating film of the TFT. And it was crystallized by laser irradiation. Then, the silicon film crystallized in this way was patterned and etched to form an active semiconductor layer 613 of the TFT. Further, a doping mask 614 was formed using silicon oxide over the semiconductor layer. (Fig. 6 (C))

In this state, boron ions were implanted into the active semiconductor layer 613 of the TFT by ion doping to form a P-type source 615 and drain 616. Here, the source 615 is kept at V _H as in the circuit of FIG. (Fig. 6 (D))
Thereafter, thermal annealing was performed at 450 ° C. for 1 hour to activate the source / drain of the TFT. Further, a contact hole was formed in the drain wiring 617 of the lower transistor, and aluminum wirings 617 and 618 were formed to a thickness of 5000 mm. In this way, a circuit equivalent to that shown in FIG. 4 could be formed. (Fig. 6 (E))

In this example, the bottom gate type TFT is used, so that the contact hole opening process can be reduced as compared with the other examples, which is effective in improving the yield.
In the present invention, a method in which a metal material mainly composed of aluminum is used as the gate electrode of the upper transistor is shown. However, it has been effective to make this aluminum a 1/4 to 1/2 thickness thinner than the uppermost aluminum layer extending to the bonding pad to obtain a high-precision pattern. In addition, a semiconductor having the same conductivity type as the source / drain of the lower transistor or silicide such as tungsten may be used for this wiring.

FIG. 3 is a cross-sectional view of a manufacturing process of a TFT according to Example 1. 1 shows an arrangement of a flip-flop circuit according to a first embodiment. 1 shows an arrangement of a flip-flop circuit according to a first embodiment. 1 shows a circuit arrangement of an SRAM according to a first embodiment. FIG. 6 shows a cross-sectional view of a manufacturing process of a TFT according to Example 2. FIG. 10 shows a cross-sectional view of a manufacturing process of a TFT according to Example 3.

Explanation of symbols

101 Monocrystalline silicon wafer 102 Field insulator 103 Gate oxide film of lower transistor 104 Gate wiring of lower transistor 105 Source of lower transistor 106 Drain of lower transistor 107 Interlayer insulator of lower transistor 108 Active semiconductor layer of TFT 109 Gate oxide film 110 of TFT Lower layer source wiring 111 Lower layer drain wiring 112 TFT gate wiring 113 TFT source 114 TFT drain 115 TFT interlayer insulator 116-118 wiring

Claims (4)

A first TFT and a second TFT on the first transistor and the second transistor;
The gate wiring of the first transistor and the drain of the second transistor are electrically connected;
The gate wiring of the second transistor and the drain of the first transistor are electrically connected;
The drain of the first TFT and the gate wiring of the second TFT are electrically connected,
The drain of the second TFT and the gate wiring of the first TFT are electrically connected,
The drain of the first transistor and the gate wiring of the second TFT are electrically connected,
The drain of the second transistor and the gate wiring of the first TFT are electrically connected,
The sources of the first transistor and the second transistor are grounded,
A flip-flop circuit in which the sources of the first TFT and the second TFT are electrically connected to an external power source. A first TFT and a second TFT on the first transistor and the second transistor;
The gate wiring of the first transistor and the drain of the second transistor are electrically connected via the gate wiring of the first TFT;
The gate wiring of the second transistor and the drain of the first transistor are electrically connected via the gate wiring of the second TFT;
The drain of the first TFT and the gate wiring of the second TFT are electrically connected via the first wiring,
The drain of the second TFT and the gate wiring of the first TFT are electrically connected via a second wiring,
The sources of the first transistor and the second transistor are grounded,
A flip-flop circuit in which the sources of the first TFT and the second TFT are electrically connected to an external power source. A first contact electrically connected to the gate wiring of the first transistor; a second contact electrically connected to a drain of the second transistor; and a gate wiring of the second transistor. A third contact electrically connected; and a fourth contact electrically connected to the drain of the first transistor;
The first contact and the second contact are electrically connected via the gate wiring of the first TFT, and the third contact and the fourth contact are connected to the gate wiring of the second TFT. The flip-flop circuit according to claim 1, wherein the flip-flop circuit is electrically connected to the flip-flop circuit. A static RAM using the flip-flop circuit according to any one of claims 1 to 3.

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