WO2014109175A1

WO2014109175A1 - Semiconductor nonvolatile memory and method for manufacturing same

Info

Publication number: WO2014109175A1
Application number: PCT/JP2013/083481
Authority: WO
Inventors: 智光理崎
Original assignee: セイコーインスツル株式会社
Priority date: 2013-01-10
Filing date: 2013-12-13
Publication date: 2014-07-17
Also published as: TW201448123A; JP2014150241A

Abstract

In order to provide a semiconductor nonvolatile memory that is able to have a good balance between chip size shrinkage and stable rewriting characteristics, this semiconductor nonvolatile memory is provided with: a source-side tunnel drain region (12) and a drain-side tunnel drain region (11), which are provided in the surface of a semiconductor substrate (10) at a distance from each other; a second tunnel drain region (15) which is provided so as to overlap the drain-side tunnel drain region (11) between the source-side tunnel drain region (12) and the drain-side tunnel drain region (11); and a floating gate insulating film (13) which is provided on the second tunnel drain region (15) and has a tunnel window (14) that serves as an ion implantation mask for the second tunnel drain region (15).

Description

Semiconductor nonvolatile memory and manufacturing method thereof

The present invention relates to an electrically rewritable semiconductor nonvolatile memory.

A conventional semiconductor nonvolatile memory will be described with reference to FIG. FIG. 5 is a cross-sectional view of a conventional semiconductor nonvolatile memory according to manufacturing process. Here, the left half in the figure shows an alignment key area in which an alignment key serving as a mask alignment reference is arranged. The right half of the figure shows a memory area in which a semiconductor nonvolatile memory is arranged.

First, as shown in FIG. 5A, an oxide film 32 is formed on the semiconductor substrate 31, and then a nitride film 33 is formed on the oxide film 32. Next, as shown in FIG. 5B, the oxide film 32 and the nitride film 33 are patterned into a desired shape by a lithography method and an etching method. Next, as shown in FIG. 5C, the semiconductor substrate 31 is thermally oxidized using the patterned nitride film 33 as a mask to form a LOCOS (Local Oxidation of Silicon) oxide film 34. Next, as shown in FIG. 5D, the nitride film 33 is removed. At this time, in the alignment key region, an alignment key using a step between the oxide film 32 and the LOCOS 34 is formed. In the memory region, an active region under the floating gate in the semiconductor nonvolatile memory is formed. The oxide film 32 may be newly formed after the LOCOS oxide film 34 is formed.

Next, as shown in FIG. 5E, after the mask alignment using the alignment key, the drain region 35 of the semiconductor nonvolatile memory is formed on the surface of the semiconductor substrate 31. Next, as shown in FIG. 5F, after mask alignment using an alignment key, a tunnel window 36 of a semiconductor nonvolatile memory is formed in the oxide film 32 (see, for example, Patent Document 1).

Japanese Patent Laying-Open No. 2005-340654 (FIGS. 3 to 4)

In the conventional technique, the drain region 35 and the tunnel window 36 are formed with their positions determined using an alignment key. Therefore, the positional relationship between the drain region 35 and the tunnel window 36 is an indirect relationship via the alignment key. . For this reason, misalignment between the drain region 35 and the tunnel window 36 may occur.

Here, in order to reduce the chip size of the semiconductor nonvolatile memory, the chip size is shrunk by forming the drain area 35 to have a small planar area. Then, since the protrusion amount 37 of the drain region 35 with respect to the tunnel window 36 is reduced, there is a high risk that the tunnel window 36 is detached from the drain region 35 due to the above-described misalignment. If even a part of the tunnel window 36 is separated from the drain region 35, the amount of charge injected into the floating gate and the amount of charge extracted from the floating gate change, and the rewrite characteristics of the semiconductor nonvolatile memory become unstable.

The present invention has been made in view of the above problems, and provides a semiconductor nonvolatile memory capable of achieving both chip size shrinkage and stable rewrite characteristics.

In order to solve the above problems, the present invention provides a source region and a drain side tunnel drain region which are provided at intervals on the surface of a semiconductor substrate, and the source region and the drain side tunnel drain region on the surface of the semiconductor substrate. A second tunnel drain region provided so as to overlap the drain-side tunnel drain region, and a tunnel window located on the second tunnel drain region and functioning as an ion implantation mask for the second tunnel drain region. And a floating gate insulating film provided on the semiconductor substrate, a tunnel insulating film provided on the semiconductor substrate exposed at the tunnel window, and provided on the floating gate insulating film and the tunnel insulating film. Floating gate and the floaty A control gate insulating film provided on the Gugeto, and semiconductor nonvolatile memories, characterized in that it comprises a control gate provided on the control gate insulating film.

According to the present invention, the tunnel window functions as an ion implantation mask for the second tunnel drain region even if a part or all of the tunnel window is removed from the drain side tunnel drain region due to misalignment. Misalignment with the drain region does not occur (referred to as self-alignment or self-alignment), and the tunnel window does not deviate from the second tunnel drain region.

In other words, even if the amount of protrusion of the drain-side tunnel drain region with respect to the tunnel window is reduced due to chip size shrinkage, the tunnel window does not deviate from the second tunnel drain region. The characteristic does not become unstable.

Therefore, the semiconductor nonvolatile memory is compatible with chip size shrink and stable rewriting characteristics.

It is sectional drawing according to manufacturing process of the semiconductor non-volatile memory which concerns on a 1st Example. It is sectional drawing according to manufacturing process of the semiconductor non-volatile memory which concerns on a 1st Example. It is sectional drawing according to manufacturing process of the semiconductor non-volatile memory which concerns on a 1st Example. It is sectional drawing of the semiconductor non-volatile memory which concerns on a 1st Example. It is sectional drawing according to the manufacturing process of the conventional semiconductor non-volatile memory. It is sectional drawing of the semiconductor non-volatile memory which concerns on a 2nd Example. It is sectional drawing of the semiconductor non-volatile memory which concerns on a 3rd Example. It is sectional drawing of the semiconductor non-volatile memory which concerns on a 4th Example. It is sectional drawing of the semiconductor non-volatile memory which concerns on a 5th Example.

Hereinafter, an embodiment of a semiconductor nonvolatile memory according to the present invention will be described with reference to the drawings. 1 to 3 are cross-sectional views showing the manufacturing process of the semiconductor nonvolatile memory according to the first embodiment.

First, as shown in FIG. 1A, a P-type semiconductor substrate 10 is prepared. Subsequently, as shown in FIG. 1B, the drain side tunnel drain region 11 and the source side are formed on the surface of the semiconductor substrate 10 at a position sandwiching the channel region of the semiconductor nonvolatile memory by photolithography and ion implantation. A tunnel drain region 12 is formed. Then, as shown in FIG. 1C, a floating gate insulating film 13 is formed on the semiconductor substrate 10 by thermal oxidation or CVD (Chemical Vapor Deposition) method.

Next, as shown in FIG. 2D, a part of the floating gate insulating film 13 is removed by photolithography and etching, and a tunnel window 14 is formed in the floating gate insulating film 13. At this time, the boundary between the drain side tunnel drain region 11 and the channel region of the semiconductor substrate 10 is exposed from the tunnel window 14. In this way, as shown in FIG. 2E, the second tunnel drain region 15 is formed on the surface of the semiconductor substrate 10 below the tunnel window 14 by ion implantation using the tunnel window 14 as a mask so as to be self-aligned. To do. At this time, the second tunnel drain region 15 and the drain side tunnel drain region 11 overlap. The second tunnel drain region 15 is preferably formed to have a higher impurity concentration than the drain side tunnel drain region 11. By doing so, even if the overlap between the second tunnel drain region 15 and the drain side tunnel drain region 11 varies, the impurity concentration of the second tunnel drain region 15 becomes dominant, and the second tunnel just below the tunnel insulating film at the time of charge injection. The width of the depletion layer formed in the drain region becomes uniform, and variations in tunnel current flowing through the tunnel insulating film formed in the tunnel window 14 on the second tunnel drain region 15 can be suppressed. As a result, variations between memory cells can be suppressed. Thereafter, as shown in FIG. 2F, a tunnel insulating film 16 is formed on the semiconductor substrate 10 exposed at the tunnel window 14 by thermal oxidation or CVD.

Further, as shown in FIG. 3G, a floating gate 17 covering the tunnel insulating film 16 and the floating gate insulating film 13 is provided, and subsequently, a control gate insulating film 18 is provided around the floating gate 17, and further the control gate is provided. A control gate 19 is sequentially provided on the floating gate 17 via the insulating film 18. Then, as shown in FIG. 3H, drain regions 20 and source regions 21 are formed on the surface of the semiconductor substrate 10 on both sides of the channel region of the control gate 19 by ion implantation using the control gate 19 as a mask. To do.

As described above, in the semiconductor nonvolatile memory, as shown in FIG. 3H, the source region 21 and the drain region 20 are arranged on the surface of the semiconductor substrate 10 with a space therebetween, and the source-side tunnel drain region 12. The drain side tunnel drain region 11 is provided on the surface of the semiconductor substrate 10 at intervals. The source side tunnel drain region 12 and the drain side tunnel drain region 11 are in contact with the channel region side of the source region 21 and the drain region 20, respectively. Both the source-side tunnel drain region 12 and the source region 21 are source regions of the semiconductor nonvolatile memory. The second tunnel drain region 15 is provided on the surface of the semiconductor substrate 10 on the channel region side of the drain side tunnel drain region 11 so as to at least partially overlap the drain side tunnel drain region 11. The floating gate insulating film 13 is located on the second tunnel drain region 15, has a tunnel window 14 that functions as an ion implantation mask for the second tunnel drain region 15, and is provided on the semiconductor substrate 10. The tunnel insulating film 16 is provided on the semiconductor substrate 10 exposed at the tunnel window 14. The floating gate 17 is provided on the floating gate insulating film 13 and the tunnel insulating film 16. The control gate insulating film 18 is provided on the floating gate 17. The control gate 19 is provided on the control gate insulating film 18.

Here, the voltage difference between the voltage of the control gate 19 and the drain region 20 is controlled to be, for example, about 15 volts. Then, a tunnel current flows between the floating gate 17 capacitively coupled to the control gate 19 and the second tunnel drain region 15. By this tunnel current, writing in which charges are injected into the floating gate 17 through the tunnel insulating film 16 of the tunnel window 14 and erasing in which charges are extracted from the floating gate 17 are performed. When the charge amount of the floating gate 17 changes in this way, the floating gate 17 exists on the channel region of the semiconductor nonvolatile memory and determines its potential, so that the conductance of the channel region apparently changes and the semiconductor nonvolatile memory The threshold voltage will change.

Since the floating gate 17 is electrically insulated from its surroundings, it is possible to store electric charges therein for a long time. That is, the threshold voltage of the semiconductor nonvolatile memory is maintained for a long time. Therefore, the semiconductor nonvolatile memory can store the threshold voltage (the magnitude) in a nonvolatile manner as information.

In the above description, a part of the tunnel window 14 overlaps the drain side tunnel drain region 11 on the plane. However, as shown in FIG. 4, the entire tunnel window 14 may overlap the drain side tunnel drain region 11a on a plane.

In the above description, the drain side tunnel drain region 11 is given its name by contributing to the tunnel current. On the other hand, the source-side tunnel drain region 12 does not contribute to the tunnel current, but is named by being formed using the same ion implantation mask as the drain-side tunnel drain region 11. The present invention is not limited to a semiconductor nonvolatile memory in which the drain side tunnel drain region 11 and the source side tunnel drain region 12 are formed using the same ion implantation mask.

In the embodiment, the source region of the semiconductor nonvolatile memory is composed of both the source-side tunnel drain region 12 and the source region 21, but the source region 21 can be omitted as appropriate. In this case, a contact region for wiring connection may be provided directly in the source-side tunnel drain region 12, and the implementation is easy.

On the other hand, it is possible to omit the source-side tunnel drain region 12, but some contrivance is required, which will be described below as a second embodiment.

FIG. 6 shows a second embodiment, which shows a semiconductor nonvolatile memory in which a source region 23 is formed by one diffusion region. In this embodiment, the source region 23 is formed simultaneously with the drain region 20. For this purpose, it is necessary to form the source region 23 in contact with the end of the floating gate 17. In this embodiment, the floating date and the control gate are overlapped and etched at a time so that a vertical cross section of the floating date and the control gate appears on the source side. In this way, the source region 23 can be formed on the floating date and the control gate in a self-aligned manner. By doing so, it is possible to reduce the length of the semiconductor nonvolatile memory in the direction along the channel length, and the effect is that the area of the cell can be reduced. Other portions have the same configuration as in FIG.

FIG. 7 shows a third embodiment in which the control gate 19 covers the floating gate 17 on both the drain side and the source side, but the semiconductor in which the source region 22 is formed on the floating gate 17 and self-alignment. A non-volatile memory is shown. To make this shape, the source region 22 cannot be formed at the same time as the drain-side tunnel drain region 11, and it is necessary to form the source region 22 individually after forming the floating gate 17. In this way, in the first embodiment, it is necessary to allow a positional shift so that the source side tunnel drain region 12 and the floating gate electrode 17 are surely overlapped. However, in this embodiment, the floating gate 17 and the self-alignment are required. Since the source region 22 is formed in this case, it is not necessary to allow for the positional deviation. Other portions have the same configuration as in FIG.

FIG. 8 shows a fourth embodiment, which shows a semiconductor nonvolatile memory in which not only the source region 23 but also the drain region 20 is in contact with the ends of the floating gate 17 and the control gate 19 and is self-aligned. In this embodiment, the length L _FGD in the channel length direction of the floating gate 17 on the drain side, which becomes the base of the tunnel window 14 for forming the tunnel insulating film 16, is made sufficiently small within the allowable range. The region 20 and the second tunnel drain region 15 can be brought close to each other. However, since the end of the floating gate on the drain side protrudes in an eaves shape, the drain region 20 and the second tunnel drain region 15 are not normally in direct contact with each other. Therefore, the drain side tunnel drain region 11 is arranged so that the drain region 20 and the second tunnel drain region 15 are reliably connected. With such a configuration, the length of the semiconductor nonvolatile memory in the direction along the channel length can be further reduced, and the cell area can be reduced.

On the other hand, depending on the conditions for diffusing the impurities in forming the drain region 20 or the second tunnel drain region 15 by ion implantation, the drain region 20 and the second tunnel drain region 15 may be in direct contact and have an overlap. The drain side tunnel drain region 11 can be omitted. FIG. 9 shows this state.

FIG. 9 shows a fifth embodiment. Compared with the fourth embodiment shown in FIG. 8, the drain region 20 and the second tunnel drain region 15 are in direct contact with each other, and thus have an overlap. The drain side tunnel drain region 11 is not provided. As a method for bringing the drain region 20 and the second tunnel drain region 15 into direct contact with each other even if the drain side tunnel drain region 11 is not provided, for example, during ion implantation when forming these impurity regions, It is possible to use oblique ion implantation with a small elevation angle. In the oblique ion implantation, since the lateral diffusion length along the surface of the semiconductor substrate is increased, the drain region 20 and the second tunnel drain region 15 can be brought into direct contact with each other. With such a structure, the size of the semiconductor nonvolatile memory in the channel length direction can be further reduced, which is advantageous when a semiconductor device including a highly integrated nonvolatile memory is configured. Other parts are the same as those of the fourth embodiment shown in FIG.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Drain side tunnel drain region 12 Source side tunnel drain region 13 Floating gate insulating film 14 Tunnel window 15 Second tunnel drain region 16 Tunnel insulating film 17 Floating gate 18 Control gate insulating film 19 Control gate 20

Drain regions

21, 22, 23 Source region

Claims

A semiconductor substrate;
On the surface of the semiconductor substrate, a source region and a drain side tunnel drain region provided at intervals,
A second tunnel drain region provided on the surface of the semiconductor substrate so as to overlap the drain side tunnel drain region between the source region and the drain side tunnel drain region;
A floating gate insulating film provided on the semiconductor substrate, having a tunnel window located on the second tunnel drain region and defining the second tunnel drain region in a self-aligning manner;
A tunnel insulating film provided on the semiconductor substrate exposed in the tunnel window;
A floating gate provided on the floating gate insulating film and the tunnel insulating film;
A control gate insulating film provided on the floating gate;
A control gate provided on the control gate insulating film;
A semiconductor non-volatile memory comprising:
2. The semiconductor nonvolatile memory according to claim 1, wherein a part of the tunnel window overlaps the drain-side tunnel drain region on a plane.
2. The semiconductor nonvolatile memory according to claim 1, wherein the entire tunnel window overlaps the drain-side tunnel drain region on a plane.
4. The semiconductor nonvolatile memory according to claim 1, wherein an impurity concentration of the second tunnel drain region is higher than an impurity concentration of the drain side tunnel drain region.
A semiconductor substrate;
A source region and a drain region provided on the surface of the semiconductor substrate at intervals;
A second tunnel drain region provided between the drain region and the source region and having an overlap in direct contact with the drain region;
A floating gate insulating film provided on the semiconductor substrate, having a tunnel window located on the second tunnel drain region and defining the second tunnel drain region in a self-aligning manner;
A tunnel insulating film provided on the semiconductor substrate exposed in the tunnel window;
A floating gate provided on the floating gate insulating film and the tunnel insulating film;
A control gate insulating film provided on the floating gate;
A control gate provided on the control gate insulating film;
With
Both the source region and the drain region are provided in a self-aligned manner with respect to the floating gate.
Preparing a semiconductor substrate; and
Forming a drain-side tunnel drain region on the surface of the prepared semiconductor substrate;
Forming a floating gate insulating film on the surface of the drain side tunnel drain region and the surface of the semiconductor substrate;
Forming a tunnel window in a portion of the floating gate insulating film located above the boundary between the drain-side tunnel drain region and the channel region of the semiconductor substrate so that the boundary is exposed;
Introducing a impurity using the tunnel window as a mask, and forming a second tunnel drain region on the surface of the semiconductor substrate under the tunnel window;
Forming a tunnel insulating film on the surface of the second tunnel drain region;
Providing a floating gate on the tunnel insulating film and the floating gate insulating film on the channel region;
Forming a control gate insulating film around the floating gate;
Providing a control gate on the floating gate via the control gate insulating film;
Forming a drain region and a source region on both sides of the control gate using the control gate as a mask;
A method for manufacturing a semiconductor non-volatile memory.