KR20060012982A - Non-volatile memory device and manufacturing method for the same - Google Patents

Abstract

A nonvolatile memory device is provided. A nonvolatile memory device includes a recess formed on an active region in a semiconductor substrate including an active region and an isolation region, a source region formed below the recess, and a source region interposed therebetween, And a floating gate buried in the groove portion and insulated from the source region via the gate insulating film, and a word line used as a selection gate and a control gate, insulated and formed through the floating gate and the tunnel oxide film in pairs. A method of manufacturing a nonvolatile memory device is also provided.

Split Gate Type, Hot Electron, Tunnel Oxide

Description

Non-volatile memory device and manufacturing method for the same

1 is a cross-sectional view of a split gate type flash memory cell according to the prior art.

2 is a cross-sectional view of a nonvolatile memory device according to an embodiment of the present invention.

3 to 8 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention in a process sequence.

<Description of the symbols for the main parts of the drawings>

10 semiconductor substrate 12 first oxide film (gate insulating film)

14: floating gate 18: second oxide film (tunnel oxide film)

20: word line 22: source region

24: drain region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a method of manufacturing the same. More particularly, the present invention relates to a nonvolatile semiconductor device capable of increasing the program efficiency of a split gate type flash memory cell and simplifying a manufacturing process. How is it?

Non-volatile memory devices with built-in flash memory cells have been applied in various fields because of the advantage that the data can be erased and programmed electrically and the data can be stored even when power is not supplied.

These flash devices are classified into NAND type and NOR type according to the structure of the memory cell array. These flash devices have respective advantages of high integration and high speed, and each of them is highlighted. The use in applications is increasing.

FIG. 1 is a cross-sectional view illustrating a split gate type flash memory cell structure which has been widely used as an example of a NOR type device.

As shown in FIG. 1, a split gate type flash memory cell structure according to the related art is as follows.

The gate insulating film 12 is formed on the active region of the semiconductor substrate 10. On the gate insulating film 12, the floating gates 14 are formed in pairs spaced apart from each other by a predetermined interval, and a tunnel oxide film 18 is formed thereon. Word lines 20 are formed in pairs on the tunnel oxide film 18, respectively, and are formed over predetermined portions on the floating gate 14 and the substrate 10, respectively. For reference, the word line 20 pairs serve as selection and control gates.

Meanwhile, a source region 22 is formed in the substrate 10 between the floating gates 14, and the word line 20 is formed in the substrate 10 at a predetermined distance from the source region 22. And a drain region 24 formed so as to overlap a predetermined portion, and the memory cell is configured to operate as a selection gate transistor and a memory gate transistor.

Hereinafter, program and erase operations of the flash memory cell will be described.

In the program operation, when a high voltage is applied to the source region 22, electrons excited by the potential difference between the coupled floating gate 14 and the drain junction 24 are floating gate by HEI (Hot Electron Injection) method. (14) is made in such a way that it is injected into. In addition, the erase operation is performed in such a manner that electrons in the floating gate 14 are tunneled to the control gate 20 by F-N and exit due to a high voltage applied to the word line 20.

According to the related art, by using only the vertical (↑ e) field in the program operation and the erase operation, the program efficiency was low and a high voltage (a voltage applied to the source for the program operation) had to be applied. Therefore, the gate oxide film must also be formed thicker, and thus there is a problem that the current consumption is large.

In addition, when the size of the floating gate 14 is limited, there is a limit to shrinking the cell beyond a predetermined limit due to a margin for misalignment with the control gate.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a nonvolatile memory device capable of miniaturizing the size of a flash memory cell and a method of manufacturing the same.                         

Another object of the present invention is to provide a nonvolatile memory device capable of maximizing program efficiency with a structure capable of injecting hot electrons in both vertical and lateral directions during a program operation of a flash memory cell.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device suitable for manufacturing the flash memory cell.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device which can simplify a process by using a minimum of masks when manufacturing a flash memory cell.

According to an aspect of the present invention, there is provided a nonvolatile memory device including a recess formed on an active region in a semiconductor substrate including an active region and an isolation region, a source region formed under the recess, A pair of source regions interposed therebetween, buried in a recess in the substrate and insulated from the source region via a gate insulating film, and insulated and formed in pairs via the floating gate and a tunnel oxide film, It includes a word line used as a select gate and a control gate.

In this case, the tunnel oxide film is preferably formed flat on the substrate.

In addition, the manufacturing method of the nonvolatile memory device according to the present invention for achieving the above technical problem is as follows. First, a recess is formed in the substrate by etching a predetermined thickness of the semiconductor substrate. Next, a gate insulating film and a first conductive film are sequentially formed along the step on the substrate. Subsequently, the first conductive layer is etched by chemical mechanical polishing to expose the gate insulating layer to form a first conductive layer pattern. Next, a tunnel oxide film and a second conductive film are sequentially formed on the resultant product. Next, a drain region is defined at both positions spaced apart from the first conductive layer pattern, and the second conductive layer is etched to form a second conductive layer pattern to expose the tunnel oxide layer on the drain region. Next, the second conductive layer pattern, the tunnel oxide layer, and the first conductive layer pattern are etched to expose the gate insulating layer on the source region to be formed under the first conductive layer pattern. Form.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

First, the structure of a nonvolatile memory device according to an embodiment of the present invention will be described in detail with reference to FIG. 2.                     

2 is a cross-sectional view of a nonvolatile memory device according to an embodiment of the present invention.

As shown in FIG. 2, in the nonvolatile memory device according to an exemplary embodiment of the present invention, a pair of floating gates 14 are disposed on both sides of a source region 22 in an active region of a semiconductor substrate 10. It is formed.

In this case, the floating gate 14 is designed to be buried in the recess h formed in the substrate 10, and an oxide film 18 is formed flat on the floating gate 14. .

As such, the recess h of a predetermined thickness is formed on the surface of the substrate 10 of the memory cell forming portion, and the floating gate 14 is formed in a structure embedded in the substrate 10. It is possible to enable hot electron injection in both lateral (→ e) and vertical (↑ e) directions. As a result, during the program operation of the flash memory cell, the hot electron injection efficiency may be higher than in the conventional flash memory cell in which the hot electron is injected only in the vertical (↑ e) direction.

In addition, since the size of the floating gate 14 may be determined by the size of the recess h, the size of the floating gate 14 may be adjusted by adjusting the width and thickness of the recess h of the substrate 10. I can regulate it. This is useful when the small size of the floating gate 14 is formed.

Meanwhile, the floating gate 14 is surrounded by the first and second oxide films 12 and 18, and a word line 20 to be used as a selection and control gate on the second oxide film 18 on the floating gate 14. ) Are stacked.                     

Insulation between the floating gate 14 and the word line 20 is made by a second oxide film 18 which is a tunnel oxide film. As the tunnel oxide film, a single layer structure of a thermal oxide film or a lamination structure of a "thermal oxide film / CVD oxide film" is used. In addition, the first oxide layer 12 serves as a gate insulating layer.

In addition, the floating gate 14 and the word line 20 may be formed of polysilicon or polyside material. Unexplained reference numeral 24 denotes a drain region.

Next, a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. 3 to 8.

3 to 8 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention in a process sequence.

In the method of manufacturing a nonvolatile memory device according to an embodiment of the present invention, as shown in FIG. 3, first, a field oxide layer (not shown) is formed in an isolation region of a semiconductor substrate 10 to define an active region. do.

A first mask pattern PR1 of photoresist material is formed on the substrate 10 so as to define a source region on the active region and have an opening having a wider width than a portion where the source region is to be formed. Subsequently, the recess 10 is formed in the substrate 10 by selectively etching the substrate 10 using the first mask pattern PR1.

Next, as shown in FIG. 4, the first mask pattern PR1 is removed, and the first oxide film 12 is deposited on the resultant using a thermal oxidation process or a chemical vapor deposition (CVD) process. Form. Subsequently, a first conductive film 14a made of polysilicon or polyside is formed on the first oxide film 12.

Next, as shown in FIG. 5, the first conductive layer 14a is etched by chemical mechanical polishing (CMP) to expose the first oxide layer 12, and thus the first conductive layer pattern 14b is etched. ).

Accordingly, the first conductive layer pattern 14b is buried in the recess h in the substrate 10, and the upper portion of the first conductive layer pattern 14b has a planarized structure.

Next, as shown in FIG. 6, a second oxide film 18 is formed on the resultant using a thermal oxidation process or a chemical vapor deposition (CVD) process on the resultant planarized by the chemical mechanical polishing process (CMP). To form. Subsequently, a second conductive layer 20a of polysilicon or polyside is formed on the second oxide layer 18.

Next, as shown in FIG. 7, regions in which the drain region 24 is to be formed are defined at both sides spaced apart from the first conductive layer pattern 14b, and the region in which the drain region 24 is to be formed. A second mask pattern PR2 of photoresist material is formed on the second conductive layer 20a so as to be exposed. Subsequently, the second conductive layer 20a is patterned by an etching process using the second mask pattern PR2 to form a second conductive layer pattern 20b. Subsequently, a high concentration of impurities are ion implanted onto the resultant product using the second mask pattern 20b as a mask to form a drain region 24 in the substrate 10.

Next, as shown in FIG. 8, a third mask pattern PR3 of photoresist material is disposed on the second conductive layer pattern (refer to 20b of FIG. 7) to expose the portion where the source region 22 is to be formed. Form. Subsequently, the second conductive layer pattern (see 20b of FIG. 7), the second oxide layer 18, and the first conductive layer pattern (see 14b of FIG. 7) are etched using the third mask pattern PR3. Pattern to process Accordingly, the first conductive layer pattern (see 14b of FIG. 7) is separated to form a floating gate 14 pair, and the second conductive layer pattern 20b is separated to form a selection and control gate 20 pair. . Subsequently, a high concentration of impurities are ion implanted onto the resultant product using the third mask pattern PR3 as a mask to form a source region 22 in the substrate 10.

Next, the third mask pattern PR3 is removed to form a flash memory cell as shown in FIG. 2.

Subsequently, a metal wiring (not shown) and a drain contact (not shown) are formed on and around the selection and control gate 20 through a silicide process and a metal process to complete the nonvolatile memory device.

Meanwhile, in the exemplary embodiment of the present invention, the source region 22 is formed by ion implantation after the pair of floating gates 14 are formed as an example, but the recess h is formed in the substrate 10. After forming, the source region 22 may be previously formed by ion implantation.

In addition, when the impurities for forming the drain region 24 and the source region 22 are the same material, the drain region 24 may be formed together when the source region 22 is formed. .

In addition, the source region 22 may be formed first, and then the drain region 24 may be formed.

Therefore, in the method of manufacturing a nonvolatile memory device according to an embodiment of the present invention, the floating gate 14 is buried in a substrate through a chemical mechanical polishing process, thereby injecting hot electrons in both vertical and lateral directions during a program operation. It is possible to manufacture flash memory cells of all possible structures, and the manufacturing process can be simplified by using a minimum mask pattern.

As mentioned above, although the present invention has been described with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention.

As described above, according to the present invention, by embedding the floating gate in the substrate through a chemical mechanical polishing process, the size of the flash memory cell can be further miniaturized, and hot electron injection in both vertical and lateral directions during the program operation can be reduced. All possible structures maximize program efficiency. In addition, minimal masks can be used to simplify the process.

Claims (8)

A recess formed in the active region in the semiconductor substrate including the active region and the device isolation region; A source region formed below the recess; A floating gate formed in pairs with the source region interposed therebetween, buried in a recess in the substrate, and insulated from the source region via a gate insulating layer; And And a word line that is insulated and formed in pairs through the floating gate and the tunnel oxide layer, and used as a selection gate and a control gate. In claim 1, And the tunnel oxide layer is formed flat on the substrate. In claim 2, And the floating gate and the word line are formed of polysilicon or polyside material. (a) forming a recess in the substrate by selectively etching a thickness of the semiconductor substrate; (b) sequentially forming a gate insulating film and a first conductive film along the steps on the substrate; (c) forming the first conductive film pattern by etching the first conductive film by a chemical mechanical polishing process so that the gate insulating film is exposed; (d) sequentially forming a tunnel oxide film and a second conductive film on the resultant product; (e) forming a second conductive layer pattern by defining a drain region at both positions spaced apart from the first conductive layer pattern, and etching the second conductive layer to expose the tunnel oxide layer over the drain region; And (f) Floating gates and word lines formed in pairs by etching the second conductive layer pattern, the tunnel oxide layer, and the first conductive layer pattern to expose the gate insulating layer on the source region to be formed under the first conductive layer pattern. Forming a non-volatile memory device. In claim 4, Between step (e) and step (f) or after step (f), And implanting impurities to form a drain region. In claim 5, Between step (a) and step (b) or after step (f), And implanting impurities into the source region. In claim 6, And forming the drain region and the source region at the same time. In claim 4, The first conductive layer and the second conductive layer are formed of polysilicon or polyside material.

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