KR100976064B1 - 2 Bit Multi-level Flash Memory of having Separeted Gate - Google Patents

Abstract

A flash memory capable of storing two bits of data in one cell is disclosed. Two gate structures are formed on the fin-shaped substrate, and a gate separator having a high dielectric constant is interposed between the formed gate structures. The interposed gate separator electrically insulates the gate structures from each other. Thus, the coupling phenomenon in which the gates electrically influence each other is prevented. In addition, the back tunneling effect is reduced by the high dielectric constant gate separation film. In addition, the fin structure ensures sufficient channel length even at short source and drain spacings.

Flash Memory, Pin Transistors, Nonvolatile Memory

Description

2 bit multi-level flash memory of having separeted gate

The present invention relates to a nonvolatile memory, and more particularly to a flash memory capable of storing two bits in one cell.

Non-volatile memory is a device that can preserve stored information even when power supply is interrupted. In particular, flash memory is a representative device of nonvolatile memory, and has high integration and excellent data retention.

The operation aspect of the flash memory includes a program operation and an erase operation. The program operation is an operation of trapping charge at an interface of a floating gate or a nitride film. On the other hand, the erase operation is an operation for transferring the trapped charge to the lower substrate. The threshold voltage of the cell transistor is changed by the program operation and the erase operation. The storage operation of the information occurs by changing the threshold voltage.

The above-described flash memory is classified into NAND type and NOR type according to an aspect of operation and an arrangement structure of cells. In particular, NAND flash memory is a memory that is actively being researched for increasing the capacity for storing a large amount of data. Such NAND flash memory has doubled in capacity over the last five years, approaching the capacity of notebook hard disks.

To increase the memory capacity, it is necessary to reduce the line width or reduce the cell area. However, when the channel length of a transistor constituting a unit cell in a flash memory is 50 nm or less, an increase in leakage current due to tunneling of the gate insulating film, an increase in quantum mechanical tunneling current to a source and a drain, a drain and a substrate, and an electron distribution in the channel Problems such as deterioration of device characteristics due to unevenness and deterioration of subthreshold characteristics due to intensification of short channel effects occur. That is, only by reducing the size of the transistor which is a unit cell, there is a limit in maintaining or improving the characteristics of the device. The main reason for the limitation due to the size reduction of the device is the occurrence of the short channel effect. As the size of the device is reduced, the short channel effect of leakage current between the source and the drain is intensified. Therefore, a method of having a three-dimensional structure has been proposed rather than a planar structure of a channel of a transistor.

In addition, a method of forming a charge stack at the interface of the SiN film by forming a SONOS type gate stack structure can be used. This has the advantage that the charge can be stored in a plurality of physically separated places, it is possible to improve the number of bits stored per cell.

For example, in the case of multi-bit of 2 bits / cell, in the floating gate type, it is necessary to separate the voltage levels into 4 types, whereas when multi-bit of 2 bits / cell is implemented, charges can be accumulated in two different regions. There is an advantage. However, the technique of separating the gates into two bits causes a coupling effect between the gates and thus the reliability of data storage becomes a problem. In addition, a problem occurs in that a back tunneling phenomenon in which charge passes through the oxide film from the gate electrode occurs.

An object of the present invention to solve the above problems is to provide a flash memory that can store two bits per cell with a small area, and can prevent back tunneling, short channel effects, and coupling between gates.

The present invention for achieving the above object is a substrate having a fin region buried from the surface; Two gate structures filling the fin region of the substrate; A source region formed on one side of the gate structure; A drain region facing the source region around the gate structure; And a gate separator disposed between the two gate structures and electrically separating the two gate structures.

According to the present invention, one cell may store two bits of data through a gate separator provided between the gate structures. In addition, back tunneling and coupling between gates are prevented through the high dielectric constant gate separator. In addition, since the substrate has a fin structure and a channel is formed along the fin shape, the short channel effect can be prevented even in a space between the short source and the drain.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

1 is a perspective view showing a flash memory according to a preferred embodiment of the present invention.

Referring to FIG. 1, a gate structure 200 is formed on a substrate 100. In addition, both side surfaces of the gate structure 200 may include a source region 310 and a drain region 320. The gate structure 200 illustrated in FIG. 1 has a shape buried inward from the surface of the substrate 100. Thus, the channel region has the shape of a fin. That is, the gate structure 200 is formed on the fin region of the substrate 100. In the technical field of the present invention, such a structure is referred to as a fin type transistor.

The gate structure 200 includes a tunneling oxide layer 120, a charge trap layer 130, a blocking insulating layer 140, and a gate electrode 150. In addition, two gate structures 200 are disposed around the gate separation layer 210. Each gate structure 200 is configured to enable independent program operation.

In addition, both side surfaces of the source and drain regions 310 and 320 may be filled with the oxide film 110.

The tunneling oxide layer 120 may be made of silicon oxide. In particular, the tunneling oxide film 120 is formed using a thermal oxidation process. In addition, the tunneling oxide layer 120 may be formed by atomic layer deposition or chemical vapor deposition.

The charge trap layer 130 is provided on the tunneling oxide layer 120. The charge trap layer 130 is preferably made of silicon nitride (Si3N4). The charge trap layer 130 stores charge at an interface with the tunneling oxide layer 120.

The blocking insulating layer 140 is disposed on the charge trap layer 130. The blocking insulating layer 140 is made of silicon oxide or metal oxide. When the blocking dielectric layer 140 is formed of a metal oxide, the metal oxide may be selected from the group consisting of hafnium oxide, titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, and zirconium oxide having a high dielectric constant. At least one selected from these groups may be an additive of nitrogen or silicon, or a composite film thereof.

The gate electrode 150 is provided on the blocking insulating layer 140. The gate electrode 150 may be made of polycrystalline silicon, metal, conductive metal nitride, or conductive oxide. The gate electrode 150 is provided separately for each gate structure 200.

Two gate structures 200 are provided in one cell. A gate separator 210 is provided between the two gate structures 200. The gate separation layer 210 preferably uses a metal oxide having a high dielectric constant. The metal oxide may be selected from the group consisting of hafnium oxide, titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide and zirconium oxide having high dielectric constant, and may be an additive of nitrogen or silicon to at least one selected from these groups. Or a composite film thereof. The coupling effect between the two gate structures is minimized by the high dielectric constant gate separator 210.

FIG. 2 is a cross-sectional view of the flash memory shown in FIG. 1 taken along the line X-X '.

Referring to FIG. 2, two gate structures 200 are disposed in a fin portion buried from the surface of the substrate 100, and a gate separation layer 210 is interposed between the gate structures 200. Each gate structure 200 has a structure in which the tunneling oxide layer 120, the charge trap layer 130, the blocking insulating layer 140, and the gate electrode 150 are sequentially stacked. In addition, in order to implement 2 bits, the concentration of impurities in either of the left and right portions of the pin portion is increased. That is, the concentration of impurities in the portion where the charge is returned to the trap and channel regions of the charges in the two gate structures 200 is uneven. For example, the width of the depletion region of the drain region 320 may be decreased by increasing the concentration of impurities in the region adjacent to the drain region 320 at the fin region. On the contrary, the doping concentration of the fin region adjacent to the source region 310 may be increased.

3 is a graph showing a trap charge amount with time during a program operation according to a preferred embodiment of the present invention.

Referring to FIG. 3, a program operation electrically separates a source region and a drain region and applies a program voltage to each gate electrode. The program voltage applied in FIG. 3 is 15V. As the program voltage is applied, charge passes through the tunneling oxide film and is trapped in the charge trap layer. That is, the phenomenon occurring during the program operation is F-N tunneling.

First, the initial state is set to '11'. This is a state where no charge is present in the charge trap layer.

Next, in the state '01', a program operation is performed on the gate structure adjacent to the source region. That is, a program voltage is applied to the gate electrode in the gate structure adjacent to the source region. Since the pin region adjacent to the source region is relatively low-doped, the amount of charge trapped is less than the amount of trap charge resulting from a program operation in a subsequent high-doped region.

In the state '10', the program operation is performed on the gate structure adjacent to the drain region. Since the fin region adjacent to the drain region is relatively doped, the amount of charge trapped by the program operation is increased compared to the state '01'.

Finally, in state '00', the program operation is performed on the two gate structures. Therefore, the amount of charge trapped becomes maximum.

4 is a graph showing the amount of charge remaining in the charge trap layer with time during an erase operation according to a preferred embodiment of the present invention.

Referring to FIG. 4, after an erase voltage is applied to the gate electrode of the gate structure, all charges in the charge trap layer may be removed after about 50 msec. The erase voltage in FIG. 4 is -12V.

5 is a graph showing the amount of change in the threshold voltage according to a preferred embodiment of the present invention.

The voltage at the gate electrode is changed, and the voltage of the gate electrode when the current flowing through the cell is 50 uA while a constant bias is applied between the drain region and the source region is set to the threshold voltage Vth.

In the state '00' where the trap amount of charge is the highest, the threshold voltage of the cell has the largest value. This is due to the effect of trapped electrons. The threshold voltages of the cells are in order of state '01', state '10', and state '11'. This is proportional to the amount of charge trapped in the charge trap layer.

The change of the threshold voltage according to the four states described above appears in the form of data stored in a read operation.

That is, a read voltage is applied to the gate electrode adjacent to the source region, and a pass voltage is applied to the gate electrode adjacent to the drain region. The read voltage is set to a value between threshold voltages of state '01' and state '10' in FIG. 5. In addition, the pass voltage is determined as a value that exceeds the threshold voltage at '00'. Therefore, when a read voltage is applied to the gate electrode adjacent to the source region, the state of the gate electrode adjacent to the source region can be confirmed. That is, when no current is detected in the drain region, it is determined as the state '01' or '00'.

Next, a read voltage is applied to the gate electrode adjacent to the drain region, and a pass voltage is applied to the gate electrode adjacent to the source region. The read voltage is determined as a threshold voltage between the state '01' and the state '00'. Therefore, the state of the cell can be finally confirmed by sensing the current flowing in the drain region.

According to the present invention described above, one cell can store two bits of data. In addition, since the pin structure has a short channel effect due to the reduction of the channel length. By preventing the short channel effect, the reliability of the data storage capacity of the cell is improved, and the storage capacity of the flash memory can be improved with the reduction of the cell area.

1 is a perspective view showing a flash memory according to a preferred embodiment of the present invention.

FIG. 2 is a cross-sectional view of the flash memory shown in FIG. 1 taken along the line X-X '.

3 is a graph showing a trap charge amount with time during a program operation according to a preferred embodiment of the present invention.

4 is a graph showing the amount of charge remaining in the charge trap layer with time during an erase operation according to a preferred embodiment of the present invention.

5 is a graph showing the amount of change in the threshold voltage according to a preferred embodiment of the present invention.

Claims (4)

A substrate having fin regions buried from the surface; Two gate structures filling the fin region of the substrate; A source region formed on one side of the gate structure; A drain region facing the source region around the gate structure; And A gate separator disposed between the two gate structures and electrically separating the two gate structures, The gate structures are sequentially disposed between the source region and the drain region, and the respective gate structures are disposed side by side in the width direction of the fin region. The method of claim 1, wherein the gate separator is selected from the group consisting of hafnium oxide, titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide and zirconium oxide having a high dielectric constant, or at least one selected from these groups Flash memory characterized in that it is an additive or a composite film thereof. The method of claim 1, wherein the gate structure, A tunneling oxide film formed on the fin region; A charge trap layer formed on the tunneling oxide film and formed of silicon nitride; A blocking insulating film formed on the charge trap layer; And And a gate electrode formed on the blocking insulating film. The flash memory of claim 1, wherein one side of the fin region adjacent to the source region or the drain region has a higher doping concentration than the other portion.

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