JPH01289282A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To electrically erase a stored data by means of a comparatively low erasure voltage by a method wherein one part of an insulating film between a floating gate and a diffusion region is formed to be thin as compared with other parts. CONSTITUTION:A gate oxide insulating film 66 is formed on a P-type silicon substrate 60 where a source diffusion region 69a and a drain diffusion region 69b have been formed. After that, a part of a tunnel film 85 is etched to the thinner than a film thickness of the gate oxide insulating film 66 and a floating gate 64, an insulating interlayer film 67 and a control gate 63 are formed on it. When the gate 63 is set to an earth voltage and a high viltage is applied to a source 62; a high electric field is applied to the tunnel film 65 formed between the diffusion region 69a and the floating gate 64 and the Fowler- Nordheim tunneling effect is caused. By this setup, a data can be erased electrically by means of a comparatively low erasure voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memory devices such as programmable read-only memory devices (hereinafter referred to as ROM) in which data can be electrically erased.

[Prior art] Erasable and programmable ROM (hereinafter referred to as EP
It's called ROM. ) can be generally classified into ultraviolet erasing type and electrically erasing type. Here, the above-mentioned ultraviolet erasing type EPROM can erase stored data by irradiating the integrated circuit package with ultraviolet rays during erasing. This ultraviolet erasing type EPRO
As mentioned above, M has the disadvantage of being expensive because it requires a package that allows ultraviolet rays to pass through. On the other hand, electrically erasable EPr (OM) (hereinafter referred to as EEFROM).

) can be constructed using an inexpensive plastic material as a package, so it has the advantage that manufacturing costs can be lowered compared to ultraviolet erasable EPROMs.

Figure 4 shows the E proposed at rsscc in 1980.
EFROM (hereinafter referred to as the first conventional example).

), and this first conventional example EEFROM has a selection transistor M21 and a memory transistor M2.
Consists of 2.

FIG. 5A shows an EEPROM transistor proposed in Japanese Patent Publication No. 62-3992 (referred to as a second conventional example).

), and FIG. 5(B) is the circuit diagram of FIG. 5(A).
FIG. 2 is a longitudinal cross-sectional view showing the structure of a PROM. The EEFROM 35 of the second conventional example has a control gate 33 and a floating gate 34, and incorporates the selection transistor of the above-mentioned first conventional EEPROM.

FIG. 6 is a circuit diagram showing a circuit in which the transistors M41 to M44 of the EEPROM of the second conventional example are arranged in a matrix array of two vertically and two horizontally. 6th
In the figure, each output terminal of row decoder 45 is connected to a word line 41.42, and each output terminal of column decoder 46 is connected to a bit line 43.44. The word line 41 is connected to the EEPROM transistor M41. M42
word line 42 is connected to each gate of EEPRO
M transistor M43. Connected to each gate of M44. Further, the bit line 43 is connected to the EEPROM transistor M41. The bit line 44 is connected to each drain of the EEPROM transistor M42. M
44 drains. Furthermore, EEPROM
The sources of transistors M41 to M44 are connected to ground.

When programming off the transistor M41 of the second conventional EEPROM configured as described above, the row decoder 45 applies a programming voltage of, for example, 21 V to the word line 41 and sets the word line 42 to the ground potential. . Further, the column decoder 46 outputs a program voltage of, for example, 21V to the bit line 43, and
Let be the ground potential.

By applying the programming voltage as described above, avalanche breakdown occurs at the drain end between the floating gate and drain of transistor M41, and hot electrons generated by this avalanche breakdown are trapped in floating gate 34 of transistor M41. Ru.

At this time, if the thickness of the gate insulating film 36 between the floating gate 34 and the P-type silicon substrate 37 is relatively thin, a program voltage of 21V is applied to the drain of the transistor M43, and the control gate of the transistor M43 is connected to the ground. Since the transistor M43 is at a potential, a Fowler-Nordheim tunneling effect occurs, which may erase data stored in the transistor M43, for example. Therefore, in order to prevent the data of the transistor M43 from being erroneously erased when programming the transistor M41, the thickness of each gate insulating film 36 of each of the transistors M41 to M44 must generally be 200 Å or more. However, in order to downsize the EEPROM transistor and simplify the peripheral circuitry, it is necessary to reduce the thickness of the gate insulating film 36 of the EEPROM transistor and lower the drain voltage during programming.

Figure 7 shows the E proposed in JP-A No. 62-3992.
EFROM (hereinafter referred to as the third conventional example).

) is a circuit diagram of a transistor. The transistor of this third conventional EEFROM has a control gate 5.
3. Bloating gate 54, erase gate 55,
It is composed of a drain 51 and a source 52.

[Problems to be Solved by the Invention] However, the above-mentioned first conventional EEPROM has the following problems:
Since the EEPROM is composed of two transistors, a selection transistor and a memory transistor, there is a problem in that the transistors of the EEPROM are relatively large.

Furthermore, in the EEFROM of the second conventional example described above, 1
In order to prevent data stored in the other transistor connected to the same bit line from being accidentally erased when programming one transistor, a relatively thick gate insulating film 36 is formed and the data is erased. When doing so, there was a problem in that a relatively high erase voltage was required.

Furthermore, since the EEFROM of the third conventional example has three gates 53 to 55 as described above, it is necessary to form three polysilicon layers, which complicates the manufacturing process. Moreover, the EEFROM of this third conventional example has a second
Similar to the conventional EEPROM, there are problems in that it is generally necessary to form a relatively thick gate insulating film of about 500 layers, and a relatively high erase voltage is required.

An object of the present invention is to solve the above problems, to make it possible to reduce the size of a semiconductor memory device compared to a conventional example, and to make the gate insulating film thinner than a conventional example. An object of the present invention is to provide a semiconductor memory device that can electrically erase data stored in the semiconductor memory device with a relatively low erase voltage.

[Means for Solving the Problems] The present invention provides first and second diffusion regions for a first electrode and a second electrode formed at a predetermined distance apart in a semiconductor substrate; a floating gate formed on the first and second diffusion regions via a first insulating film; a control gate formed on the floating gate via a second insulating film; In the semiconductor memory device, a portion of the first insulating film between the floating gate and the first diffusion region is connected to the first diffusion region. It is characterized by being formed thinner than other parts of the insulating film.

In the invention, data is written by applying predetermined DC voltages between the first electrode and the second electrode and between the first electrode and the control gate to trap electrons in the floating gate. The data is erased by applying a predetermined DC voltage between the control gate and the first electrode to erase the electrons trapped in the floating gate.

Further, in the above invention, after erasing data by applying a high voltage between the control gate and the first electrode to erase electrons trapped in the floating gate, the first and second diffusion The method is characterized in that the threshold voltage of the semiconductor memory device is changed by changing the amount of impurity implanted into the channel portion in the semiconductor substrate between regions.

[Operation] In the semiconductor memory device configured as above, a predetermined DC voltage higher than, for example, a data read voltage is applied between the first electrode and the second electrode and between the first electrode and the control gate, respectively. When the above second
Avalanche breakdown occurs at the end of the electrode, and electrons generated by the avalanche breakdown are trapped in the floating gate to write data.

Next, when a predetermined DC voltage is applied between the control gate and the first electrode, the first insulating film between the floating gate formed thinly as described above and the first diffusion region changes. In some cases, a Fowler-Nordheim tunneling effect occurs. The electrons trapped in the floating gate move to the first electrode via the diffusion region of the first electrode due to the tunneling effect, thereby erasing the electrons trapped in the floating gate, thereby causing data is erased.

Further, after the data is erased, the threshold voltage of the semiconductor memory device can be increased by changing the amount of impurity implanted into the channel portion in the semiconductor substrate between the first and second diffusion regions. can change. Therefore,
In erasing the data, more charges are erased than the amount of electrons trapped in the floating gate of the semiconductor memory device, resulting in a state of over-disappearance of trapped electrons, and the semiconductor memory device exhibits depletion mode characteristics. This can be prevented by controlling the threshold voltage described above.

[Embodiment] FIG. 1(A) shows an N-channel MO9 field effect transistor (hereinafter referred to as N
It's called MOS FET. ) is the circuit diagram of the first
Figure (B) shows the NMOSFE of the EEPROM in Figure 1 (A).
It is a longitudinal cross-sectional view showing the structure of T.

This NMOSFET has a drain 61, a source 62, a control gate 63, and a floating gate 6.
The floating gate 64 is formed of 4 electrodes on the source diffusion region 69 of the P-type silicon substrate 60.
It is characterized in that a relatively thin insulating film (hereinafter referred to as a tunnel film) 65 with a thickness of 80 to 150 thick is formed below the film so that the Fowler-Nordheim tunneling effect can occur.

Hereinafter, the EEPr (OM's NMOS PET
The manufacturing method will be explained.

First, a field oxide film 70 is formed on a P-type silicon substrate 60.
After forming the control gate 63, which will be formed later.
For example, injection volume 5×lOl 1/cm″
~1xlO'3/cffl" of boron is implanted at an implantation energy of 50 KeV. By changing the implantation amount of this impurity boron, that is, into the channel portion located between both diffusion regions 69a and 69b that will be formed later. By changing the implantation amount of , it is possible to control the threshold voltage vth of the NMOS FET after erasing the stored data.

Furthermore, arsenic is implanted with an implantation energy of, for example, 8 x 1014/cm'' into the upper right side of the source diffusion region 69a in FIG. 1B and directly below the tunnel film 65 to be formed. Implant at 70KeV.

Next, a gate oxide insulating film 66 with a thickness of approximately 300 layers is formed on the P-type silicon substrate 60 on which the source diffusion region 69a and the drain diffusion region 69b are formed, and then the gate oxide insulating film 66 formed as described above is tunnel membrane 65 in
Etching is performed so that the thickness of the gate oxide insulating film 66 is relatively thinner than that of the other gate oxide insulating film 66 by, for example, 80 to 150 layers. Here, a portion of the tunnel film 65 is located on the diffusion region 69a of the source 62.

Further, the gate oxide film 66 from which the tunnel oxide film 65 has been etched is subjected to dilute oxidation treatment at a temperature of 950° C. for one hour, for example, to form the tunnel film 65.

Next, a floating gate 64 is formed on the gate oxide film 66 and the tunnel film 65. Furthermore, after forming an insulating interlayer film 67 of a predetermined thickness on the floating gate 64, a control gate 63 is formed on the insulating interlayer film 67. Here, as described above, the tunnel film 65
Since the thickness of the gate oxide insulating film 66 is smaller than that of the gate oxide insulating film 66, parts 64a and 63a of the floating gate 64 and the control gate 63 located directly above the tunnel film 65 protrude downward. It becomes the shape.

Furthermore, using the control gate 63 as a mask, arsenic is implanted into the P-type silicon substrate 60 with an implantation energy of 70 KeV, for example, at an implantation amount of 6×I O "7 cm", and the implant is placed directly under the gate 63.64 in between. A pair of N-type diffusion regions 69a and 69b are then formed. Here, the first
The diffusion region 69a on the left side of the figure (B) is a source diffusion region, and the diffusion region 69b on the right side of the figure is a drain diffusion region. Here, on the upper right side of the diffusion region 69a in the figure,
Tunnel film 65, protrusion 6 of floating gate 64
Diffusion region 69a is formed such that protrusion 63a of control gate 63 and 4a1 are located.

Further, the diffusion region 69a has a length in the horizontal direction in the drawing that is longer than the length in the horizontal direction in the drawing of the diffusion region 69b.

Finally, after forming an insulating film 68 on the control gate 63, contact holes 62h and 6th are formed on the diffusion regions 69a and 69b, respectively, by a known method. Next, contact hole 62h.

Aluminum electrodes are inserted and formed in 61h, respectively, thereby forming a source 62 and a drain 61, respectively.

The operation of the NMOSFET configured as described above will be explained below separately into (1) data programming operation and (2) data erasing operation.

(1) Data programming operation When programming the NMOSFET of this EEPROM to OFF and writing data, a high voltage Vl) of, for example, +2.5V is applied to both the drain 61 and gate 63 of this NMOSFET, and the The source 62 is set at ground potential. At this time, the above NMO
Avalanche breakdown occurs between the drain 61 and control gate 63 of the SFET, and hot electrons generated by this avalanche breakdown are trapped in the floating gate 64. Here, as shown in FIG. 1(B),
The floating gate 64 is surrounded by insulating films 66, 67 .
68, the trapped electrons are applied to the source 62, for example, at a high voltage Vl)I), as will be described in detail later.
It does not disappear under normal conditions unless .

As described above, the threshold voltage vth of the NMOSFET of the EEPROM in which hot electrons are trapped in the floating gate 64 has a voltage value of, for example, 6V to 9V, which is higher than the normal data read voltage of, for example, 5V. Therefore, even if a data read voltage of, for example, 5V is applied to the gate of this NMOS FET, this NMOS FET does not turn on, but maintains an off state.

(2) Data erasure operation
When erasing the data of MOSFET, this NMOSF
The drain 61 of the ET is set in a floating state or at ground potential, the gate 63 is set at ground potential, and a high voltage Vl)l) of, for example, 12.5 V is applied to the source 62. At this time, the high voltage vp is applied to the tunnel film 65 formed between the diffusion region 69a of the source 62 and the floating gate 64.
The addition of a high electric field due to p causes the Fowler-Nordheim tunneling effect, which causes electrons to move from the floating gate 64 to the source 62.

Therefore, the electrons trapped in the floating gate 64 are erased.

Here, since it is difficult to control the amount of charge of the electrons that disappear, more charge is erased than the amount of charge of the trapped electrons, resulting in a state in which holes are trapped (hereinafter referred to as an over-disappearance state). ing. Therefore, the NMOSFET in this state has depletion mode characteristics.

In order to prevent the NMO3FET from entering the depletion mode, a selection transistor is required in the first conventional example, but in this example, the threshold voltage vth is controlled by changing the doping amount of the channel. As a result, the threshold voltage vth is set to approximately 1 to 2V.

When reading data stored in the NMOSFET set as above, applying a data read voltage to the gate of the NMOSFET turns on the NMO5FET, and setting the gate of the NMOSFET to, for example, ground potential turns off the NMO8FET. . Therefore, it is possible to erase the data stored in the NMOSFET of this EEPROM.

Figure 2 shows the four EEPRs in Figure 1 (A) and (B) above.
FIG. 2 is a circuit diagram showing a first embodiment in which OM NMOSI"ET M71 to M74 are arranged in a matrix array. FIG.

In FIG. 2, each output terminal of row decoder 76 is connected to a word line 71.72, and each output terminal of column decoder 77 is connected to a bit line 73.74. Word line 71 is NMOSFETM71. connected to each gate of M72, word line 72 is connected to each gate of NMOS FET
Connected to each gate of M 73 and M 74. Bit line 73 is connected to NMOSFET M71. connected to each drain of M73, bit line 74 is an NMOSFET
M72. Connected to each drain of M74. moreover,
The sources of NMOSFETM71 to M74 are connected together and connected to the output terminal of erase circuit 78 via erase line 75.

In the EEPROM configured as above, after erasing the data stored in all NMOSFETs M71 to M74, one NMOSFET M71
The operation when programming off is described below.

First, row decoder 76 operates on word line 7! , 72 are at ground potential, and the column decoder 77 is connected to the bit lines 73, 74.
is in a floating state or at ground potential. Then,
The erase circuit 78 applies +12.5 to the erase line 75, for example.
A high voltage vpp of V is applied. As a result, the electrons trapped in the floating gates 64 of all NMOS FETs M71 to M74 move to the source 6I due to the Fowler-Nordheim tunneling effect, and at this time, the electrons trapped in the floating gates 64 are erased.

Next, in order to perform a data write operation, the row decoder 76 applies the high voltage Vpp to the word line 71,
Meanwhile, the column decoder 77 applies the high voltage vpp to the bit line 73. Further, the erase circuit 78 sets the erase line 75 to the ground potential. This data writing operation is similar to the conventional example, and in only one NMOSFETM71 of the EEPROM in FIG.
Avalanche breakdown occurs at the end of the drain 61 between the control gate 63 and the drain 61 of the TM71, and this avalanche breakdown generates thermoelectrons. These generated thermoelectrons are trapped in the floating gate 64, and as described above, this NMOSFET M71
The threshold voltage vth is higher than the normal data read voltage, which is, for example, +5V, and is, for example, a voltage of +6V to +9V.

Meanwhile, the remaining three NMOSFETs M72 to M7
The threshold voltage of 4 is held at a voltage of, for example, +3.sup.4, and the three NMOSF'ETMs 72 to M74 are not programmed off and no data is written.

Next, one NMOS FET (
Hereinafter, it will be referred to as the selected NMOSFET. ), the row decoder 76 applies, for example, +5V to the word line (hereinafter referred to as the selected word line) connected to the NMOSFET from which the data is read.
A data read voltage of H level is applied, and on the other hand,
Word lines that are not connected to NMOSFETs from which data is read (hereinafter referred to as unselected word lines) are set to ground potential. Further, the erase circuit 78 sets the erase line 75 to the ground potential.

Next, a bit line (hereinafter referred to as a selected bit line) connected to an NMOSFET from which data is read.

) is connected to a sense amplifier (not shown), and the voltage of the selected bit line connected to the source of the selected NMOSFET is sent to the sense amplifier.

Thereby, the data of the selected NMOSFET can be read. Here, the above selected NM
If the OSFET is programmed off, the selected NMOSFET remains off even if the data read voltage is applied to the gate of the selected NMOSFET via the selected word line. The selected bit line connected to the selected NMOSFET is pulled up to an H level voltage of +5V, for example.

Additionally, if the selected NMOSFET is not programmed off, when the data read voltage is applied to the selected word line, the selected NMOSFET is turned on and the selected NMOSFET is turned on.
The selected bit line connected to the SFET is at ground potential. Therefore, as described above, depending on whether the selected NMOSFET is programmed off or not programmed off, the selected bit line becomes the H level voltage and the ground potential, respectively. The above selected N M
Data can be read from the OS FET by the sense amplifier.

Figure 3 shows the four EEPRs shown in Figure 1 (A) and (B) above.
FIG. 7 is a circuit diagram showing a second embodiment in which OM NMOSFETs M81 to MB2 are arranged in a matrix array.

In FIG. 3, each output terminal of row decoder 86 is connected to a word line 81.82, and each output terminal of column decoder 87 is connected to a bit line 83.84. Word line 81 is NMOSFETM81. Word line 82 is connected to each gate of NMOSFET MB2.
．． 84 gates. Also bit line 83
is NMOSFET M81. Connected to each source of MB2, bit line 84 is NMO8FETM821M84
connected to each source. Furthermore, NMOS FETTM
The drains of 81 to MB2 are connected together and connected to the output terminal of a reset circuit 88 via a reset line 85.

In the EEFROM configured as above, after programming all NMOSFETs M81 to MB2 off, that is, writing data to all NMOSFETs M81 to MB2, NMOSFET M
The operation of erasing data stored in 81 will be described below.

First, row decoder 86 decodes all word lines 81.8
2 is applied with a high voltage Vl)p, for example +12.5V, while the column decoder 87 applies a high voltage Vl)p to all the hit lines 83
．． 84 is set to ground potential. Next, the reset circuit 88
applies a high voltage Vl)l), for example ++2.5V, to the reset line 85. This is all (
7) Avalanche breakdown occurs at the drain end between the floating gate and drain of NMOSFET M81 or MB2, and the hot electrons generated by this avalanche breakdown are trapped in the floating gate, and at this time, as described above, all NMOS
The threshold voltage vth of the FET is higher than the normal data read voltage of 5V, for example, from +6V to +9V.

Row decoder 86 then deactivates word line 8 to erase the data stored in one NMOSFET M81.
1 is at ground potential, while the word line 82 is in a floating state, and the column decoder 87 applies a high voltage Vl)l) of, for example, 12°5 V to the bit line 83,
On the other hand, the bit line 84 is set to ground potential. At this time, a high electric field is applied by the high voltage vpp to the tunnel film formed between the floating gate and source diffusion regions 69a and 69b of the selected NMOSFET M81, thereby causing the NMOSFET M81 to
The electrons trapped in the floating gate of M81 disappear. Therefore, the data stored in one NMOSFET M81 is erased, while the remaining three NMOSFETs
The data stored in OSFET MB2 or MB2 is held as is.

Then, one selected NMOS of the above EEFROM
When reading data from a FET, column decoder 86 selects a word line (hereinafter referred to as a selected word line) connected to the NMOSFET from which data is to be read.

) is applied with an H-level data read voltage of, for example, +5■, and the negative word line (hereinafter referred to as an unselected word line) not connected to the NMOSFET from which data is read is grounded. Further, the reset circuit 88 sets the reset line 85 to ground potential.

Next, the bit line connected to the selected NMOSFET (hereinafter referred to as the selected bit line).
Connect only the above selected NMOS to the sense amplifier.
The voltage of the selected bit line connected to the source of the FET is sent to the sense amplifier. Thereby, the data of the selected NMOSFET can be read.

Here, even if the data read voltage is applied to the gate of the selected NMOSFET via the selected word line when the selected NMOSFET is programmed off,
The selected NMOSFET remains in the off state, and the selected bit line connected to the selected NMOSFET is pulled up to an H level voltage, for example +5.

Further, when the selected NMOSFET is not programmed to turn off, when the data read voltage is applied, the selected NMOSFET is turned on, and the selected bit is connected to the selected NMOSFET. The line is at ground potential.

As described above, depending on the state in which the selected NMOSPET is programmed off and the state in which it is not programmed off, the selected bit line becomes the H level voltage and the ground potential, respectively. Data can be read from the selected NMOSFET by the upper three sense amplifiers.

In the circuit of the second embodiment configured as shown in FIG. 3, unselected word lines are programmed in a floating state, and at this time, due to capacitance coupling between the unselected word lines and bit lines, The voltage on the word line increases and the NMO of the EEPROM
There is a possibility that incorrect data will be read when reading data from the SFET. Therefore, it is necessary to form each word line and each bit line so as to reduce the amount of capacitance coupling by increasing the distance between each word line and each bit line.

Therefore, when designing the circuit of the second embodiment, it is necessary to configure it so as to prevent malfunctions as described above.

As explained above, the tunnel film 6 is directly under the floating gate 64 and on the diffusion region 69a of the source 62.
5 to configure the NMOSFET of the EEPROM, there is no need to provide a selection transistor unlike the first conventional example, and the tunnel, which is an insulating film between the floating gate 64 and the diffusion region 69a of the source 62, is not required. The film 65 can be made of an insulating film that is thinner than the conventional example in which the number of people is approximately 80 to 150, for example. Therefore, E.E.
There is an advantage that the erasing voltage for erasing data in the PROM can be set to a lower voltage than in the conventional example.

[Effects of the Invention] As detailed above, according to the present invention, the first electrode and the second electrode
In a semiconductor memory device comprising first and second diffusion regions for electrodes, a floating gate, and a control gate, the first insulating film between the floating gate and the first diffusion region is Since the first insulating film is formed to be thinner than the other portion, a portion of the first insulating film can be used as a tunnel film when erasing data. Therefore, there are advantages in that the thickness of the tunnel film can be made thinner than in the conventional example, and data can be electrically erased with a relatively low erase voltage.

[Brief explanation of the drawing]

FIG. 1(A) is a circuit diagram of an NMOSFET of an EEPROM which is an embodiment of the present invention, FIG. 1(B) is a vertical cross-sectional view showing the structure of the NMOSFET of FIG. 1(A), and FIG. 4 NMOS of EEPROM in Figure 1 (A)
A circuit diagram showing a first embodiment of a circuit in which FETs are arranged in an array.
A circuit diagram showing a second embodiment of a circuit in which OSFETs are arranged in an array; FIG. 4 is a circuit diagram of an EEPROM equipped with a selection transistor and a memory transistor, which is the first conventional example; ) is the MO of the second conventional EEPROM.
SFET circuit diagram, Figure 5 (B) is a vertical cross-sectional view showing the structure of the MOSFET in Figure 5 (A), Figure 6 is the four M08Fs of the EEFROM in Figure 5 (A).
A circuit diagram showing a circuit in which ETs are arranged in an array. Figure 7 is a third conventional example of an EEPROM MOSFE.
It is a circuit diagram of T. 60... P-type silicon substrate, 61... Drain, 62... Source, 63... Control gate, 64... Floating gate, 65... Tunnel film, 69a... Source diffusion region , 69b... Drain diffusion region, 67.68... Insulating film. Patent applicant: Lico Co., Ltd. Attorney, Patent attorney: Mr. Maeda and one other person Figure 1 (B) Figure 2 on the 6th

Claims (3)

[Claims] (1) first and second diffusion regions for the first and second electrodes formed at a predetermined distance apart in the semiconductor substrate; and a first and second diffusion region formed on the first and second diffusion regions. a floating gate formed via a first insulating film, a control gate formed on the floating gate via a second insulating film, and a first floating gate connected to the first and second diffusion regions, respectively. and a second electrode, a part of the first insulating film between the floating gate and the first diffusion region is compared with another part of the first insulating film. A semiconductor memory device characterized in that it is formed thinly. (2) Data is written by applying predetermined DC voltages between the first electrode and the second electrode and between the first electrode and the control gate to trap electrons in the floating gate. Claim 1, wherein data is erased by applying a predetermined DC voltage between the control gate and the first electrode to erase electrons trapped in the floating gate.
1. Semiconductor device described in Section 1. (3) After data is erased by applying a high voltage between the control gate and the first electrode to erase the electrons trapped in the floating gate, the data is erased between the first and second diffusion regions. 3. The semiconductor memory device according to claim 2, wherein the threshold voltage of the semiconductor memory device is changed by changing the amount of impurity implanted into the channel portion in the semiconductor substrate.