JPH05110038A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To provide the NAND cell EEPROM capable of high integration by shortening the selective gate length. CONSTITUTION:Source drain diffused layers in NAND cells and common source diffused layers connecting to adjacent NAND cells are composed of n type diffused layers 9 simultaneously formed by the ion implanting step in low dosage not exceeding 1X10<15>/cm<2> thereby enabling the gate length of source side selective gate to be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAND cell type non-volatile semiconductor memory device (EEPROM) using an electrically rewritable memory cell having a structure in which a floating gate and a control gate are laminated.

[0002]

2. Description of the Related Art Conventionally, an EEPROM having a plurality of memory cells connected in series has been proposed as an EEPROM which can be highly integrated.
An AND cell type EEPROM is known. One memory cell has a FETMOS structure in which a floating gate and a control gate are laminated on a semiconductor substrate via an insulating film, and a plurality of memory cells adjacent to each other are connected in series to share a source and a drain. Connected to form a NAND cell. Such NAND cells are arranged in a matrix to form a memory cell array. The drains on one end side of the NAND cells arranged in the column direction of the cell array are commonly connected to the bit line via the select gates, and the sources on the other end side are also connected to the common source diffusion layer to be the source lines via the select gates. ing. The gate electrodes of the control gates and select gates of the memory cells are commonly connected as control gate lines (word lines) and select gate lines in the row direction of the memory cell array. The operation of this NAND cell type EEPROM is as follows.

Data writing is performed sequentially from the memory cell farther from the bit line. To explain the case of the n-channel, a high potential Vpp (for example, 20V) is applied to the control gate of the selected memory cell, and the control gate and the select gate of the non-selected memory cell on the bit line side from this are applied. An intermediate potential VM (for example, 10V) is applied. 0 V (for example, "1") or an intermediate potential VM (for example, "0") is applied to the bit line depending on the data. At this time, the potential of the bit line is transmitted to the drain of the selected memory cell through the selection gate and the non-selected memory cell.

When there is data to be written (“1” data), a high electric field is applied between the gate and drain of the selected memory cell, and electrons are tunnel-injected from the substrate to the floating gate. As a result, the threshold value of the selected memory cell moves in the positive direction. When there is no data to be written (“0” data), there is no threshold change.

To erase data, a high potential is applied to a p-type substrate (n-type substrate and a p-type well formed therein in the case of a well structure), and the control gate and select gate of the selected memory cell are set to 0V. Then, a high potential is applied to the control gates of the non-selected memory cells. As a result, in the selected memory cell, electrons in the floating gate are emitted to the substrate, and the threshold value moves in the negative direction.

For data reading, a non-selected memory cell on the bit line side of the selected gate and the selected memory cell is turned on, and 0V is applied to the gate of the selected memory cell. At this time, by reading the current flowing through the bit line, "0",
The determination of "1" is made.

Such a conventional NAND cell type EEPRO
In M, in the data write mode, the intermediate potential VM is applied to the bit line which is not written. Therefore, in order to prevent data destruction in non-selected NAND cells,
It is essential to provide a select gate between each NAND cell and the bit line. This is because without this selection gate, the memory cell on the bit line side of the non-selected NAND cell in which all the control gates are 0 V is given the intermediate potential of the bit line to the drain and enters the erase mode.
A select gate is also provided on the source side of the NAND cell in order to prevent current from flowing.

Further, the source and drain diffusion layers in the region sandwiched by the respective gate portions of the NAND cell have a reduced concentration to suppress the exudation of impurities in the gate length direction as much as possible. As a result, the gate length of each memory cell is shortened to achieve high integration.

However, even if the source and drain diffusion layers of each memory cell have a low concentration, the common source diffusion layer at one end of the NAND cell should have a sufficiently high concentration to reduce the resistance in order to secure the cell current. Was needed. When the common source diffusion layer is made to have a high concentration in this way, the gate length of the source side select gate cannot be shortened because the impurity leakage of the diffusion layer must be taken into consideration.
This hinders the high integration of the EEPROM.

[0010]

As described above, the conventional N
In the AND cell type EEPROM, the concentration of the common source diffusion layer is higher than the concentration of the source and drain diffusion layers between the cells, so that the gate length of the source side select gate of the NAND cell is prevented from being shortened, which results in high integration of the EEPROM. There was a problem that it was hindered. The present invention has been made in consideration of such circumstances, and it is possible to realize high integration of N.
It is an object to provide an AND cell type EEPROM.

[0011]

In the NAND cell type EEPROM according to the present invention, firstly, the source / drain diffusion layers in the NAND cell and the common source diffusion layer serving as the source line have the same dose amount by the same ion species. 1 x 10 ¹⁵ / cm ²
It is characterized in that it is composed of the following ion-implanted layers.

NAND cell type EEPROM according to the present invention
Secondly, the common source diffusion layer is a first diffusion layer formed at the same time as the source and drain diffusion layers in the NAND cell, and the first diffusion layer is separated from the source side select gate end by a predetermined distance. And a high-concentration second diffusion layer formed in a stacked state.

[0013]

According to the first aspect of the present invention, the common source diffusion layer is NA
By using a low-dose ion implantation layer together with the source and drain diffusion layers in the ND cell, the exudation of impurities under the source side select gate of the NAND cell is reduced,
Therefore, the select gate length can be shortened sufficiently. As the number of memory cells in one NAND cell increases, the channel resistance of this NAND cell increases accordingly. Therefore, even if the concentration of the common source diffusion layer is lowered in this manner, the adverse effect on the characteristics is small. Therefore, high integration can be achieved without impairing the characteristics.

According to the second invention, the common source diffusion layer is a double diffusion layer, and the resistance of the common source diffusion layer can be kept sufficiently small. Moreover, by forming the high-concentration diffusion layer in the common source diffusion layer away from the end of the select gate, the influence of the high-concentration diffusion layer impurities exuding below the select gate is prevented.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an EEPRO according to an embodiment of the present invention.
FIG. 2 is a plan view showing an M NAND cell, and FIGS. 2 (a) and 2 (b) are sectional views taken along the lines AA ′ and BB ′. Moreover, FIG. 3 shows NA
It is an equivalent circuit of an ND cell.

In this embodiment, four memory cells M1 ...
M4 is connected in series in such a manner that the source and drain diffusion layers are shared by adjacent ones to form a NAND cell. Such NAND cells are arranged in a matrix to form a cell array. The drain at one end of the NAND cell is connected to the bit line BL via the first selection gate S1, and the source at the other end is connected to the common source line (common source diffusion layer) via the second selection gate S2. ing. The control gates CG1 to CG4 of each memory cell are arranged in a direction intersecting the bit line BL to form a word line WL.

In this embodiment, four memory cells constitute one NAND cell, but in general, 2 n (n = 1, 2, ...) Memory cells constitute one NAND cell. can do.

The specific memory cell structure is as shown in FIG. A p-type well 1'is formed on the n-type silicon substrate 1, and memory cells are arrayed in the p-type well 1 '. The peripheral circuit will be formed in a p-type well different from the memory cell. Four memory cells and two select gates are formed in a region surrounded by the element isolation insulating film 2 of the p-type well 1 '.

Each memory cell has 5 to 5 on the p-type well 1 '.
The floating gates 4 (41 to 44) are formed by the first layer polycrystalline silicon of 50 to 400 nm formed through the first gate insulating film 31 made of a thermal oxide film of 20 nm, and the heat of 15 to 40 nm is formed thereon. The control gates 6 (61 to 64) are formed by the second layer polycrystalline silicon having a thickness of 100 to 400 nm formed through the second gate insulating film 5 made of an oxide film. The n-type layer 9 serving as the source / drain diffusion layer of each memory cell is shared by adjacent ones, and four memory cells are connected in series.

At both ends of the NAND cell, a gate insulating film 3 made of a thermal oxide film of 5 to 40 nm is formed on the p-type well 1 '.
A select gate having gate electrodes 45 and 46 formed of the first-layer polycrystalline silicon is formed via the gate electrode 2.
Here, the gate insulating film 32 may be the same as the first gate insulating film 31. Wirings 65 and 66 made of the second polycrystalline silicon are arranged on the gate electrodes 45 and 46 so as to overlap each other. The gate electrodes 45 and 46 and the wirings 65 and 66 are connected by through holes at predetermined intervals to reduce the resistance.

The floating gates 41 to 44 and control gates 61 to 64 of each memory cell, and the gate electrode 4 of the select gate.
5 and 46 and wirings 65 and 66 are patterned and aligned in the channel length direction using the same etching mask. The n-type layer 9 serving as a common source diffusion layer connected to the source and drain diffusion layers in the NAND cell and the adjacent NAND cell is formed by ion implantation of arsenic or phosphorus using these electrodes as a mask. The dose is 1 × 10 ¹⁵ / cm ² It is set as follows. The substrate on which the elements are formed is covered with the CVD insulating film 7, and the bit line 8 is provided thereon by the Al film.

In such a structure, the coupling capacitance C1 between the floating gate 4 and the substrate of each memory cell is set smaller than the coupling capacitance C2 between the floating gate 4 and the control gate 6. This relationship is obtained by extending the floating gate 4 from above the element region to above the element isolation region, as shown in FIG.

Explaining with concrete parameters,
According to the rule of 1 μm pattern, the floating gate 4 and the control gate 6 have a width of 1 μm and a channel width of 1 μm.
The floating gate 4 is 1 μm on both sides on the element isolation insulating film.
We are extending each. The first gate insulating film 31 is, for example, a 10 nm thermal oxide film, and the second gate insulating film 5 is a 28 nm thermal oxide film. When the dielectric constant of the thermal oxide film is ε, C1 = ε / 0.02 and C2 = 3ε / 0.035. Therefore, C1 <C2. FIG. 4 shows two adjacent NAND cell parts connected to two bit lines BL1 and BL2.
The M operation will be described.

First, in the data erasing, the memory cells constituting the NAND cell are collectively erased. Therefore, in this embodiment, the gate electrodes SG1 and SG2 of the first and second select gates S1 and S2 and the control gates CG1 to CG4 of all memory cells in the NAND cell are set to 0V, and the n-type substrate 1 and the p-type High potential V boosted to well 1 '
pp '(eg 18V) is applied. Bit line BL1,
High potential Vpp 'is also applied to BL2.

As a result, an electric field is applied between the control gates of all the memory cells and the p-type well 1 ', and electrons are emitted from the floating gate 4 to the p-type well 1'by a tunnel current. As a result, the threshold values of all the memory cells (M1 to M8 in the case of FIG. 4) are moved in the negative direction, and the "0" state is set.

Next, data writing is sequentially performed from the memory cell on the source line side in the NAND cell, that is, the memory cell farther from the bit line. Now, memory cell M4
A case of selectively writing "1" data in (cell A surrounded by a broken line in FIG. 4) will be described. The gate electrode SG2 of the second select gate S2 on the source side is set to 0V, and the control gate CG4 is set. A high potential Vpp (for example, 16 to 18 V) is applied, and the remaining control gates CG1 to CG3 and the gate electrode SG1 of the drain side first select gate S1 are at an intermediate potential VM (between the power supply potential Vcc and the high potential Vpp). For example, (1 /
2) Vpp) is applied. Further, the selected bit line BL1 is supplied with 0V as the "L" level potential, and the non-selected bit line BL2 is supplied with the intermediate potential VM. The p-type well is set to 0V and the n-type substrate is set to Vcc.

As a result, in the selected cell A, 0 V of the bit line BL1 is transmitted to the drain, a high electric field is applied between the cell and the control gate, and electrons are injected into the floating gate. As a result, in the cell A, the threshold value moves in the positive direction and "1" is written.

Another memory cell M connected to the bit line BL1
In 1 to M3, the write mode is set, but the electric field is small and there is no threshold change. In the memory cells M5 to M7 on the non-selected (or "0" write) bit line BL2 side,
The control gate has an intermediate potential VM, the channel potential is Vcc, the potential difference is 3 to 4V, and there is no threshold change. Similarly, the memory cell M8 on the side of the bit line BL2 is also in the write mode, but its electric field is small and the threshold value does not change.

When the writing to the cell A is completed in this way, the memory cell M3 one above in the NAND cell is next.
Are similarly written to the memory cells M2,
Writing is done with M1.

In the above write operation, the high potential Vpp and the intermediate potential VM are applied to the control gate of the memory cell, but since the flowing current is only the tunnel current, it is at most 1 μA. At the time of batch erasing, the n-type substrate and the p-type well are raised to the high potential Vpp '. The current flowing at this time is the tunnel current and the leak current between the p-type well and the n-type substrate of the peripheral circuit kept at 0V. And this is also 10 μA
It is below. Therefore, the high potentials Vpp and Vpp 'used for writing and erasing (these may have the same value).
Can be sufficiently covered by a booster circuit provided inside the chip.

Further, since the current flowing due to the high potential at the time of selective writing is minute as described above, it is possible to simultaneously write data to all the memory cells connected to one control gate line (word line). That is, page mode writing can be performed, and high speed writing can be performed accordingly.

The data read operation will be described with reference to the cell A of FIG. 4. The gate electrodes SG1 and SG2 of the select gates will be described.
To the control gates CG1 to CG3 of the unselected memory cells M1 to M3, Vcc is also given as a potential for turning on the memory cells in the "1" state, and the control gate CG4 of the selected cell is set to 0V. To be done. Then, a read potential of 1 to 5V is given to the bit line BL1 connected to the selected cell, and the other non-selected bit line BL2 is set to 0V. As a result, data "0" or "1" is discriminated depending on whether or not a current flows through the bit line BL1.

As described above, in this embodiment, the common source diffusion layer is composed of the source and drain diffusion layers in the NAND cell and the n-type diffusion layer formed by low-dose ion implantation. The gate intestine of the selection gate can be shortened, and the EEPROM can be highly integrated.

FIG. 5 shows a NAND according to the second embodiment of the present invention.
A plan view of the cell type EEPROM is shown in correspondence with FIG. In this embodiment, the common source diffusion layer portion is N
A low-concentration n-type diffusion layer 9 formed at the same time as the source / drain diffusion layers in the AND cell, and a high-concentration n ⁺ layer formed on the diffusion layer 9. The mold diffusion layer 10 is used. n ⁺
The type diffusion layer 10 is formed at a predetermined distance from the end of the source-side second select gate. Others are the same as in the previous embodiment.

According to this embodiment, the common source diffusion layer has a sufficiently low resistance. Moreover, high concentration of n ⁺ Since the type diffusion layer 10 is formed away from the end of the select gate, the exudation of impurities under the select gate is prevented. Therefore, the gate length of the select gate can be made sufficiently small.

[0037]

As described above, according to the present invention, N
By making the concentration of the common source diffusion layer of the AND cell as low as the concentration of the source / drain diffusion layer in the NAND cell, the gate length of the source side select gate can be shortened, and thus the high integration of the EEPROM can be achieved. Can be planned.

[Brief description of drawings]

FIG. 1 is an EEPROM NAN according to an embodiment of the present invention.
The top view of D cell.

2 is an AA 'and a BB' of the NAND cell of FIG.
Sectional view.

FIG. 3 is an equivalent circuit diagram of the NAND cell.

FIG. 4 is an equivalent circuit diagram of two adjacent NAND cell units.

FIG. 5 is an N diagram of an EEPROM according to a second embodiment of the present invention.
The top view of an AND cell.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... N-type silicon substrate, 1 '... P-type well, 2 ... Element isolation insulating film, 3 ... Gate insulating film, 4 (41-44) ... Floating gate, 5 ... Interlayer insulating film, 6 (61-64) ... Control gate, 45, 46 ... Select gate electrode, 7 ... CVD insulating film, 8 ... Bit line, 9 ... N-type diffusion layer (source, drain, common source), 10 ... N ⁺ Type diffusion layer, M1 to M4 ... Memory cell, S1, S2 ... Select gate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seiichi Aridome 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Research Institute, Inc. (72) Inventor Tetsuro Endo Komukai-Toshiba, Kawasaki-shi, Kanagawa Town No. 1 Incorporated company Toshiba Research Institute

Claims (2)

[Claims] 1. An electrically rewritable memory cell in which a floating gate and a control gate are stacked on a semiconductor substrate via a gate insulating film, and source and drain diffusion layers are formed on both sides of these stacked gates. , NAND cells configured by connecting a plurality of drain diffusion layers in series so as to be shared by adjacent ones are arranged in a matrix, the drains on one end side of the NAND cells are connected to bit lines, and the source on the other end side is common. In a non-volatile semiconductor memory device connected to a source diffusion layer and having a control gate of each memory cell connected to a word line, a source / drain diffusion layer of each memory cell in the NAND cell and the common source diffusion layer Is the same dose with the same ion species 1 × 10 ¹⁵ / cm
² A nonvolatile semiconductor memory device comprising the following ion-implanted layer. 2. An electrically rewritable memory cell in which a floating gate and a control gate are stacked on a semiconductor substrate via a gate insulating film, and source and drain diffusion layers are formed on both sides of these stacked gates. , A plurality of NAND cells are connected in series so that adjacent drain diffusion layers are shared by adjacent ones, and the drains on one end side of the NAND cells are connected to a bit line through a first select gate. , A source on the other end side is connected to a common source diffusion layer serving as a source line via a second select gate, and a control gate of each memory cell is connected to a word line, The common source diffusion layer includes a first diffusion layer formed at the same time as the source and drain diffusion layers of the NAND cell and the first and second selection gates, and Nonvolatile semiconductor memory device characterized in that it is composed of a high concentration formed by overlapping a predetermined distance apart state second diffusion layer from said second selecting gate edge to the diffusion layer of the.