JPH01117365A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable the unrestricted and high-precision control of tunneling insulating film thickness and diffusion layer impurity concentration by a method wherein a diffusion layer is formed after the formation of a thin silicon oxide film capable of serving as a tunneling medium. CONSTITUTION:After the formation of a field oxide film 4, a silicon nitride film 3 and a silicon oxide film 2 thereunder are in that order removed by etching, and then a second thermal oxidation process is accomplished for the formation of a silicon oxide film 5 on the primary surface of a P-type silicon substrate 1. A prescribed part is removed by selective etching from the silicon oxide film 5, where a thin silicon oxide film 6 is formed to serve as a tunneling insulating film. Next, with a photoresist 7 serving as a mask, phosphorus ions 8 are implanted, which results in N-type diffusion layers 9 and 10. A process follows wherein the photoresist 7 is removed and, on the silicon oxide film 5 and the thin silicon oxide film 6, a phosphorus-doped polycrystalline silicon film is formed by vapor deposition. A photoetching process follows, whereby a floating gate electrode 11 is built, composed of a polycrystalline silicon film.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a manufacturing method capable of improving the write/erase characteristics of a semiconductor memory device comprising a floating gate field effect transistor.

Conventional technology Conventionally, electrically programmable and erasable ROM (EEPRO)
M；Electrically Erasable a
As one of the ndProgrammable ROM),
2. Description of the Related Art A semiconductor memory device having a floating gate structure in which writing and erasing is performed by tunneling injection is well known.

This floating gate type semiconductor memory device tunnels charges through a thin insulating film formed on a diffusion layer, accumulates charges in a floating gate electrode further formed on the insulating film, and raises the threshold voltage of the transistor. It is used to store information by changing the

To manufacture such a floating gate type semiconductor memory device, conventionally, a diffusion layer of a conductivity type opposite to that of the substrate is formed on the surface layer of a semiconductor substrate, and then the above diffusion layer is oxidized. A method of forming a thin silicon oxide film (hereinafter referred to as a tunneling insulating film) (hereinafter referred to as a tunneling insulating film) that can be used as a tunneling medium, and then forming a floating gate electrode on this film has been adopted. Also,
In order to form a thin tunneling insulating film on the diffusion layer with good control and stability, the impurity concentration of the diffusion layer is set to a relatively low concentration (1017 to 1018).
cIR-3).

Problems to be Solved by the Invention In recent years, with the increasing functionality and performance of semiconductor integrated circuits,
In EFROM as well, there is a growing demand for improved write/erase speed, and one way to achieve this is to increase the tunneling injection efficiency by increasing the impurity concentration in the diffusion layer under the tunneling insulating film to a high concentration of about 10 to 10 α. It will be done.

However, when the impurity concentration of the diffusion layer under the tunneling insulating film is increased, propagated oxidation occurs in the oxidation process to form the tunneling insulating film, and the film thickness can be controlled with good control.
It becomes difficult to form it stably. Furthermore, the problem of deterioration of film quality also occurs.

An object of the present invention is to provide a manufacturing method that can stably form a thin tunneling insulating film on a diffusion layer with high impurity concentration with good controllability.

Means for Solving the Problems The manufacturing method of the present invention, which can achieve the above objects, involves forming an insulating film to serve as a tunneling medium in a predetermined area on the surface of a semiconductor substrate of one conductivity type, and then forming a film under the insulating film. forming a first region of an opposite conductivity type and a second region of an opposite conductivity type separated therefrom, and then forming a floating gate electrode on the tunneling insulating film. It is characterized by:

Function: In the manufacturing method of the present invention, a thin tunneling insulating film is formed on the semiconductor substrate surface with a low impurity concentration before forming a diffusion layer with a high impurity concentration that becomes a tunneling implantation region. Thickness can be controlled more easily. After this, a diffusion layer with a high impurity concentration is formed, so a thin tunneling insulating film can be stably formed even on a high concentration diffusion layer, making it possible to improve write/erase characteristics. .

Example Specific embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A and 1F are cross-sectional views showing an embodiment of the present invention in the order of steps.

First, as shown in FIG. 1A, a silicon oxide film 2 is formed on the entire surface of a P-type silicon substrate 1 to a thickness of about 500 nm, and a silicon nitride film 3 is further formed to a thickness of about 100 nm. Then, a well-known photoetching process is performed on a predetermined portion where an element isolation region is to be formed, thereby removing the silicon oxide film and silicon nitride film in this portion.

Next, as shown in FIG. 1B, a conventional thermal oxidation process is performed to selectively oxidize the exposed portion of the P-type silicon substrate to form a field oxide film 4 having a thickness of about 1 μm.

Next, the silicon nitride film 3 and the underlying silicon oxide film 2 are sequentially etched and removed, and then thermal oxidation treatment is performed again to form a silicon oxide film 6 on the main surface of the P-type silicon substrate 1.
By selectively etching and removing a predetermined portion of the silicon oxide film 6, and forming a thin silicon oxide film 6 that will serve as a tunneling insulating film in this portion, the silicon oxide film 6 is formed to have a thickness of 0.00 mm. The structure shown is obtained. In this example, a thin silicon oxide film 6 is formed by dry oxidation at a temperature of eoo°C under argon dilution, and the film thickness is 1
00 people.

Next, as shown in the first diagram, using the photoresist 7 as a mask, phosphorus ions 8 are implanted into the N-type diffusion layer 9.
, 1o. In this embodiment, the silicon oxide film 6,
and an acceleration voltage of 100 KeV so that phosphorus ions are also implanted into the semiconductor substrate below the silicon oxide film 6.
The implantation was carried out under -2 implantation conditions with a dose of 2.times.10.sup.-15. After this treatment, the photoresist is removed.

Next, as shown in FIG. 1E, a phosphorus-doped polysilicon film is formed on the silicon oxide film 6 and the thin silicon oxide film 6 to a thickness of about 5000 nm by vapor phase epitaxy. A floating gate electrode 11 made of a polysilicon film is formed by photoetching.
form. Next, a silicon oxide film 12 is formed on the floating gate electrode to a thickness of approximately 700 nm by a normal thermal oxidation process. Thereafter, a polysilicon film doped with phosphorus is formed to a thickness of about 4,000 wafers by vapor phase growth, and a control electrode 13 made of the polysilicon film is formed by photo-etching.
form.

Next, as shown in FIG.
．． 10 in an N2 atmosphere to densify the silicon oxide film 14.

Perform heat treatment at a temperature of ℃. Finally, the silicon oxide film 14
A contact hole is formed in this portion, and an aluminum electrode 15 is formed in this portion. Through the above steps, a floating gate type semiconductor memory device manufactured by the manufacturing method of the present invention is completed.

In this example, as a method for forming a diffusion layer that will become a tunneling implantation region, a method is shown in which impurity ions are implanted from above a silicon oxide film using a photoresist as a mask immediately after forming a tunneling insulating film. As shown in FIG. 2A, after forming a floating gate electrode 11 made of a polysilicon film, phosphorous ions 8 are implanted in a self-aligned manner using the floating gate electrode 11 and field oxide film 4 as masks, and then, as shown in FIG. B
As shown in FIG.
It is also possible to use a method in which heat treatment is performed so that the diffusion in the lateral direction progresses until it is located at the bottom of the .

As is clear from the detailed description of the invention, according to the manufacturing method of the present invention, the diffusion layer is formed after the formation of a thin silicon oxide film that can serve as a tunneling medium. It becomes possible to control the impurity concentration freely and with high precision. Therefore,
It becomes possible to stably form a very thin silicon oxide film whose film thickness is controlled with high precision on a diffusion layer with a high impurity concentration, and it becomes easy to increase tunneling injection efficiency. This brings about an effect that greatly contributes to improving the write/erase characteristics of the 70-gate type semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a step-by-step sectional view for explaining one embodiment of the manufacturing method of the present invention, and FIG. 2 is a step-by-step sectional view for explaining another embodiment of the present invention. 1...P-type silicon substrate, 2, 5, 12.14
...Silicon oxide film, 3...Silicon nitride film, 4...Field oxide film, 6...
・・Thin silicon oxide film (tunneling insulating film), 7・
...Photoresist, 8...Phosphorus ion, 9,1o...N-type diffusion layer, 11...
Floating gate electrode, 13... control electrode, 16... aluminum electrode. . Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure ql, sl. /-F Hard silicon basic woman 2 7- Photoresist z, /2. t+-Mllified silicon (5-"son ion 3- fluorinated silicon'!l 9,1θ・
・-N split fox double counterfeit 4゛-field four doubts a U
---70-Chinging gate lt tree i5-゛Thick i! 2
(t:, silicon film 13-“-control electricity
6--Thin resistant silicone 15--Aluminum base material i. Figure 1/-P next silicon layer 4-11 field oxide film, 5-X silicon oxide film 6°-thin silicon oxide film 9, tθ-N type 4th layer. , J //---701 Teing Gate Sakiishi Gate Number + Number ◆
◆V 65 lθ

Claims (1)

[Claims] After forming an insulating film to serve as a tunneling medium in a predetermined area on the surface of a semiconductor substrate of one conductivity type, a first region of an opposite conductivity type is formed from the same first region in a positional relationship in which a portion of the insulating film is located under the same insulating film. 1. A method of manufacturing a semiconductor memory device, comprising the steps of forming second regions of opposite conductivity type in a spaced-apart relationship, and further forming a floating gate electrode on the insulator.