JPH01117365A - Manufacture of semiconductor memory device - Google Patents
Manufacture of semiconductor memory deviceInfo
- Publication number
- JPH01117365A JPH01117365A JP27621287A JP27621287A JPH01117365A JP H01117365 A JPH01117365 A JP H01117365A JP 27621287 A JP27621287 A JP 27621287A JP 27621287 A JP27621287 A JP 27621287A JP H01117365 A JPH01117365 A JP H01117365A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon oxide
- film
- insulating film
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 230000005641 tunneling Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000012212 insulator Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 30
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 30
- 238000009792 diffusion process Methods 0.000 abstract description 20
- 238000000034 method Methods 0.000 abstract description 12
- 239000012535 impurity Substances 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- -1 phosphorus ions Chemical class 0.000 abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 238000007740 vapor deposition Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 18
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Formation Of Insulating Films (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、フローティングゲート型の電界効果トランジ
スタからなる半導体記憶装置の書き込み消去特性の向上
をはかることができる製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a manufacturing method capable of improving the write/erase characteristics of a semiconductor memory device comprising a floating gate field effect transistor.
従来の技術
従来、電気的書き込み消去が可能なＲＯＭ（ＥＥＰＲＯ
Ｍ；Ｅｌｅｃｔｒｉｃａｌｌｙ Ｅｒａｓａｂｌｅ ａ
ｎｄＰｒｏｇｒａｍａｂｌｅ ＲＯＭ）の１つとして、
トンネリング注入により書き込み消去を行うフローティ
ングゲート構造の半導体記憶装置がよく知られている。Conventional technology Conventionally, electrically programmable and erasable ROM (EEPRO)
M；Electrically Erasable a
As one of the ndProgrammable ROM),
2. Description of the Related Art A semiconductor memory device having a floating gate structure in which writing and erasing is performed by tunneling injection is well known.
このフローティングゲート型の半導体記憶装置は、拡散
層上に形成した薄い絶縁膜を介して電荷のトンネリング
を行い、絶縁膜上にさらに形成したフローティングゲー
ト電極に電荷を蓄積させ、トランジスタのしきい値電圧
を変化させて情報を記憶させるものである。This floating gate type semiconductor memory device tunnels charges through a thin insulating film formed on a diffusion layer, accumulates charges in a floating gate electrode further formed on the insulating film, and raises the threshold voltage of the transistor. It is used to store information by changing the
このようなフローティングゲート型の半導体記憶装置を
製造するにあたシ、従来は、半導体基板の表面層に基板
とは反対導電型の拡散層を形成した後、前記の拡散層上
を酸化することによってトンネリング媒体となりうる薄
い（１００人程０）酸化シリコン膜（以下トンネリング
絶縁膜と記す）を形成し、さらにこの上にフローティン
グゲート電極を形成する方法が採用されていた。また、
拡散層上に形成する１００人程０）薄いトンネリング絶
縁膜を制御よく、しかも、安定に形成するために、拡散
層の不純物濃度を比較的低い濃度（１０１７〜１ｏ１８
ｃＩＲ−３程度）に抑えていた。To manufacture such a floating gate type semiconductor memory device, conventionally, a diffusion layer of a conductivity type opposite to that of the substrate is formed on the surface layer of a semiconductor substrate, and then the above diffusion layer is oxidized. A method of forming a thin silicon oxide film (hereinafter referred to as a tunneling insulating film) (hereinafter referred to as a tunneling insulating film) that can be used as a tunneling medium, and then forming a floating gate electrode on this film has been adopted. Also,
In order to form a thin tunneling insulating film on the diffusion layer with good control and stability, the impurity concentration of the diffusion layer is set to a relatively low concentration (1017 to 1018).
cIR-3).
発明が解決しようとする問題点
近年、半導体集積回路の高機能化、高性能化に伴い、Ｅ
ＥＦＲＯＭにおいても、書き込み消去スピードの向上の
要求が高まりつつあり、これを実現するにはトンネリン
グ絶縁膜下の拡散層の不純物濃度を１０〜１０ α 程
度の高い濃度としてトンネリング注入効率を高める方法
が考えられる。Problems to be Solved by the Invention In recent years, with the increasing functionality and performance of semiconductor integrated circuits,
In EFROM as well, there is a growing demand for improved write/erase speed, and one way to achieve this is to increase the tunneling injection efficiency by increasing the impurity concentration in the diffusion layer under the tunneling insulating film to a high concentration of about 10 to 10 α. It will be done.
しかしながら、トンネリング絶縁膜下の拡散層の不純物
濃度を高くすると、トンネリング絶縁膜を形成する酸化
工程で増殖酸化が起こり、膜厚を制御性よく、しかも、
安定して形成することが困難となる。さらに、膜質が劣
化する問題も発生する。However, when the impurity concentration of the diffusion layer under the tunneling insulating film is increased, propagated oxidation occurs in the oxidation process to form the tunneling insulating film, and the film thickness can be controlled with good control.
It becomes difficult to form it stably. Furthermore, the problem of deterioration of film quality also occurs.
本発明の目的は、不純物濃度の高い拡散層上に薄いトン
ネリング絶縁膜を制御性よく、しかも、安定に形成する
ことができる製造方法を提供することにある。An object of the present invention is to provide a manufacturing method that can stably form a thin tunneling insulating film on a diffusion layer with high impurity concentration with good controllability.
問題点を解決するだめの手段
上記の目的を達成することができる本発明の製造方法は
一導電型半導体基板表面の所定域にトンネリング媒体と
なる絶縁膜を形成したのち、同絶縁膜下に一部が位置す
る関係を成立せた反対導電凰の第１領域およびこれから
離間する反対導型の第２領域を形成し、こののち、前記
トンネリング絶縁膜上にフローティングゲート電極を形
成する工程を少なくとも備えたことを特徴とするもので
ある。Means for Solving the Problems The manufacturing method of the present invention, which can achieve the above objects, involves forming an insulating film to serve as a tunneling medium in a predetermined area on the surface of a semiconductor substrate of one conductivity type, and then forming a film under the insulating film. forming a first region of an opposite conductivity type and a second region of an opposite conductivity type separated therefrom, and then forming a floating gate electrode on the tunneling insulating film. It is characterized by:
作 用
本発明の製造方法では、トンネリング注入領域となる高
い不純物濃度の拡散層を形成する以前、すなわち、不純
物濃度の低い半導体基板面に薄いトンネリング絶縁膜が
形成されるため、トンネリング絶縁膜の膜厚の制御性が
高くなる。こののち、高不純物濃度の拡散層が形成され
るため、高濃度の拡散上であっても薄いトンネリング絶
縁膜を安定して形成することができ、書き込み消去特性
の向上をはかることが可能となる。Function: In the manufacturing method of the present invention, a thin tunneling insulating film is formed on the semiconductor substrate surface with a low impurity concentration before forming a diffusion layer with a high impurity concentration that becomes a tunneling implantation region. Thickness can be controlled more easily. After this, a diffusion layer with a high impurity concentration is formed, so a thin tunneling insulating film can be stably formed even on a high concentration diffusion layer, making it possible to improve write/erase characteristics. .
実施例 本発明の具体的な実施例を図面を用いて説明する。Example Specific embodiments of the present invention will be described with reference to the drawings.
第１図Ａ、Ｆは、本発明の一実施例を示した工程順断面
図である。FIGS. 1A and 1F are cross-sectional views showing an embodiment of the present invention in the order of steps.
まず、第１図Ａに示すように、Ｐ型シリコン基板１の全
面に、酸化シリコン膜２を５００人の厚さに形成し、さ
らに窒化シリコン膜３を１ｏＯＯ人程度の厚さに形成し
た後、素子分離領域を形成すべき所定の部分に周知のフ
ォトエツチング処理を施すことによってこの部分の酸化
シリコン膜と窒化シリコン膜を除去する。First, as shown in FIG. 1A, a silicon oxide film 2 is formed on the entire surface of a P-type silicon substrate 1 to a thickness of about 500 nm, and a silicon nitride film 3 is further formed to a thickness of about 100 nm. Then, a well-known photoetching process is performed on a predetermined portion where an element isolation region is to be formed, thereby removing the silicon oxide film and silicon nitride film in this portion.
次いで、第１図Ｂに示すように、通常の熱酸化処理を施
すことによって、露出するＰ型シリコン基板部分を選択
的に酸化して厚さが１μｍ程度のフィールド酸化膜４を
形成する。Next, as shown in FIG. 1B, a conventional thermal oxidation process is performed to selectively oxidize the exposed portion of the P-type silicon substrate to form a field oxide film 4 having a thickness of about 1 μm.
次に、窒化シリコン膜３とこの下の酸化シリコン膜２を
順次エツチングして取り除いた後、再度熱酸化処理を施
してＰ型シリコン基板１の主面に酸化シリコン膜６を５
００人の厚さに形成し、さらに、酸化シリコン膜６の所
定の部分を選択的にエツチングして取り除き、この部分
にトンネリング絶縁膜となる薄い酸化シリコン膜６を形
成することによって第１図Ｃで示す構造が得られる。本
実施例では、薄い酸化シリコン膜６を温度ｅｏｏ℃、ア
ルゴン希釈下のドライ酸化により形成し、その膜厚を１
００人とした。Next, the silicon nitride film 3 and the underlying silicon oxide film 2 are sequentially etched and removed, and then thermal oxidation treatment is performed again to form a silicon oxide film 6 on the main surface of the P-type silicon substrate 1.
By selectively etching and removing a predetermined portion of the silicon oxide film 6, and forming a thin silicon oxide film 6 that will serve as a tunneling insulating film in this portion, the silicon oxide film 6 is formed to have a thickness of 0.00 mm. The structure shown is obtained. In this example, a thin silicon oxide film 6 is formed by dry oxidation at a temperature of eoo°C under argon dilution, and the film thickness is 1
00 people.
次に、第１図りに示すように、フォトレジスト７をマス
クとして用いて、リンイオン８を注入し、Ｎ型拡散層９
，１ｏを形成する。本実施例では、酸化シリコン膜６、
および酸化シリコン膜６の下の半導体基板内にもリンイ
オンが注入されるように、加速電圧１００ＫｅＶ 、
ドーズ量２Ｘ１０−１５の−２の注入条件のもとで実
施した。この処理ののち、フォトレジストアを除去する
。Next, as shown in the first diagram, using the photoresist 7 as a mask, phosphorus ions 8 are implanted into the N-type diffusion layer 9.
, 1o. In this embodiment, the silicon oxide film 6,
and an acceleration voltage of 100 KeV so that phosphorus ions are also implanted into the semiconductor substrate below the silicon oxide film 6.
The implantation was carried out under -2 implantation conditions with a dose of 2.times.10.sup.-15. After this treatment, the photoresist is removed.
次に、第１図Ｅに示すように酸化シリコン膜６および薄
い酸化シリコン膜６の上に、リンをドープしたポリシリ
コン膜を気相成長法により約５０００人の厚さに形成し
、その後周知のフォトエツチング処理を施すことにより
ポリシリコン膜よりなるフローティングゲート電極１１
を形成する。次いで、通常の熱酸化処理により、酸化シ
リコン膜１２をフローティングゲート電極上で厚さが約
７００人となるように形成する。その後、リンをドープ
したポリシリコン膜を気相成長法により約４０００人の
厚さに形成し、さらに、フォトエツチング処理を施すこ
とによりポリシリコン膜よりなるコントロール電極１３
を形成する。Next, as shown in FIG. 1E, a phosphorus-doped polysilicon film is formed on the silicon oxide film 6 and the thin silicon oxide film 6 to a thickness of about 5000 nm by vapor phase epitaxy. A floating gate electrode 11 made of a polysilicon film is formed by photoetching.
form. Next, a silicon oxide film 12 is formed on the floating gate electrode to a thickness of approximately 700 nm by a normal thermal oxidation process. Thereafter, a polysilicon film doped with phosphorus is formed to a thickness of about 4,000 wafers by vapor phase growth, and a control electrode 13 made of the polysilicon film is formed by photo-etching.
form.
次いで、第１図Ｆに示すように、気相成長法により、酸
化シリコン膜１４を全面に被着したのち、Ｎ型拡散層９
．１０の押し込みと、酸化シリコン膜１４の緻密化のた
めに、Ｎ２雰囲気中で１ｏｏ。Next, as shown in FIG.
．． 10 in an N2 atmosphere to densify the silicon oxide film 14.
℃の温度の熱処理を行う。最後に、酸化シリコン膜１４
にコンタクト孔を形成し、この部分にアルミニウム電極
１５を形成する。以上の過程を経ることによって、本発
明の製造方法によるフローティングゲート型の半導体記
憶装置が完成する。Perform heat treatment at a temperature of ℃. Finally, the silicon oxide film 14
A contact hole is formed in this portion, and an aluminum electrode 15 is formed in this portion. Through the above steps, a floating gate type semiconductor memory device manufactured by the manufacturing method of the present invention is completed.
本実施例では、トンネリング注入領域となる拡散層の形
成法として、トンネリング絶縁膜を形成した直後に、酸
化シリコン膜の上から、フォトレジストをマスクとして
不純物イオンを注入する方法を示したが、たとえば、第
２図Ａに示すように、ポリシリコン膜よりなるフローテ
ィングゲート電極１１を形成した後に、フローティング
ゲート電極１１とフィールド酸化膜４をマスクとしてリ
ンイオン８を自己整合的に打ち込み、その後、第２図Ｂ
に示すように、Ｎ型拡散層９が、薄い酸化シリコン膜６
の下部に位置するまで横方向への拡散が進行するように
熱処理を施す方法を用いることもできる。In this example, as a method for forming a diffusion layer that will become a tunneling implantation region, a method is shown in which impurity ions are implanted from above a silicon oxide film using a photoresist as a mask immediately after forming a tunneling insulating film. As shown in FIG. 2A, after forming a floating gate electrode 11 made of a polysilicon film, phosphorous ions 8 are implanted in a self-aligned manner using the floating gate electrode 11 and field oxide film 4 as masks, and then, as shown in FIG. B
As shown in FIG.
It is also possible to use a method in which heat treatment is performed so that the diffusion in the lateral direction progresses until it is located at the bottom of the .
発明の詳細
な説明したところから明らかなように、本発明の製造方
法によれば、トンネリング媒体となりうる薄い酸化シリ
コン膜の形成後に拡散層が形成されるため、トンネリン
グ絶縁膜の膜厚および拡散層の不純物濃度を自由に、し
かも、高い精度で制御することが可能となる。従って、
高不純物濃度の拡散層の上に、膜厚が高い精度で制御さ
れた非常に薄い酸化シリコン膜を安定に形成することが
可能となり、トンネリング注入効率を高めることが容易
になる。このことによって７０−ティングゲート型の半
導体記憶装置の書き込み消去特性の向上に大きく寄与す
る効果が奏される。As is clear from the detailed description of the invention, according to the manufacturing method of the present invention, the diffusion layer is formed after the formation of a thin silicon oxide film that can serve as a tunneling medium. It becomes possible to control the impurity concentration freely and with high precision. Therefore,
It becomes possible to stably form a very thin silicon oxide film whose film thickness is controlled with high precision on a diffusion layer with a high impurity concentration, and it becomes easy to increase tunneling injection efficiency. This brings about an effect that greatly contributes to improving the write/erase characteristics of the 70-gate type semiconductor memory device.
第１図は本発明の製造方法の一実施例を説明するための
工程順断面図、第２図は本発明の別の実施例を説明する
ための工程順断面図である。
１・・・・・・Ｐ型シリコン基板、２，５，１２．１４
・・・・・・酸化シリコン膜、３・・・・・・窒化シリ
コン膜、４・・・・・・フィールド酸化膜、６・・・・
・・薄い酸化シリコン朕（トンネリング絶縁膜）、７・
・・・・・フォトレジスト、８・・・・・・リンイオン
、９，１ｏ・・・・・・Ｎ型拡散層、１１・・・・・・
フローティングゲート電極、１３・・・・・・コントロ
ール電極、１６・・・・・・アルミニウム電極。。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
ｑｌ、ｓｌ。
／−Ｆ 堅シリコン基本女２ ７− フォトレジスト
ｚ、 ／２． ｔ＋−Ｍｌｌ化シリボン （５−”ソ
ンイオン３− 菫化シリコン’！ｌ ９，１θ・
・−Ｎ裂狐双贋４゛−フィールド四疑イヒａ Ｕ
−−−７０−チイングゲートｌｔ木ｉ５−゛厚いｉ！２
（ｔ：、シリコン膜 １３−“−コントロール電湘ｉ
６−・薄い耐ピしシリコン秩 １５−−−アルミニウ
ム宅才ｉ。
第１図
／−Ｐ翌シリコン」艮零更
４−一一フイールド酸イヒ膜
、５−Ｘい酸化シリコン膜
６°−薄い酸化シリコン膜
９、 ｔθ−Ｎ型４ム裟層
第 。、Ｊ ／／−−−７０一テイ
ングゲート叱石ｉ門 番 ＋ 番 ◆
◆Ｖ ６５ ｌθFIG. 1 is a step-by-step sectional view for explaining one embodiment of the manufacturing method of the present invention, and FIG. 2 is a step-by-step sectional view for explaining another embodiment of the present invention. 1...P-type silicon substrate, 2, 5, 12.14
...Silicon oxide film, 3...Silicon nitride film, 4...Field oxide film, 6...
・・Thin silicon oxide film (tunneling insulating film), 7・
...Photoresist, 8...Phosphorus ion, 9,1o...N-type diffusion layer, 11...
Floating gate electrode, 13... control electrode, 16... aluminum electrode. . Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure ql, sl. /-F Hard silicon basic woman 2 7- Photoresist z, /2. t+-Mllified silicon (5-"son ion 3- fluorinated silicon'!l 9,1θ・
・-N split fox double counterfeit 4゛-field four doubts a U
---70-Chinging gate lt tree i5-゛Thick i! 2
(t:, silicon film 13-“-control electricity
6--Thin resistant silicone 15--Aluminum base material i. Figure 1/-P next silicon layer 4-11 field oxide film, 5-X silicon oxide film 6°-thin silicon oxide film 9, tθ-N type 4th layer. , J //---701 Teing Gate Sakiishi Gate Number + Number ◆
◆V 65 lθ
Claims (1)
媒体となる絶縁膜を形成したのち、同絶縁膜下に一部が
位置する位置関係で反対導電型の第１領域を、同第１領
域から離間する位置関係で反対導電型の第２領域を作り
込み、さらに、前記絶縁物上にフローティングゲート電
極を形成する工程を備えることを特徴とする半導体記憶
装置の製造方法。After forming an insulating film to serve as a tunneling medium in a predetermined area on the surface of a semiconductor substrate of one conductivity type, a first region of an opposite conductivity type is formed from the same first region in a positional relationship in which a portion of the insulating film is located under the same insulating film. 1. A method of manufacturing a semiconductor memory device, comprising the steps of forming second regions of opposite conductivity type in a spaced-apart relationship, and further forming a floating gate electrode on the insulator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62276212A JP2672530B2 (en) | 1987-10-30 | 1987-10-30 | Method for manufacturing semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62276212A JP2672530B2 (en) | 1987-10-30 | 1987-10-30 | Method for manufacturing semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01117365A true JPH01117365A (en) | 1989-05-10 |
| JP2672530B2 JP2672530B2 (en) | 1997-11-05 |
Family
ID=17566243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62276212A Expired - Lifetime JP2672530B2 (en) | 1987-10-30 | 1987-10-30 | Method for manufacturing semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2672530B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0511370A1 (en) * | 1990-11-21 | 1992-11-04 | Atmel Corporation | Method of making an MOS EEPROM floating gate transistor cell |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61182267A (en) * | 1985-02-08 | 1986-08-14 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS61294870A (en) * | 1985-06-21 | 1986-12-25 | Nec Corp | Non-volatile semiconductor memory device |
-
1987
- 1987-10-30 JP JP62276212A patent/JP2672530B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61182267A (en) * | 1985-02-08 | 1986-08-14 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS61294870A (en) * | 1985-06-21 | 1986-12-25 | Nec Corp | Non-volatile semiconductor memory device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0511370A1 (en) * | 1990-11-21 | 1992-11-04 | Atmel Corporation | Method of making an MOS EEPROM floating gate transistor cell |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2672530B2 (en) | 1997-11-05 |
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