JPH0565063B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a buried gate field effect transistor (hereinafter referred to as FET), which is employed, for example, in a silicon thin film transistor.

[Conventional technology]

A buried gate FET uses a resistive semiconductor region buried in a high-resistance semiconductor substrate as a gate, and has a channel region and source/drain regions of a thin semiconductor film formed on the substrate with an insulating film interposed therebetween. Figures 2a to 2c show the conventional manufacturing method,
First, as shown in Figure a, an oxide film 2 was formed on a silicon substrate 1, a resist 31 with selective openings only at the gate was formed by photolithography, and the oxide film 2 was partially removed by etching. After that, for example, when forming an n-type gate electrode,
Impurity diffusion is performed by implanting phosphorus ions 4. A conventional gas diffusion method using PoCl ₃ may be used instead of ion implantation. Next, as shown in FIG. 2b, the gate oxide film 5 is formed by reoxidation, and at the same time, the buried gate electrode portion is heated to form a gate oxide film 5.
A mold diffusion layer 6 is formed. Thereafter, a polycrystalline silicon layer 7, which will become the channel region and source/drain region of the FET, is deposited by CVD method, and a resist 32 with openings only in the source/drain region is deposited thereon.
After forming the pattern, phosphorus ions 4 are implanted again. Thereafter, source/drain regions 8 are formed in the polycrystalline silicon by annealing, as shown in FIG. 2c, and a channel region 9 remains between them.

[Problem that the invention seeks to solve]

In such steps in the conventional manufacturing method, the alignment between the buried gate electrode 6 and the source/drain region 8 depends on the mask alignment accuracy of the photolithography technique. Since the precision of mask aligners normally used for manufacturing elements such as thin film transistors is at the level of ±1 to 1.5 μm, conventional methods that require consideration of this alignment margin have had limits on microfabrication of transistors.

An object of the present invention is to address the above-mentioned problems and improve the alignment accuracy of the gate electrode with the source/drain region, thereby making the buried gate type more suitable for miniaturization than the conventional one.
The purpose of the present invention is to provide a method for manufacturing FETs.

[Means for solving problems]

In order to achieve the above object, the method of the present invention forms an insulating film on a semiconductor substrate, and then forms two source/drain regions made of a semiconductor layer with a high impurity concentration on the insulating film, separated from each other. Next, using this source/drain region as a mask, impurities are introduced into the semiconductor substrate to form a buried gate electrode.
Furthermore, a channel region made of a semiconductor layer with a low impurity concentration is formed between the source and drain regions.

[Effect]

In the above method, the buried gate electrode is formed in self-alignment by introducing impurities using the already formed source/drain regions as a mask, so there is no need to consider alignment margins, and pattern miniaturization is possible. It becomes possible.

〔Example〕

An embodiment of the present invention is shown in FIGS.
Parts common to those in the figure are given the same reference numerals.
First, the semiconductor substrate 1 is oxidized to form a gate oxide film 5.
(Figure a). Here, the material of the substrate 1 may be single crystal silicon or polycrystalline silicon often used in thin film transistors. Next, a polycrystalline silicon layer 7, which will become the source/drain region of the buried gate FET, is formed (FIG. b). This is deposited in the form of doped polycrystalline Si using a conventional low pressure CVD method. However, undoped polycrystalline Si
After deposition, impurities may be introduced by PoCl ₃ gas diffusion or ion implantation. A typical value is a sheet resistance value of 20 to 40 Ω/□ for the source/drain region. Next, as shown in FIG. 1c, the resist 33 that selectively covers the source/drain regions is patterned, and the polycrystalline Si layer 7 that is not covered is removed by dry etching. At this time, both source and drain regions 8 shown in FIG. 1d are formed, and the space between them serves as a window for forming a buried gate electrode, and is also a portion where a channel region is formed. Next, phosphorus ions 4 are implanted through the gate oxide film 5 by ion implantation.
A dose of about 5×10 ¹⁵ /cm ² is implanted at 150 keV into the buried gate region. At this time, the region away from the gate electrode is covered with a resist 34, but the pattern does not require alignment accuracy. in this way,
The first layer is self-aligned through the gate oxide film using the polycrystalline Si layer 8 forming the source/drain region as a mask.
To form the gate electrode 6 of the n ⁺ layer shown in Figure e,
Microfabrication can be achieved without being affected by mask alignment accuracy. Finally, a low concentration polycrystalline Si layer 9, which will become a channel region, is formed by low pressure CVD.
This makes it possible to create a buried gate FET that uses a diffusion layer in the semiconductor substrate for the gate electrode, which is the opposite of a normal insulated gate FET, using self-alignment technology between the gate and source/drain regions.

Note that terminal electrodes or wiring for connecting the buried gate 7 and the source/drain region 8 with an external circuit or with elements formed in other regions of the semiconductor substrate 1 are formed in the buried gate or the source/drain region, respectively. They can be formed simultaneously and in the same manner.

〔Effect of the invention〕

According to the present invention, the gate electrode is not buried in the semiconductor substrate in advance, but after the source/drain region is formed, it is formed in self-alignment by introducing impurities as a mask, and there is no need for mask alignment. Since it is not affected by alignment accuracy, microfabrication is possible, which is effective for miniaturizing devices and increasing their density. Furthermore, since the gate overlap capacitance is reduced, it is possible to achieve higher speed buried gate type FETs.

[Brief explanation of the drawing]

1A to 1E are cross-sectional views sequentially showing the manufacturing process of an embodiment of the present invention, and FIGS. 2A to 2C are cross-sectional views sequentially showing the manufacturing process of a conventional method. 1: semiconductor substrate, 4: phosphorus ion, 5: gate oxide film, 6: gate electrode, 8: source/drain region.

Claims (1)

[Claims] 1. After forming an insulating film on a semiconductor substrate, two source/drain regions made of a semiconductor layer with a high impurity concentration are formed on the insulating film, separated from each other, and then, using the source/drain regions as a mask, the semiconductor substrate is coated. A method for manufacturing a buried gate field effect transistor, comprising the steps of: introducing an impurity to form a buried gate electrode; and further forming a channel region made of a semiconductor layer with a low impurity concentration between the source and drain regions.