JPH0760863B2 - Thin film mask ROM - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film mask ROM.

[0002]

2. Description of the Related Art Conventionally, a read-only mask ROM in which binary data is written at the manufacturing stage is formed by arranging a large number of MOS transistors arranged on a Si (silicon) substrate. The configured binary data of each bit (“0” or “1” data) is transferred to each MOS.
It is written by controlling the gate oxide film thickness of the transistor, controlling Vth by ion implantation, or presence or absence of contact.

[0003]

However, since the conventional mask ROM described above has MOS transistors formed on the Si substrate, not only many steps are required for its manufacture, but also it is difficult to increase its area. Had a problem.

The present invention has been made in view of the above situation, and an object thereof is a thin film mask which can be manufactured easily and can be manufactured at a low cost and can be made large in area. It is to provide ROM.

[0005]

Means for Solving the Problems The thin film mask RO of the present invention
M denotes a plurality of row address lines parallel to each other on the insulating substrate, and a plurality of column address lines and ground lines orthogonal to the row address lines and adjacent to each other, and an insulating film interposed therebetween. The rows and columns are arranged in an array, and the facing portions of the row address lines and the adjacent column address lines and ground lines are used as 1-bit write areas, and a predetermined write area of each write area is provided. Further, a semiconductor film facing the row address line via the insulating film and connected to the column address line and the ground line on both sides is formed.

[0006]

That is, in the thin-film mask ROM of the present invention, the facing portions of the row address line and the adjacent column address line and ground line are used as 1-bit write areas, and of these write areas. A semiconductor film is formed in a predetermined write region, and in this write region, the row address line is used as a gate electrode, the column address line and the ground line are used as source and drain electrodes, and the semiconductor film is used as a channel region. The thin film transistor is configured, and the write data (binary data of “0” or “1”) of each write area is
It is distinguished by the presence or absence of a thin film transistor.

This thin film mask ROM can be manufactured by forming row address lines, insulating films, column address lines and ground lines, and a semiconductor film on an insulating substrate, so that the manufacturing is simple. Thus, the cost can be reduced and the area can be increased, and the write data in each write region can be arbitrarily selected by changing the formation pattern of the semiconductor film.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the thin film mask ROM of the present invention will be described below.

First, the circuit of the thin film mask ROM shown in FIG. 5 will be described. This thin film mask ROM circuit is similar to the conventional mask ROM in that the row decoder section 1 is used.
, Column decoder section 2, memory matrix section 3, and column switch section 4, and these sections are formed on the same insulating substrate.

The specific structure of the thin film mask ROM will be described. FIGS. 1 to 3 show a part of the memory matrix portion 3 of the thin film mask ROM, in which 10 is an insulating substrate. A large number of row address lines 11 and 11 are arranged in parallel with each other on the upper surface of the substrate 10, and each row address line is formed on the surface of the substrate 10.
An insulating film 12, such as SiN, covering 11 and 11 is formed over the entire surface of the substrate.

A large number of column address lines 13, 13 and ground lines 14, 14 are formed on the insulating film 12 so as to be orthogonal to the row address lines 11, 11. The column address lines 13 and the ground lines 14 are alternately arranged so as to be adjacent to each other.

The row address line 11 and
Adjacent column address line 13 and ground line 14
The portions facing with are the writing area A for 1 bit,
A predetermined write area A of each write area is opposed to the row address line 11 via the insulating film 12 and has the column address line 13 and the ground line on both sides. A-S connected to 14
An i (amorphous-silicon) semiconductor film 15 is formed.

The semiconductor film 15 is formed on the insulating film 12,
The column address line 13 and the ground line 14 are formed to have substantially the same width as the row address line 11 and a length substantially equal to the distance between the outer edges of the adjacent column address line 13 and the ground line 14. Ohmic connections are made to the upper surfaces of both sides of the semiconductor film 15.

That is, in this thin film mask ROM, the facing portions of the row address line 11 and the adjacent column address line 13 and ground line 14 are set as 1-bit write areas A and A, respectively. A semiconductor film 15 is formed in a predetermined writing area A of the writing area,
In the write area A, the row address line 11 is used as a gate electrode, one of the column address line 13 and the ground line 14 is used as a source electrode, and the other is used as a drain electrode, and the column address of the semiconductor film 15 is used. An inverted staggered thin film transistor T having a channel region between the line 13 and the ground line 14 is formed, and write data (binary data of “0” or “1”) in each write region A, A is a thin film transistor. It is distinguished by the presence or absence of T. FIG. 4 shows a method of manufacturing the above-mentioned thin film mask ROM in the order of steps.
Is manufactured as follows.

First, as shown in FIG. 4A, the insulating substrate 10
After forming a large number of row address lines 11 on the upper surface of the substrate, an insulating film 12 is formed on the entire surface of the substrate, and an a-Si semiconductor film 15 is formed on the entire surface of the insulating film 11.

Next, a photoresist is applied on the semiconductor film 15 and is exposed and developed to form a resist mask 16 having a pattern corresponding to a writing region for forming a thin film transistor, as shown in FIG. Formed as
In this state, the semiconductor film 15 is etched to leave the semiconductor film 15 only in the portion corresponding to the writing region where the thin film transistor is formed and remove the resist mask 16 as shown in FIG. 4B.

Thereafter, as shown in FIG. 4C, a conductive metal film 17 is formed on the patterned semiconductor film 15 over substantially the entire surface of the insulating film 12, and the conductive metal film 17 is formed on the metal film 17. By applying a photoresist and subjecting it to exposure and development, a resist mask 18 corresponding to the pattern of the column address line and the ground line is formed, and in this state, the metal film 17 is etched, as shown in FIG. Column address lines 13 and 13 and ground lines 14 and 14
And the resist mask 18 is peeled off after that, and a thin film mask ROM in which binary data is written in each writing area A, A depending on the presence or absence of the thin film transistor T is completed.

Although the memory matrix section 3 of the thin film mask ROM has been described here, the row decoder section 1, the column decoder section 2 and the column switch section 4 shown in FIG. The thin film mask ROM has the same structure as the matrix section 3
Is manufactured by forming the row decoder section 1, the column decoder section 2, the memory matrix section 3 and the column switch section 4 by the above manufacturing method.

Next, reading of write data from the thin film mask ROM will be described with reference to FIG. 5. Read of write data from the thin film mask ROM is performed by the row decoder of the memory matrix section 3 in the row decoder section 1. The address matrix 11 is selected, and the column switch unit 4 controlled by the column decoder unit 2 controls the memory matrix unit 3
The write data in the write area A of the memory matrix section 3 selected by selecting the row address line 11 and the column address line 13 is It is output from the OUT terminal of the column switch unit 4.

In this embodiment, a NOR type mask ROM is formed, and this memory matrix section 3 is formed.
When the writing area A in which the thin film transistor T is formed is selected, the writing area A has the transistor T,
Since this transistor T is connected to the ground line 14, the OUT terminal output becomes the ground level. Further, when the writing area A in which the thin film transistor T is not formed is selected, even if this writing area A is selected, since the writing area A does not have the transistor T, the OUT terminal output is pulled up, for example. It will be a raised high level.

In the thin film mask ROM, however, the facing portions of the row address line 11 and the adjacent column address line 13 and the ground line 14 are set as 1-bit write areas A and A, respectively, and A semiconductor film 15 is formed in a predetermined write area A of each write area, and the row address line 11 is used as a gate electrode in the write area A, the column address line 13 and the ground line 14 are sources, By forming a thin film transistor T having a drain electrode and a semiconductor film 15 as a channel region, write data in each write region A is distinguished by the presence or absence of the thin film transistor T. As in the manufacturing method described above, the row address line 11, the insulating film 12, and the column are formed on the insulating substrate 11. It can be manufactured by forming the address line 13, the ground line 14, and the semiconductor film 15.

Therefore, this thin film mask ROM is simple to manufacture and can be manufactured at low cost. Further, since the write areas A and A are formed on the substrate 10, the area can be increased. Is. Moreover, according to the thin film mask ROM, the write data of the write areas A, A can be arbitrarily selected only by changing the formation pattern when the semiconductor film 15 is formed. It can be manufactured in a manufacturing facility.

In the above embodiment, the column address lines 13 and the ground lines 14 are alternately arranged so that the column address lines 13 and the ground lines 14 correspond one to one. Is not limited to the above-mentioned configuration, and column address lines and ground lines are arranged in the order of column, ground, column, column, ground, column, column, ground, column ... column, ground, column, A write area may be formed at a portion where the row address line and the ground line and the column address line face each other. In this case, since the thin film transistors formed in the adjacent write regions share one ground line as a source electrode or a drain electrode,
The number of ground lines is reduced, and the integration degree of the writing area is improved.

Further, in the above embodiment, the write areas A, A
Although the thin film transistor T formed in 1 has a reverse stagger structure, the thin film transistor T may have a stagger structure, and in this case also, the column address line 13 and the ground line 14 are formed on the insulating substrate 10 and the semiconductor film is formed thereon. 15 is formed, and then the row address lines 11 are formed on the thin film mask RO through the insulating film 12.
M can be manufactured easily.

[0025]

According to the thin film mask ROM of the present invention, the facing portions of the row address lines and the adjacent column address lines and ground lines are used as 1-bit write areas, and of these write areas. A semiconductor film is formed in a predetermined write area of the column, and the row address line is used as a gate electrode in the write area.
The write data (binary data of “0” or “1”) of each write area is transferred to the thin film transistor by forming the thin film transistor using the address line and the ground line as the source and drain electrodes and the semiconductor film as the channel region. The thin-film mask ROM is designed to be distinguished by its presence or absence on an insulating substrate.
Since it can be manufactured by forming address lines, insulating films, column / address lines and ground lines, and semiconductor films, the manufacturing is simple and low cost is possible, and the area can be increased. Moreover, the write data in each write area can be arbitrarily selected by changing the formation pattern of the semiconductor film.

[Brief description of drawings]

FIG. 1 is a plan view of a part of a memory matrix portion of a thin film mask ROM showing an embodiment of the present invention.

FIG. 2 is a sectional view taken along line II-II in FIG.

FIG. 3 is a sectional view taken along line III-III in FIG.

FIG. 4 is a manufacturing process diagram of a thin film mask ROM.

FIG. 5 is a circuit diagram of a thin film mask ROM.

[Explanation of symbols]

10 ... Insulating substrate, 11 ... Row address line, 12 ... Insulating film, 13 ... Column address line, 14 ... Ground line, 15
... semiconductor film, A ... writing region, T ... thin film transistor.

Claims (1)

[Claims] 1. A plurality of row address lines parallel to each other and a plurality of column address lines and ground lines orthogonal to the row address lines and adjacent to each other are insulated from each other on an insulating substrate. The films are arranged in an array, and the facing portions of the row address lines and the adjacent column address lines and ground lines are used as 1-bit write areas, and a predetermined area of each write area is set. A thin film mask ROM, characterized in that a semiconductor film facing the row address line via the insulating film and connected to the column address line and the ground line on both sides is formed in the write region.