JP2003060075A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device facilitating processes and a manufacturing method of the semiconductor device. SOLUTION: The manufacturing method of the semiconductor device provided with n-type and p-type gate electrodes is provided with a process of forming a first insulating film 12 on a semiconductor substrate 11; a process of forming a first electrode material to which impurities are not introduced on the first insulating film 12; a process of forming an element isolation region composed of an insulating film 15 for element isolation inside the first electrode material, the first insulating film 12, and the semiconductor substrate 11; a process of forming n-type first and second conductive layers 13b and 16b, and forming p-type first and second conductive layers 13c and 16c by performing ion implantation and heat treatment to the first electrode material; and a process of forming an n-type second electrode material on the second conductive layers 16b and 16c, and forming n-type third conductive layers 21b and 21c composed of the second conductive material.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a memory transistor having a floating gate and a control gate, and N-type and P-type peripheral transistors for controlling the memory transistor, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a dual gate function CMOS transistor has been used as a nonvolatile memory for low power consumption or a high-performance transistor that requires high-speed operation. This CMOS transistor has an NMOS
There are transistors and PMOS transistors. In the case of forming these transistors, first, an electrode material in which impurities are not implanted is deposited in advance. And NMO
In the gate region of the S transistor, As which is an N-type impurity
(Arsenic) or P (phosphorus) is implanted, and B (boron), which is a P-type impurity, is implanted into the gate region of the PMOS transistor. In this way, by using the exposure technique, the impurities are separately implanted into the N-type gate electrode and the P-type gate electrode, and the Dual Gate
The gate electrode of the Function structure was formed.

[0003]

However, in the formation of the gate electrode having the Dual Gate Function structure according to the above-mentioned conventional technique, there are problems that the process is complicated and the cost is increased.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of facilitating the process and a method of manufacturing the same.

[0005]

The present invention uses the following means in order to achieve the above object.

A semiconductor device according to a first aspect of the present invention is
A semiconductor device having a gate electrode of a first conductivity type, comprising:
The gate electrode is formed on the semiconductor substrate.
It is composed of a first conductive type conductive layer and a second conductive type second conductive layer formed on the first conductive layer.

A semiconductor device manufacturing method according to a second aspect of the present invention is a method of manufacturing a semiconductor device having a first conductive type gate electrode composed of first and second conductive layers, which is provided on a semiconductor substrate. A step of forming a first insulating film on the
A step of forming a first electrode material on which an impurity is not introduced on the insulating film, and an element isolation region including the element isolation insulating film in the first electrode material, the first insulating film and the semiconductor substrate. Forming step, forming the first conductive layer of the first conductivity type by performing ion implantation and heat treatment on the first electrode material, the first conductive layer and the element Forming a second electrode material of the second conductivity type on the isolation insulating film and forming the second conductive layer made of the second conductive material.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. When explaining this,
Common parts are designated by common reference numerals.

[First Embodiment] In the first embodiment, P
Made of an N-type first conductive layer and an N-type second conductive layer
This is an example of using an electrode material in which impurities are not implanted into the first conductive layer when forming the OS transistor.

1 and 2 are sectional views of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a cross-sectional view of the memory cell region perpendicular to the element isolation region.
Shows a cross-sectional view perpendicular to the gate electrode in the memory cell region.

As shown in FIG. 1, according to the first embodiment.
The semiconductor device has a memory cell region, an NMOS region, and a P region.
And a peripheral circuit region including a MOS region. PMOS
The PMOS transistor 25 in the region is on the semiconductor substrate 11.
Formed on P⁺Type first and second conductive layers 13c, 1
6c and the opening 20 formed on the second conductive layer 16c.
An insulating film 19 having a film, the insulating film 19 and the second conductive layer 1
N formed on 6c ⁺From the third conductive layer 21c of the mold
Become. The NMOS transistor 24 in the NMOS region is a half
N formed on the conductor substrate 11⁺First and second leads of the mold
Formed on the conductive layers 13b and 16b and the second conductive layer 16b.
An insulating film 19 having an opening 20, and the insulating film 19 and
N formed on the second conductive layer 16b⁺Mold third conductivity
And a layer 21b. Memory transition of memory cell area
The star 23 is an N formed on the semiconductor substrate 11.⁺Type number
1 and 2nd conductive layer 13a, 16a, and 2nd conductive layer 1
6a formed on the insulating film 19 and the insulating film 19 formed on the insulating film 19
N done⁺Mold third conductive layer 21a.

In the peripheral circuit area, the insulating film 19 is formed.
Are the second conductive layers 16b and 16c and the third conductive layer 21.
It only has to exist at the end between b and 21c. Therefore, the opening 20 of the insulating film 19 has the second conductive layer 16b,
It is desirable to be located at the center between 16c and the third conductive layers 21b and 21c. Further, the opening 20 of the insulating film 19 is
First and second conductive layers 13b, 13c, 16b, 16c
Since it is provided to electrically connect the third conductive layers 21b and 21c with each other, the number and shape of the openings 20 may be any number as long as they can be connected, and a plurality of openings 20 may be provided. Furthermore, the insulating film 19 in the peripheral circuit region can be entirely removed.

In the memory cell region, the first and second conductive layers 13a and 16a function as the floating gate of the memory transistor 23, and the third conductive layer 21a functions as the control gate of the memory transistor 23.

Normally, the PMOS transistor is composed of a P-type conductive layer, but the third conductive layer 21c of the PMOS transistor 25 according to the first embodiment is an N ⁺ -type conductive layer. Therefore, in order to sufficiently function as the gate of the PMOS transistor 25, the first to third conductive layers 13a, 13b, 13c, 16a, 16b, 16 are provided.
c, 21a, 21b, 21c have an impurity concentration of 1 × 1
It is desirable to set it to 0 ¹⁸ cm ^-3 or more.

As shown in FIG. 2, in the semiconductor device according to the first embodiment, the third region of the NMOS region and the PMOS region is formed.
The conductive layers 21b and 21c can be formed by the same layer of the same conductivity type (N ⁺ type). Therefore, the third conductive layer 21b of the NMOS transistor 24 and the third conductive layer 21c of the PMOS transistor 25 do not have to be separated on the element isolation insulating film 15. That is, the third conductive layer 21 b and the third conductive layer 21 c are continuously formed on the element isolation insulating film 15.

3 to 10 are sectional views showing the steps of manufacturing a semiconductor device according to the first embodiment of the present invention. The method for manufacturing the semiconductor device according to the first embodiment will be described below.

First, as shown in FIG.
A first insulating film 12 serving as a gate insulating film is formed thereon,
The first electrode material 13 is formed on the first insulating film 12. The first electrode material 13 is made of polysilicon in which impurities are not implanted. Next, the second insulating film 14 made of, for example, a silicon nitride film is deposited on the first electrode material 13.

Next, as shown in FIG. 4, the second insulating film 1
4, the first electrode material 13, the first insulating film 12 and the semiconductor substrate 11 are selectively removed to form an element isolation groove. An element isolation insulating film 15 made of, for example, an oxide film is deposited in the element isolation groove, and the element isolation insulating film 15 is formed.
Is planarized until the surface of the second insulating film 14 is exposed. That is, the second insulating film 14 is the element isolation insulating film 1
At the time of flattening of No. 5, it functions as a stopper film. In this way, the STI (Shal
An element isolation region having a low Trench Isolation structure is formed. Then, the second insulating film 14 is peeled off.

Next, as shown in FIG. 5, the first electrode material 1
A second electrode material 16 made of polysilicon not implanted with impurities is formed on the element 3 and the element isolation insulating film 15. Next, until the surface of the element isolation insulating film 15 is exposed,
The second electrode material 16 is removed.

Next, as shown in FIG. 6, the second electrode material 1
A resist 17 is formed on the insulating film 6 and the element isolation insulating film 15, and the resist 17 is patterned so as to remain only on the PMOS region. Using the patterned resist 17 as a mask, ion implantation is performed on the second electrode material 16 in the memory cell region and the NMOS region.
In this ion implantation, for example, As is used as an N-type impurity.
(Arsenic) or P (phosphorus) is used. Then, by heat treatment, the impurities injected into the second electrode material 16 are diffused to the first electrode material 13, and the N ⁺ -type first conductive layer 13 is formed.
a, 13b and the second conductive layers 16a, 16b are formed. Then, the resist 17 is removed.

Next, as shown in FIG. 7, the second conductive layer 1
A resist 18 is formed on the 6a and 16b and the element isolation insulating film 15.
Is formed, and the resist 18 serves as a memory cell region and N
It is patterned so as to remain only on the MOS region. Using the patterned resist 18 as a mask, P
Ion implantation is performed on the second electrode material 16 in the MOS region. For this ion implantation, for example, B (boron) is used as a P-type impurity. After that, the impurities injected into the second electrode material 16 are removed by heat treatment from the first electrode material 13.
To the P ⁺ -type first conductive layer 13c and the second conductive layer 16c. Then, the resist 18 is removed.

Next, as shown in FIG. 8, the second conductive layer 1
A third insulating film 19 is deposited on 6a, 16b and 16c and the element isolation insulating film 15.

Next, as shown in FIG. 9, a part of the third insulating film 19 in the peripheral circuit region is removed to form openings 20 respectively. Although it is possible to completely remove the third insulating film 19 in the peripheral circuit region in this step, it is preferable to form the opening 20 and leave the third insulating film 19 in the peripheral circuit region. .

Next, as shown in FIG. 10, a third electrode material 21 is deposited on the third insulating film 19 and the second conductive layers 16b and 16c. Here, the third electrode material 21 is made of polysilicon in which N-type impurities are implanted. Next, the third
A metal film 22 made of, for example, a WSi (tungsten silicon) film is formed on the electrode material 21 of FIG.

Next, as shown in FIGS. 1 and 2, the metal film 2
The second and third electrode materials 21 are selectively removed. As a result, the memory transistor 23 and the peripheral transistor 2
4, 25 gate patterns are formed.

FIG. 11 shows the first embodiment of the present invention compared with the conventional example.
9 is a graph showing an IV characteristic of the semiconductor device according to the embodiment. In this graph, the IV voltage between the P ⁺ type gate formed of the first and second conductive layers 13c and 16c in the PMOS transistor 25 and the N ⁺ type gate formed of the third conductive layer 21c in the PMOS transistor 25 is shown. Evaluating the characteristics. As a result, as shown in FIG. 11, as in the case of the conventional example, a good IV characteristic having a substantially straight line was obtained. Therefore, even when the PMOS transistor 25 is composed of the P ⁺ type gate and the N ⁺ type gate as in the first embodiment, the PN junction is not formed and the gate function is sufficiently fulfilled. It can be said that Further, according to the present invention, it is possible to reduce the voltage to 1.8 V or less.

According to the first embodiment, the gate of the NMOS transistor 24 and the gate of the PMOS transistor 25 can be formed by the third electrode material 21 of the same conductivity type. In other words, it is not necessary to separately implant impurities in the gate of the NMOS transistor 24 and the gate of the PMOS transistor 25 by using the exposure technique. Therefore, a dual gate function CMOS transistor can be easily formed.

Further, the third electrode material 21 of the NMOS and PMOS transistors 24 and 25 can be used as the control gate of the memory transistor 23 without ion implantation. Therefore, the process can be further facilitated.

Further, the third conductive layer 21b of the NMOS transistor 24 and the third conductive layer 21c of the PMOS transistor 25 can be continuously formed on the element isolation insulating film 15. Therefore, it is not necessary to separate the third conductive layer 21b and the third conductive layer 21c from each other, so that the area occupied by the peripheral circuit region can be reduced.

In the peripheral transistors 24 and 25,
Second and third conductive layers 16b, 21b, 16c, 21c
A third insulating film 19 having an opening 20 is provided therebetween. Therefore, the end portion of the gate electrode has a three-layer structure in which the third insulating film 19 is interposed between the second and third conductive layers 16b, 21b, 16c and 21c. On the other hand, in the memory transistor 23, the second and third conductive layers 16a, 2
It has a three-layer structure in which the third insulating film 19 is interposed on the entire surface between 1a. Therefore, regarding the end portion of the gate electrode on which the gate processing is performed, the laminated structure of the gates in the peripheral transistors 24 and 25 and the memory transistor 23 is the same. Therefore, the gate processing can be simultaneously performed on the memory transistor 23 and the peripheral transistors 24 and 25 without changing the etching conditions.

Further, since the separation of the first electrode material 13 is performed in a self-aligned manner with the formation of the element isolation region shown in FIG.
It is possible to miniaturize the cell size.

As described above, the present invention is very effective for a mixed memory of a non-volatile memory and a logic device such as a CPU.

[Second Embodiment] In the second embodiment, P
Made of an N-type first conductive layer and an N-type second conductive layer
This is an example in which an electrode material in which impurities are implanted is used for the first conductive layer when forming the OS transistor. still,
Since the final structure of the second embodiment is the same as that of the first embodiment, the description of the structure is omitted.

12 to 16 are sectional views showing the steps of manufacturing a semiconductor device according to the second embodiment of the present invention. The method for manufacturing the semiconductor device according to the second embodiment will be described below. In the method of manufacturing the semiconductor device according to the second embodiment, the description of the same steps as those of the method of manufacturing the semiconductor device according to the first embodiment will be simplified, and only different steps will be described.

First, as shown in FIG. 12, the semiconductor substrate 1
A first insulating film 12 serving as a gate insulating film is formed on the first insulating film 12, and a first electrode material 31 is formed on the first insulating film 12. Here, the first electrode material 31 is made of polysilicon in which an N-type impurity such as P or As is implanted. Next, the second insulating film 14 made of, for example, a silicon nitride film is deposited on the first electrode material 31.

Next, as shown in FIG. 13, the second insulating film 14, the first electrode material 31, the first insulating film 12 and the semiconductor substrate 11 are selectively removed to form a device isolation groove. To be done. An element isolation insulating film 15 made of, for example, an oxide film is deposited in the element isolation groove, and the element isolation insulating film 15 is formed.
Is planarized until the surface of the second insulating film 14 is exposed. In this way, S made of the element isolation insulating film 15 is formed.
An element isolation region having a TI structure is formed. Then, the second insulating film 14 is peeled off.

Next, as shown in FIG. 14, a second electrode material 16 made of polysilicon not doped with impurities is formed on the first electrode material 31 and the element isolation insulating film 15. Next, the second electrode material 16 is removed until the surface of the element isolation insulating film 15 is exposed.

Next, as shown in FIG. 15, a resist 17 is formed on the second electrode material 16 and the element isolation insulating film 15, and is patterned so that the resist 17 remains only on the PMOS region. A heat treatment is performed using the patterned resist 17 as a mask. Thus, the impurities in the first electrode material 31 are diffused to the second electrode material 16, and the N ⁺ -type first conductive layers 31a and 31b and the second conductive layers 16a and 16b are formed. After that,
The resist 17 is removed.

Next, as shown in FIG. 16, the resist 1 is formed on the second conductive layers 16a and 16b and the element isolation insulating film 15.
8 is formed, and this resist 18 is patterned so as to remain only on the memory cell region and the NMOS region.
Using the patterned resist 18 as a mask,
Ion implantation is performed on the second electrode material 16 in the PMOS region. For this ion implantation, for example, B (boron) is used as a P-type impurity. After that, by heat treatment,
Impurities injected into the second electrode material 16 are removed from the first electrode material 3
1 to the P ⁺ -type first conductive layer 31c and the second
Conductive layer 16c is formed. Then, the resist 18 is removed.

After that, the semiconductor device as shown in FIGS. 1 and 2 is formed through the steps shown in FIGS. 8 to 10 as in the first embodiment.

According to the second embodiment, the same effect as that of the first embodiment can be obtained.

Furthermore, the step of implanting impurities into the first electrode material 13 in the memory cell region and the NMOS region can be omitted. Therefore, the number of manufacturing steps can be reduced and the manufacturing can be facilitated.

It should be noted that the first electrode material 31 may be made of polysilicon not doped with impurities, and the second electrode material 16 may be made of polysilicon doped with impurities. In this case, by performing heat treatment, the impurities in the second electrode material 16 are diffused into the first electrode material 31, and the first and second conductive layers 31a, 31b, 31c, 16a, 16b, 16 are formed.
It is sufficient to form c.

In addition, the present invention is not limited to each of the above-described embodiments, and can be variously modified at the stage of implementation without departing from the spirit of the invention. further,
The embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiment,
When the problem described in the column of the problem to be solved by the invention can be solved and the effect described in the column of the effect of the invention can be obtained, a configuration in which this constituent element is deleted can be extracted as the invention.

[0045]

As described above, according to the present invention, it is possible to provide a semiconductor device capable of facilitating the process and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention in a direction perpendicular to an element isolation region.

FIG. 2 is a sectional view of the semiconductor device according to the first embodiment of the present invention in a direction perpendicular to a gate electrode.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 3;

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 4;

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 5;

FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 6;

FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 7;

FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 8;

FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 9;

FIG. 11 is a graph showing IV characteristics of the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the invention.

FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 12;

FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 13;

FIG. 15 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 14;

FIG. 16 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 15;

[Explanation of symbols]

11 ... Semiconductor substrate, 12 ... First insulating film, 13, 31 ... First electrode material, 13a, 13b, 13c, 31a, 31b, 31c ... First conductive layer, 14 ... Second insulating film, 15 ... element isolation insulating film, 16 ... second electrode material, 16a, 16b, 16c ... second conductive layer, 17, 18 ... resist, 19 ... third insulating film, 20 ... opening, 21 ... third Electrode material, 22 ... Metal film, 23 ... Memory transistor, 24 ... NMOS transistor, 25 ... PMOS transistor.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/43 H01L 27/10 434 29/788 29/78 371 29/792 F term (reference) 4M104 AA01 BB01 BB40 CC05 DD55 DD78 FF13 FF14 GG09 GG10 GG14 GG16 HH14 5F048 AA01 AA09 AB01 AC03 BA01 BB01 BB03 BB06 BB07 BB08 BG14 5F083 EP23 GA09 GA28 JA32 JA35 JA53 NA21 PR35 PR53 PR08 PR31 PR44 PR44 PR44 PR44 PR44 PR44 PR44 PRZA

Claims (35)

[Claims] 1. A semiconductor device having a gate electrode of a first conductivity type, wherein the gate electrode is formed on a semiconductor substrate.
A semiconductor device comprising a first conductive type conductive layer and a second conductive type second conductive layer formed on the first conductive layer. 2. A semiconductor device comprising a first gate electrode of a first conductivity type and a second gate electrode of a second conductivity type, wherein the first gate electrode is formed on a semiconductor substrate. The first conductive type first conductive layer and the second conductive type second conductive layer formed on the first conductive layer, wherein the second gate electrode is the semiconductor A semiconductor comprising: a second conductive type third conductive layer formed on a substrate; and a second conductive type fourth conductive layer formed on the third conductive layer. apparatus. 3. A semiconductor device comprising a peripheral circuit region having the first gate electrode and the second gate electrode, and a memory cell region having the third gate electrode of the second conductivity type. The third gate electrode includes a fifth conductive layer of the second conductivity type formed on the semiconductor substrate, a third insulating film formed on the fifth conductive layer, 3. The semiconductor device according to claim 2, comprising the sixth conductive layer of the second conductivity type formed on the third insulating film. 4. The insulating film, which is formed between the first and second conductive layers and has an opening for connecting the first and second conductive layers to each other.
The semiconductor device described. 5. A first insulating film formed between the first and second conductive layers, the first insulating film having a first opening for conducting the first and second conductive layers, and the third and fourth insulating films. 4. The semiconductor device according to claim 2, further comprising: a second insulating film formed between the conductive layers of the second insulating film and having a second opening portion for connecting the third and fourth conductive layers. . 6. The semiconductor device according to claim 4, wherein the opening of the insulating film is located at the center between the first and second conductive layers. 7. The first opening of the first insulating film is located in the center between the first and second conductive layers, and the second opening of the second insulating film is The semiconductor device according to claim 5, wherein the semiconductor device is located in the center between the third and fourth conductive layers. 8. The semiconductor device according to claim 4, wherein a plurality of the openings of the insulating film are provided between the first and second conductive layers. 9. A plurality of the first openings of the first insulating film are provided between the first and second conductive layers, and the second openings of the second insulating film are The semiconductor device according to claim 5, wherein a plurality of layers are provided between the third and fourth conductive layers. 10. The impurity concentration of the first and second conductive layers
Degree is 1 x 10 each ¹⁸cm^-3It is characterized by the above
The semiconductor device according to claim 1, wherein 11. The impurity concentration of the first to fourth conductive layers
Degree is 1 x 10 each ¹⁸cm^-3It is characterized by the above
The semiconductor device according to claim 2, wherein 12. An element isolation region formed of an element isolation insulating film for isolating an element region of the semiconductor substrate is formed, and the second conductive layer and the fourth conductive layer are formed on the element isolation insulating film. The semiconductor device according to claim 2, wherein the semiconductor device is formed continuously. 13. The semiconductor device according to claim 1, wherein the first conductive layer has a two-layer structure. 14. The first and third conductive layers are each 2
The semiconductor device according to claim 2, wherein the semiconductor device has a layered structure. 15. The first, third and fifth conductive layers include:
4. The semiconductor device according to claim 3, wherein each has a two-layer structure. 16. The semiconductor device according to claim 1, wherein the first conductivity type is P type and the second conductivity type is N type. 17. The semiconductor device according to claim 3, wherein in the third gate electrode, the fifth conductive layer functions as a floating gate, and the sixth conductive layer functions as a control gate. . 18. A method of manufacturing a semiconductor device comprising a first conductive type gate electrode composed of first and second conductive layers, the method comprising: forming a first insulating film on a semiconductor substrate; A step of forming a first electrode material on which impurities are not introduced on the first insulating film; and element isolation including the first electrode material, the first insulating film, and the element isolation insulating film in the semiconductor substrate. A step of forming a region, a step of forming the first conductive layer of the first conductivity type by performing ion implantation and heat treatment on the first electrode material, and the first conductive layer and A step of forming a second conductive type second electrode material on the element isolation insulating film and forming the second conductive layer made of the second conductive material. Production method. 19. A first region having a first gate electrode of a first conductivity type composed of first and second conductive layers, and a second region of a second conductivity type composed of third and fourth conductive layers. And a second region having a gate electrode, the method comprising: forming a first insulating film on a semiconductor substrate; and introducing impurities into the first insulating film. Forming a first electrode material that does not exist, forming an element isolation region formed of an element isolation insulating film in the first electrode material, the first insulating film, and the semiconductor substrate; and the second region The step of forming the third conductive layer of the second conductivity type by performing ion implantation and heat treatment on the first electrode material of the first electrode material in the first region. By performing ion implantation and heat treatment, the first conductivity type of the first conductivity type is obtained. And a step of forming the second conductive type second electrode material on the first conductive layer, the third conductive layer and the element isolation insulating film, and the second conductive material is used. The second conductive layer and the fourth
And a step of forming a conductive layer. 20. A first region having a first gate electrode of a first conductivity type composed of first and second conductive layers and a second region of a second conductivity type composed of third and fourth conductive layers. A semiconductor device comprising: a peripheral circuit region having a second region having a gate electrode; and a memory cell region having the second gate electrode of the second conductivity type composed of fifth and sixth conductive layers. A step of forming a first insulating film on a semiconductor substrate; a step of forming a first electrode material on which impurities have not been introduced on the first insulating film; A step of forming an element isolation region made of an element isolation insulating film in the electrode material, the first insulating film and the semiconductor substrate, and the first electrode material in the second region and the memory cell region. By performing ion implantation and heat treatment,
The step of forming the third conductive layer and the fifth conductive layer of the second conductivity type, and the step of performing ion implantation and heat treatment on the first electrode material in the first region, A step of forming the first conductive layer of a first conductivity type, a step of forming a second insulating film on the fifth conductive layer, the second insulating film, the first conductive layer, By forming and patterning the second conductive type second electrode material on the third conductive layer and the element isolation insulating film, the second conductive layer made of the second conductive material, A method of manufacturing a semiconductor device, comprising: forming a fourth conductive layer and the sixth conductive layer. 21. The first electrode material comprises a first layer and a second layer, and one of the first layer and the second layer is preliminarily implanted with the impurity of the first conductivity type. 19. The method for manufacturing a semiconductor device according to claim 18, wherein a layer is used. 22. The first electrode material comprises a first layer and a second layer, and one of the first layer and the second layer is preliminarily implanted with the impurity of the first conductivity type. 20. The method of manufacturing a semiconductor device according to claim 19, wherein the third conductive layer is formed by using a layer to diffuse the impurities to the other layer by heat treatment. 23. The first electrode material comprises a first layer and a second layer, and one of the first layer and the second layer is preliminarily implanted with the impurity of the first conductivity type. 21. The method of manufacturing a semiconductor device according to claim 20, wherein a layer is used to diffuse the impurities to the other layer by heat treatment to form the third conductive layer and the fifth conductive layer. 24. A second insulating film is formed between the first and second conductive layers, and the first and second insulating films are formed on the second insulating film.
19. The method of manufacturing a semiconductor device according to claim 18, further comprising forming an opening for electrically connecting the conductive layer. 25. The second insulating film is formed between the first and second conductive layers and between the third and fourth conductive layers, and the first and second conductive layers are formed on the second insulating film. Layer, the third
21. The method of manufacturing a semiconductor device according to claim 19, further comprising forming an opening for electrically connecting the fourth conductive layer and the fourth conductive layer. 26. The method of manufacturing a semiconductor device according to claim 18, wherein the opening of the second insulating film is formed in the center between the first and second conductive layers. 27. The second opening of the second insulating film is formed in the center between the first and second conductive layers and in the center between the third and fourth conductive layers, respectively. The method for manufacturing a semiconductor device according to claim 19 or 20. 28. The method of manufacturing a semiconductor device according to claim 18, wherein a plurality of the openings of the second insulating film are formed between the first and second conductive layers. 29. A plurality of the second openings of the second insulating film are formed in each of the first and second conductive layers and the third and fourth conductive layers. 21. A method of manufacturing a semiconductor device according to claim 19 or 20. 30. Concentration of impurities in the first and second conductive layers
Degree is 1 x 10 each ¹⁸cm^-3It is characterized by the above
19. The method for manufacturing a semiconductor device according to claim 18, further comprising: 31. Concentration of impurities in the first to fourth conductive layers
Degree is 1 x 10 each ¹⁸cm^-3It is characterized by the above
20. The method of manufacturing a semiconductor device according to claim 19. 32. The impurity concentration of the first to sixth conductive layers
Degree is 1 x 10 each ¹⁸cm^-3It is characterized by the above
21. The method for manufacturing a semiconductor device according to claim 20, wherein 33. The method of manufacturing a semiconductor device according to claim 19, wherein the second conductive layer and the fourth conductive layer are continuously formed on the element isolation insulating film. . 34. The first conductivity type is P-type, and the second conductivity type is N-type.
21. The method for manufacturing a semiconductor device according to any one of 20 to 20. 35. The semiconductor device according to claim 20, wherein in the third gate electrode, the fifth conductive layer functions as a floating gate, and the sixth conductive layer functions as a control gate. Manufacturing method.