JPH0344076A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form low-concentration source-drain regions easily by diffusing an impurity from a semiconductor layer buried into the trench of a substrate by utilizing the semiconductor layer for shaping a gate electrode and forming the low-concentration source-drain regions. CONSTITUTION:A doped polysilicon layer 27 containing an N-type impurity in high concentration is deposited on the whole surface on a substrate 21 includ ing trenches 26. The doped polysilicon layer 27 is etched while using a resist pattern 28 as a mask, thus shaping a gate electrode 27a. An inter-layer insulat ing film 29 formed onto the substrate 21 is thermally treated for smoothing. The N-type impurity of the doped polysilicon layer 27 in the trenches 26 is activated through the heat treatment, and changed into N<+> regions 27b as high- concentration source-drain regions. The N-type impurity is diffused into the peripheral substrate 21 from the doped polysilicon layer 27 at the same time, thus shaping N<-> regions 30 as low-concentration source-drain regions.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing an MO3 type transistor.

(Prior art) In an MO3 type transistor, if the drain has a structure with a concentration gradient, for example, by a double diffusion layer of n' and n- layers, concentration of electric field strength is alleviated, and long-term life deterioration due to hot electrons is avoided. "Dark value fluctuation" which is the cause of this, and source/drain breakdown voltage are greatly improved.

An MO3 type transistor having such a drain structure has conventionally been manufactured as shown in FIG.

First, a gate oxide film 2 is formed on the surface of a semiconductor substrate 1 as shown in FIG. 2 (al), and then ion implantation 3 for Vt (threshold) control is performed as shown in FIG.
An impurity 3a is obtained in the substrate 1.

Next, as shown in FIG. 2(c), a polysilicon layer 4 for forming a gate electrode is formed on the substrate 1, and then a second polysilicon layer 4 is formed on it.
As shown in FIG. dl, a resist pattern 5 is formed by a known photolithography technique.
The polysilicon layer 4 is etched using the mask as a mask, and the second
A gate electrode 4a is formed by selectively leaving it as shown in FIG.

Furthermore, after forming the gate electrode 4a, unnecessary portions of the gate oxide film 2 are also etched away using it as a mask.

After that, a mask oxide film 6 is formed on the surface of the substrate 1 and the gate electrode 4a as shown in FIG. 2 (fl), and then ion implantation 7 for forming low concentration source/drain regions is shown in FIG. 2fg. The impurity 7a is obtained in the substrate 1.

Thereafter, a channel region 3b and a low concentration source/drain region 7b are formed in the substrate 1 as shown in FIG. 2 (hl) by performing a diffusion process of impurities 3a and 7a. After performing ion implantation 8 to form the source/drain regions and obtaining impurities 8a in the low concentration source/drain regions 7b, drive-in is performed to form the high concentration source/drain regions 7b as shown in FIG.
Drain region 8b is formed within lightly doped source/drain region 7b.

Thereafter, as shown in FIG. 2(1), a glabellar insulating film 9 is formed on the entire surface, and a resist pattern 10 is formed thereon. Then, by etching the interlayer insulating film 9 and the mask oxide film 6 using this resist pattern IO as a mask, a contact hole 11 is formed therein as shown in FIG. 2.

Then, high concentration contact ion implantation 12 is performed through the contact hole 11 into the high concentration source/drain region 8b as shown in FIG.
get. Subsequently, a heat treatment is performed to activate the impurity 12a, thereby forming a contact region 12b in the heavily doped source/drain region 8b as shown in FIG. 2 (kl).

Thereafter, as shown in the figure, a metal wiring 13 is formed so as to be connected to the contact region 12b and the gate electrode 4a through the contact hole 11, thereby completing the transistor.

(Problem to be Solved by the Invention) However, in the conventional manufacturing method as described above, since an ion implantation process or the like is required to form the low concentration source/drain region 7b, the low concentration source/drain region 7b is There was a problem that the formation process was complicated.Furthermore, in order to properly connect the source/drain region and the metal wiring 13, it was necessary to form the contact region 12b within the highly doped source/drain region 8b. The process becomes complicated.Furthermore, during contact ion implantation for forming the contact region t2b, contact defects occur due to charge-up, resulting in a problem of deterioration of characteristics. Further, since the effective channel length between the source and drain is determined by the photolithography process shown in FIG. 2 fdl, fine control is difficult.

The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can eliminate the above conventional problems.

(Means for Solving the Problems) In the present invention, grooves are formed in regions of a semiconductor substrate where high concentration sources and drains are to be formed.Then, when a gate electrode is formed using a semiconductor layer containing a high concentration of impurities, this semiconductor layer is A layer is left as a high concentration source/drain region in the groove, and a low concentration source/drain region is formed by impurity diffusion from this semiconductor layer.Furthermore, a contact hole is opened in the interlayer insulating film on the semiconductor layer. Then, wiring is formed by connecting to the semiconductor layer.Moreover, the impurity diffusion is performed using heat treatment for smoothing the interlayer insulating film.

(Function) In the above-mentioned invention, the highly doped source/drain regions are formed using the semiconductor layer for forming the gate electrode, and the lightly doped source/drain regions are formed by only impurity diffusion from this semiconductor layer. is easily formed. Furthermore, this impurity diffusion is performed using heat treatment during smoothing of the interlayer insulating film, so there is no increase in the number of steps. Furthermore, the highly doped source/drain regions made of the semiconductor layer in the trench can be formed only in the connection area with the wiring, as shown in FIG. The concentration can be so high that it doubles as a region. Therefore, a region corresponding to a conventional contact region can be omitted. Also, the effective channel length between source and drain is
It can be controlled by the degree of formation of the low concentration source/drain regions, that is, the degree of diffusion of impurities from the semiconductor layer in the trench, and fine control can be achieved by diffusion.

(Example) An embodiment of the present invention will be described below with reference to FIG.

One example of this is the case of manufacturing an N-channel MO3 type transistor.

First, as shown in FIG. 1(a), a P-type silicon substrate 21
After forming an oxide film 22 as a gate insulating film on the surface of the substrate 21, a resist pattern 23 is formed thereon, and ion implantation 24 is performed using the resist pattern 23 as a mask to form a region of the substrate 21 that is to become a transistor region. Inject P-type impurity 24-a for dark value control.

Next, after removing the resist pattern 23, as shown in FIG.
1(c), a new resist pattern 25 is formed as shown in FIG. As shown in FIG. 2, grooves 26 are formed in the substrate 21 at locations where highly doped source/drain regions are to be formed.

Next, after removing the resist pattern 25, a doped polysilicon layer containing a high concentration of N-type impurities such as phosphorus is formed on the entire surface of the substrate 21 including the groove 26, as shown in FIG. 1(d). 27 is deposited to the desired thickness by LPGVD (K direct graphical vapor deposition) technique. Furthermore, a resist pattern 28 is formed on the portion of the doped polysilicon layer 27 that will become the gate electrode, as shown in FIG. 1 (d+).

Thereafter, using the resist pattern 28 as a mask, the doped polysilicon layer 27 is etched by RIE technology, leaving the doped polysilicon layer 27 under the resist pattern 28 on the substrate 21 as shown in FIG. A gate electrode 27a is formed. At this time, groove 26
The doped polysilicon layer 27 inside is also left unetched, and the inside of a26 is filled with the doped polysilicon layer 27.

Thereafter, after removing the resist pattern 28, an interlayer insulating film 29 is formed on the entire surface of the substrate 21 as shown in FIG. By this heat treatment, 'a26
The N-type impurity in the doped polysilicon layer 27 is activated, and the doped polysilicon layer 27 becomes an N' region 27b as a heavily doped source/drain region, as shown in FIG. 1(f).

Also, at this time, at the same time, N
Type impurities (for example, phosphorus) diffuse into the surrounding substrate 21,
An N- region 30 as a low concentration source/drain region is formed around the N+ region 27b. Furthermore, the P-type impurity 24a implanted in the process of FIG.
161 area 24b is formed.

Thereafter, a resist pattern 31 is formed on the glabella insulating film 29 as shown in FIG. As shown in FIG. 1 (hl), a contact hole 32 is opened above the <N'' region 27b and the gate electrode 27a.

Further, after removing the resist pattern 31, as shown in FIG.
As shown in hl, a metal layer 33 is formed on the entire surface, a resist pattern 34 is formed on the metal layer 33, and the metal layer 33 is patterned using the resist pattern 34 as a mask to form the N4 region 27b ( A metal wiring 35 connected to the source/drain region) and the gate electrode 27a is formed as shown in FIG. 1 (il). Thus, an N-channel MO3 transistor is completed.

Although this embodiment is a case where an N-channel MO3 type transistor is formed, it goes without saying that a P-channel type can be formed in exactly the same manner.

Further, in the above embodiment, the doped polysilicon layer 27 is formed as a doped semiconductor layer by LPC in the step +di in FIG.
Although the VD method is used to form the doped single crystal silicon layer, the doped single crystal silicon layer may also be formed by epitaxial growth. in this case,
A polysilicon layer naturally forms on the oxide film 22.

(Effects of the Invention) As described above in detail, according to the manufacturing method of the present invention, impurities are diffused from the semiconductor layer buried in the groove of the substrate using the semiconductor layer for forming the gate electrode. Since the low concentration source/drain regions are formed, the low concentration source/drain regions can be formed much more easily than a conventional method using ion implantation or the like. Moreover, the impurity diffusion in this case is performed simultaneously using the heat treatment during smoothing of the interlayer insulating film, so there is no increase in the number of steps, and the steps can be further simplified.

In addition, the semiconductor layer buried in the trench is a highly doped source.
This will become the drain region, but this highly concentrated source and
The drain region can be formed only at the connection part with the wiring, for example, as shown in FIG. According to the invention, the process can be simplified by omitting the region corresponding to the conventional contact region.Furthermore, if the formation of the contact region can be omitted, the contact ion implantation can be eliminated, and contact defects due to the charge amplifier during contact ion implantation can be eliminated. In addition, in this invention, the effective channel length between the source and drain is determined by the degree of formation of the lightly doped source and drain regions, that is, by the degree of diffusion of impurities from the semiconductor layer in the trench. It has the effect of being able to be controlled finely by diffusion.

[Brief explanation of drawings]

1 FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 is a process sectional view showing a conventional manufacturing method. 21... P-type silicon substrate, 22... Oxide film, 26
... Groove, 27... Doped polysilicon layer, 27a
...gate electrode, 27b...N'' region, 29...
Interlayer insulating film, 30...N- region, 32... Contact hole, 35... Metal wiring. a 3b Figure 2 of the 5th Qing

Claims (1)

[Claims] (a) A step of forming a gate insulating film on the surface of a semiconductor substrate, and further forming a groove in a region where a high concentration source/drain is to be formed on the surface of the semiconductor substrate; (b) forming the groove. (c) etching the semiconductor layer to form a gate electrode made of the remaining semiconductor layer on the substrate; (d) After that, an interlayer insulating film is formed on the entire surface of the substrate, and this interlayer insulating film is smoothed by heat treatment.
At the same time, a step of diffusing impurities from the semiconductor layer in the groove into the substrate to form a low concentration source/drain region around the semiconductor layer; A method of manufacturing a semiconductor device, comprising the steps of: forming a contact hole on the semiconductor layer; and forming a wiring connected to the semiconductor layer through the contact hole.