JPS62291178A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the increase of the resistances of source and drain even when a channel is shortened by burying a metal or semiconductor material in a groove formed in a semiconductor substrate of source and drain regions. CONSTITUTION:In an MOS transistor, grooves are formed in source and drain regions, metal or semiconductor is buried in the grooves to laterally diffuse an impurity in the metal and semiconductor, thereby forming a superposing part of channel with the source and drain. Thus, even when the transistor is shortened in its channel, it is not necessary to form shallow the source and drain to form the source and drain in low resistance.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to the structure and manufacturing method of the source and drain of a MOS transistor.

[Summary of the invention]

The present invention provides a MOS type l-run lister in which grooves are prepared in the source and drain regions, the grooves are filled with a metal having the same polarity as the source and drain, or a semiconductor material different from the semiconductor substrate material, and the metal or semiconductor is By making impurities transversely wave 11 and forming an overlapping part between the channel part and the source and drain regions, (1) the resistance of the source and I-rain does not need to be increased even when the channel is shortened; 2) illi I Hoso] - Elek 1 ~ Ron sex first
r[Lc, ta, thing.

[Conventional technology]

Sources of conventional semiconductor devices and 11-11 C
, l, had a structure as shown in FIG. 2, and was formed by thermal diffusion or ion implantation.

Here, 21 is a substrate, 22 is a source (source) wide loss layer, 23 is a drain diffusion layer, 24 is an ogate nail electrode, and 25 is a gate insulating film.

[Problem that the invention seeks to solve]

However, in the above-mentioned conventional technology, when the MOS type transistor is miniaturized and the channel is shortened, the following problems occur.

In order to reduce the short channel effect of the fl1MOS type l-run lister, it is necessary to form a shallow layer in the source and drain expansion 11.
``Rain resistance increases.

(2) Day 1 - Train and source expansion 1 directly below the electrode
Due to the steep concentration profile of the first layer, Bott electrons reduce the reliability of the device.

Therefore, the present invention solves these problems.
The objectives are: (11) Even if the channel of a MOS transistor is shortened, the source and drain resistance will not increase. (2) To provide a semiconductor device with excellent hot electron resistance. It is.

[Means for solving problems]

In the semiconductor device of the present invention, grooves are prepared in the source and ruin regions, a metal or semiconductor having the same polarity as the source and drain is formed in the grooves, and impurities are laterally diffused from the metal or semiconductor to form the channel portion. It forms an overlapping portion with the source and drain diffusion layers.

[For production]

According to the structure of item 2 of the present invention, a groove is prepared in the source and [-1 fin regions, and the depth of the groove is to be buried in order to bury the metal or semiconductor that will become the source and [-1 fin region 41]. The depth of the source and drain can be determined according to the
By increasing the depth, the resistance can be lowered. Furthermore, by heat treatment, impurities in the metal or semiconductor described in (-) are laterally diffused to form overlapping portions between the channel portion and the source and drain portions. At this time, the short channel effect can be minimized by setting the minimum necessary thermal process to form the overlapping portion.

In addition, in this case, the impurity concentration distribution in the overlapping portion of the channel and drain portions shows a gentler distribution than in the case where the drain diffusion layer is formed by ion implantation, and in this respect, the impurity concentration distribution in the overlapping portion of the channel region and the drain region is more gradual than that in the case where the drain diffusion layer is formed by ion implantation. There is.

〔Example〕

FIG. 1 is a main sectional view in an embodiment of the present invention,
11 is a substrate; 12 is arsenic-doped polysilicon in the drain region; 13 is arsenic-doped polysilicon in the source region; 15 is a gate electrode, and 16 is a gate insulating layer.

In this example, arsenic-doped polysilicon is considered as the material for the source and drain regions, but by combining instantaneous annealing such as lamp annealing, the overlapping portions of the channel region and the source and drain materials can be reduced. The short channel effect can be avoided as much as possible. Furthermore, as mentioned above, the impurity concentration distribution directly under the gate does not have the same curvature as in the case of ion implantation, so the generation of Bot electrons is sufficiently suppressed.
Therefore, it has a structure with excellent hot electron resistance. Furthermore, by digging the trench deep enough to have the desired resistance and by increasing the arsenic concentration in the polysilicon sufficiently, low resistance can be maintained even when the channel is shortened.

〔Effect of the invention〕

As described above, according to the present invention, in a MO'S transistor, a trench is formed in the n region of the source and drain regions, a metal or a semiconductor is buried in the trench, and impurities in the metal and semiconductor are removed laterally. By creating a structure in which the channel part and the source and drain overlap with each other by diffusion in the direction, there is no need to form the source and drain shallowly even if the channel part of the 11 MOS transistor is shortened. (2) Since the concentration profile of the 1-rain and source expansion 11-layer directly under the gate has no curvature, the generation of hot electrons can be achieved, resulting in high reliability of the device. .

It has this effect.

[Brief explanation of the drawing]

FIG. 1 is a main sectional view showing an embodiment of the semiconductor device of the present invention. FIG. 2 is a main sectional view showing a conventional semiconductor device. 11...Substrate 12...Polysilicon doped with arsenic 13 in the drain region...Polysilicon 14 doped with arsenic in the source region... ....ω element diffusion region 15 thermally diffused from the source and drain regions...Gate electrode 16...Gate insulating layer 21...Substrate 22... Drain diffusion layer 23...Source diffusion layer 24...Gate electrode 25...Gate insulating film 2

Claims (3)

[Claims] (1) A MOS type semiconductor device formed on a semiconductor substrate, characterized in that source and drain regions of the MOS type semiconductor device are formed of metal or a semiconductor material different from the material of the semiconductor substrate. semiconductor device. (2) A semiconductor device according to claim 1, wherein grooves are formed in the semiconductor substrate in the source and drain regions, and the metal or the semiconductor material is embedded in the grooves. . (3) The overlapping portion between the channel portion of the MOS type semiconductor device and the source and drain regions is a diffusion region formed by impurity diffusion from the metal or the semiconductor material. A semiconductor device according to scope 1 or 2.