JPS6362382A - Floating gate nonvolatile semiconductor storage device and manufacture thereof - Google Patents

Floating gate nonvolatile semiconductor storage device and manufacture thereof

Info

Publication number
JPS6362382A
JPS6362382A JP20817186A JP20817186A JPS6362382A JP S6362382 A JPS6362382 A JP S6362382A JP 20817186 A JP20817186 A JP 20817186A JP 20817186 A JP20817186 A JP 20817186A JP S6362382 A JPS6362382 A JP S6362382A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
region
gate
insulating film
formed
floating gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20817186A
Inventor
Susumu Hasunuma
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor

Abstract

PURPOSE:To simplify the process, by performing a forming step of an impurity diffusing region in a region, in which tunnel injection is performed, and a forming step of a thin insulating film region for conducting a tunnel current, in the same patterning. CONSTITUTION:An element region having a first (gate) insulating film 3 and an element isolation insulating region 2 are formed. An opening is provided in the insulating film 3. An impurity diffused region 4, which has a reverse conductivity type with respect to a semiconductor substrate 1, is formed. A second (gate) thin insulating film 5 for conducting a tunnel current is formed on the layer 4. A polycrystalline silicon layer 6 as a floating gate, a third (gate) insulating layer 7 and a polycrystalline silicon layer 8 as a control gate are sequentially formed. A selecting gate 8' and the control gate 8 are patterned. Etching is performed, and source and drain regions 9 are formed in alignment with a gate electrode. A region 10, which injects electrons into the floating gate 6 in a tunnel mode, does not include the end parts of the element isolation insulating film 2. The tunnel injection region 10 is determined by the impurity diffused region 4 and the floating gate 6 in a self-aligning mode.
JP20817186A 1986-09-03 1986-09-03 Floating gate nonvolatile semiconductor storage device and manufacture thereof Pending JPS6362382A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20817186A JPS6362382A (en) 1986-09-03 1986-09-03 Floating gate nonvolatile semiconductor storage device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20817186A JPS6362382A (en) 1986-09-03 1986-09-03 Floating gate nonvolatile semiconductor storage device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6362382A true true JPS6362382A (en) 1988-03-18

Family

ID=16551834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20817186A Pending JPS6362382A (en) 1986-09-03 1986-09-03 Floating gate nonvolatile semiconductor storage device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6362382A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132239A (en) * 1989-09-04 1992-07-21 Sgs-Thomson Microelectronics S.R.L. Process for manufacturing eeprom memory cells having a single level of polysilicon and thin oxide by using differential oxidation
EP0542575A2 (en) * 1991-11-14 1993-05-19 Fujitsu Limited Method for fabricating a semiconductor memory device having a floating gate with improved insulation film quality
US5273923A (en) * 1991-10-09 1993-12-28 Motorola, Inc. Process for fabricating an EEPROM cell having a tunnel opening which overlaps field isolation regions
US5397725A (en) * 1993-10-28 1995-03-14 National Semiconductor Corporation Method of controlling oxide thinning in an EPROM or flash memory array
US5470771A (en) * 1989-04-28 1995-11-28 Nippondenso Co., Ltd. Method of manufacturing a floating gate memory device
US6373093B2 (en) 1989-04-28 2002-04-16 Nippondenso Corporation Semiconductor memory device and method of manufacturing the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6365458B1 (en) 1989-04-28 2002-04-02 Nippondenso Co., Ltd. Semiconductor memory device and method of manufacturing the same
US6373093B2 (en) 1989-04-28 2002-04-16 Nippondenso Corporation Semiconductor memory device and method of manufacturing the same
US6525400B2 (en) 1989-04-28 2003-02-25 Denso Corporation Semiconductor memory device and method of manufacturing the same
US5470771A (en) * 1989-04-28 1995-11-28 Nippondenso Co., Ltd. Method of manufacturing a floating gate memory device
US5132239A (en) * 1989-09-04 1992-07-21 Sgs-Thomson Microelectronics S.R.L. Process for manufacturing eeprom memory cells having a single level of polysilicon and thin oxide by using differential oxidation
US5273923A (en) * 1991-10-09 1993-12-28 Motorola, Inc. Process for fabricating an EEPROM cell having a tunnel opening which overlaps field isolation regions
US5497018A (en) * 1991-11-14 1996-03-05 Fujitsu Limited Semiconductor memory device having a floating gate with improved insulation film quality
EP0542575A2 (en) * 1991-11-14 1993-05-19 Fujitsu Limited Method for fabricating a semiconductor memory device having a floating gate with improved insulation film quality
US5397725A (en) * 1993-10-28 1995-03-14 National Semiconductor Corporation Method of controlling oxide thinning in an EPROM or flash memory array

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