JPH07147327A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To achieve the high integration of a semiconductor device, such as a CMOS-LSI or the like, in which an impurity diffused layer of a first conductivity type and an impurity diffused layer of a second conductivity type are arranged so as to be adjacent by being isolated by an element isolation region. CONSTITUTION:A semiconductor device in which a first impurity diffused layer of a first conductivity type and a second impurity diffused layer of a second conductivity type opposite to the first conductivity type are arranged so as to be adjacent on a semiconductor substrate 34 by being isolated by a LOCOS element isolation region is improved. A well which is formed at the lower part of the first impurity diffused layer is formed in a self-aligned manner with the element isolation region. The well is formed by an oblique ion implantation method. In addition, a well 42b may be constituted of a self-aligned well part 51 and of a non-self-aligned well part 52.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a first conductivity type impurity diffusion layer and a second conductivity type impurity diffusion layer such as a CMOS-LSI. The present invention relates to an improvement in a semiconductor device which is separated by an element isolation region and is arranged in close proximity thereto, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In order to increase the integration degree of a CMOS-LSI, as shown in FIGS. 11A and 11B, a p-type impurity diffusion layer 6 for forming a p-type MOS transistor 2,
The pn distance L with the n-type impurity diffusion layer 8 for forming the n-type MOS transistor 4 may be made as small as possible. Particularly, in a 6-transistor complete CMOS bulk SRAM in which a p-type load transistor is formed on the surface of a semiconductor substrate together with an n-type drive transistor and an n-type select transistor, there is a strong demand for increasing the degree of integration by reducing the pn distance L. .

As shown in FIG. 11, a p-type MOS transistor 2 is formed on the surface of an n-type semiconductor substrate 10 or the surface of an n-type well, and has a p-type impurity diffusion layer 6, a gate insulating layer 12a, and a gate electrode. 14a and. n-type MOS
The transistor 4 is formed on the surface of the p-type well 16 formed on the surface of the semiconductor substrate 10, and has the n-type impurity diffusion layer 8, the gate insulating layer 12b, and the gate electrode 14b. Each element is isolated by an element isolation region (LOCOS) 18 formed by a selective oxidation method.

In this CMOS-LSI, the pn
As shown in FIG. 12, the distance L is equal to the n-type impurity diffusion layer 8
And the breakdown voltage between the n-type semiconductor substrate 10 (corresponding to the distance L ₁ ),
Breakdown voltage between p-type impurity diffusion layer 6 and p-type well 16 (distance L
(Corresponding to ₂ ) and. That is, the distance L
₁ and the distance L ₂ are determined so as to prevent punch-through, and the pn distance L is determined so as to be equal to or more than the sum of the distances L ₁ and L ₂ .

Here, as in the above-mentioned conventional example, a p-type MOS is used.
A method of manufacturing a semiconductor device in which the transistor 2 and the n-type MOS transistor 4 are arranged close to each other will be briefly described. As shown in FIG. 13, an n-type semiconductor substrate 10 is prepared, an oxidation resistant film 20 for forming LOCOS composed of a silicon nitride layer and a silicon oxide layer is formed on the surface thereof, and a mask for ion implantation is formed on the surface thereof. A resist film 22 to be the following is formed. After that, ion implantation for forming the p-type well 16 is performed using the resist film 22 as a mask. A p-type impurity such as boron is used as the impurity at the time of ion implantation.

Next, after removing the resist film 22, another resist film is used as a mask and ion implantation of p-type impurities (for example, boron B ⁺ ) for forming the n-channel stopper region 24 shown in FIG. 14 is performed. Ion implantation of an n-type impurity (for example, phosphorus p ⁺ ) for forming the p channel stopper region 26 is performed. After that, after the annealing treatment, the oxidation resistant film 20 for LOCOS formation (see FIG. 13) is etched with an element isolation pattern, and selective oxidation is performed by using this as an oxidation prevention mask. As shown in FIG. LOCOS) 18 is formed. Then LO
The oxidation resistant film 20 for COS formation is removed.

Next, as shown in FIG. 15, the semiconductor substrate 1
Gate insulating layer 1 composed of a silicon oxide layer on the surface of 0
After forming 2a and 12b, gate electrodes 14a and 14b made of a polysilicon layer are formed. Then, Figure 1
6, the semiconductor substrate 10 other than the p-type well 16
Is masked with a resist film 28, and n-type impurities such as arsenic As ⁺ are selectively ion-implanted into the surface of the p-type well 16 to form an n-type impurity diffusion layer 8. The n-type impurity diffusion layer 8 is formed in self-alignment with the gate electrode 14b and serves as the source / drain region of the n-type MOS transistor.

Next, as shown in FIG. 17, the p-type well 1
The resist film 30 is formed on the surface of the semiconductor substrate 10 on which
Then, p-type impurities such as boron B ⁺ are selectively ion-implanted into the surface of the n-type semiconductor substrate 10 or the surface of the n-well to form the p-type impurity diffusion layer 6. The p-type impurity diffusion layer 6 is formed in self-alignment with the gate electrode 14a and serves as the source / drain region of the p-type MOS transistor.

[0009]

As described above, in a semiconductor device in which the p-type impurity diffusion layer 6 and the n-type impurity diffusion layer 8 are arranged close to each other, the pn distance L shown in FIG. 11 is narrowed. The reason why it is not possible is as follows. First,
As shown in the above-described conventional manufacturing method, the p-type well 16 is formed in a non-self-aligned manner. Second, p
Since the well 16 is formed deeply, it is difficult to control the impurity diffusion laterally.

Next, when manufacturing a semiconductor device in which the p-type impurity diffusion layer 6 and the n-type impurity diffusion layer 8 are arranged close to each other by the conventional manufacturing method, what is the minimum value of the pn distance L? How to decide is explained. 12 and 18
As shown in, the pn distance L is the n ⁺ -n substrate distance L
It is determined to be equal to or more than the sum of ₁ and the p ⁺ -p type well distance L ₂ . The distance L ₁ is equal to the n-type impurity diffusion layer 8 and n.
Basically, it is determined so that punch-through does not occur with the type semiconductor substrate 10, but it is determined by adding a margin dimension in manufacturing described below. The distance L ₂ is basically determined so that punch-through does not occur between the p-type impurity diffusion layer 6 and the p-type well 16. However, the distance L ₂ is determined by adding the following manufacturing margin. It

First, the n ⁺ -n substrate-to-substrate distance L ₁ will be described. Assuming the conventional manufacturing method, the distance L ₁
19 is determined to be equal to or greater than the value obtained by adding the marginal dimensions a, b, and c to the distance d ₁ required to prevent punch-through, as shown in FIG. That is, L ₁ ≧ a
+ B + c + d ₁ . Here, the margin dimension a is an alignment margin dimension between the n ⁺ n-type impurity diffusion layer 8 and the p-type well 16. In addition, the allowance b is determined by the p-type well 16
Is a margin dimension due to variation in the dimension of
Is a marginal dimension due to variations in the n ⁺ n-type impurity diffusion layer 8.

Next, the p ⁺ -p type well distance L ₂ will be described. Assuming the conventional manufacturing method, the distance L ₂
Is determined to be equal to or greater than the value obtained by adding the marginal dimensions a, b, and c to the distance d ₂ required to prevent punch-through, as shown in FIG. That is, L ₂ ≧
a '+ b' is a + c '+ d _1. Here, the margin a '
Is an alignment margin dimension between the p ⁺ p-type impurity diffusion layer 6 and the p-type well 16, and is the same value as the margin dimension a. The margin dimension b ′ is a margin dimension due to variation in the dimensions of the p-type well 16, and is the same as the margin dimension b. Further, the margin dimension c ′ is a margin dimension due to variation of the p ⁺ p-type impurity diffusion layer 6, and the margin dimension c
Is the same value as.

Since the pn distance L is determined to be the sum of the distance L ₁ and the distance L ₂ , L = L ₁ + L ₂
≧ a + b + c + d ₁ + a ′ + b ′ + c ′ + d ₁ = 2 *
(A + b + c) + d ₁ + d ₂ . That is, in the conventional manufacturing method, it is necessary to add a marginal dimension of 2 * (a + b + c) to the minimum distance d ₁ + d ₂ required to prevent punch-through, which hinders high integration.

The present invention has been made in view of the above circumstances, and the first conductivity type impurity diffusion layer and the second conductivity type impurity diffusion layer are separated by an element isolation region, as in a CMOS-LSI or the like. It is an object of the present invention to increase the degree of integration of a semiconductor device that is placed close to the same.

[0015]

In order to achieve the above object, a semiconductor device according to the present invention has a first substrate on a semiconductor substrate.
A first impurity diffusion layer of conductivity type and a second impurity diffusion layer opposite to the first conductivity type
A semiconductor device in which the second conductivity type impurity diffusion layer is separated from each other by an element isolation region and arranged adjacent to each other,
At least a part of the well formed below either the impurity diffusion layer or the second impurity diffusion layer on the adjacent side is formed in a self-aligned manner with respect to the element isolation region.

The element isolation region is composed of a LOCOS or trench type element isolation region formed by a selective oxidation method. The well includes a non-self well portion formed before the formation of the element isolation region, and a self-aligned well portion formed in self-alignment with the element isolation region so as to overlap the non-self well portion. It is preferable that

A method of manufacturing a semiconductor device according to a first aspect of the present invention comprises a step of forming an element isolation region by selective oxidation and an active region surrounded by the element isolation region on a surface of a semiconductor substrate, and a semiconductor. A step of performing oblique ion implantation only in a predetermined active region surrounded by the element isolation region formed on the surface of the substrate, selectively introducing impurities, and forming a well in a self-aligned manner with respect to the element isolation region. , A step of forming a first impurity diffusion layer of a conductivity type opposite to that of the well on the surface of the well, and a step of forming the conductivity of the first impurity diffusion layer on the surface of the active region where the well is not formed. Forming a second impurity diffusion layer of a conductivity type opposite to that of the mold.

A method of manufacturing a semiconductor device according to a second aspect of the present invention comprises a step of forming a trench type element isolation region and an active region surrounded by the trench type element isolation region on the surface of a semiconductor substrate. Ions are implanted only into a predetermined active region surrounded by a trench type element isolation region formed on the surface of a semiconductor substrate to selectively introduce impurities to form a well in a self-aligned manner with respect to the element isolation region. A step of forming a first impurity diffusion layer of a conductivity type opposite to that of the well on the surface of the well, and a step of forming the first impurity diffusion layer on the surface of the active region where the well is not formed. Forming a second impurity diffusion layer having a conductivity type opposite to that of the above.

A method of manufacturing a semiconductor device according to a third aspect of the present invention comprises a step of forming a non-self well portion which becomes a part of a well on the surface of a semiconductor substrate, and a step of forming on the surface of the semiconductor substrate.
A step of forming an element isolation region and an active region surrounded by the element isolation region, and the non-self well part and a part of the non-self well portion only in a predetermined active region surrounded by the element isolation region formed on the surface of the semiconductor substrate. Ions are implanted in an overlapping pattern to selectively introduce impurities to form a self-aligned well portion in a self-aligned manner with respect to the element isolation region. The self-aligned well portion and the non-self well portion form wells. And a step of forming a first impurity diffusion layer of a conductivity type opposite to the conductivity type of the well on the surface of the well, and a step of forming the first impurity diffusion layer on the surface of the active region where the well is not formed. And a step of forming a second impurity diffusion layer having a conductivity type opposite to that of the impurity diffusion layer.

[0020]

In the semiconductor device obtained by the manufacturing method of the present invention,
Since at least a portion of the well formed below either the first impurity diffusion layer or the second impurity diffusion layer is formed in a self-aligned manner with respect to the element isolation region, The alignment margin dimension a with the formed impurity diffusion layer becomes unnecessary. Also, for the same reason,
The margin dimension b based on the variation of the well dimension is also unnecessary.

As a result, the pn distance L between the adjacent first and second impurity diffusion layers is L ≧ 2 * c +.
It is determined so as to satisfy the relationship of d ₁ + d ₂ . here,
d ₁ is the minimum distance required to prevent punch-through between one impurity diffusion layer formed on the well and the semiconductor substrate, and d ₂ is the minimum distance required to prevent punch-through between the other impurity diffusion layer and the well. The required distance, c, is a marginal dimension in consideration of the dimensional variation of the impurity diffusion layer.

Conventionally, the above-mentioned pn distance L is L ≧ 2 *
It was determined to be (a + b + c) + d ₁ + d ₂ . Therefore, according to the present invention, a marginal dimension of 2 * (a + b) is not required, and high integration can be achieved correspondingly. a
= 0.1 μm and b = 0.25 μm, the pn distance L can be shortened by 0.7 μm in the present invention. More specifically, in the semiconductor device manufactured by the conventional method, the minimum pn distance L is about 1.8 μm, whereas in the semiconductor device manufactured by the method of the present invention, the pn distance L is Has a minimum of about 1.1 μm. That is, in the semiconductor device manufactured by the method of the present invention, the inter-pn distance L can be reduced to about 60%.

Particularly, in the semiconductor device manufactured by the manufacturing method according to the third aspect of the present invention, a part of the well located in the vicinity of the first impurity diffusion layer and the second impurity diffusion layer is a self-aligned well. Since the other well portions are formed of relatively deep low-concentration non-self well portions, it is possible to avoid an increase in junction capacitance.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described below in detail with reference to the embodiments shown in the drawings. 1 is a cross-sectional view of an essential part of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of an essential part of a method for manufacturing the semiconductor device shown in FIG. 1, and FIG. 3 is another embodiment of the present invention. 4 is a cross-sectional view of a main part of a semiconductor device, FIG. 4 is a cross-sectional view of a main part of a semiconductor device according to yet another embodiment of the present invention, and FIGS. 5 to 8 are cross-sectional views of a main part showing a manufacturing process of the semiconductor device shown in FIG. FIG. 9 is a plan view of an essential part showing an example of an SRAM in which the structure of the semiconductor device shown in FIG. 4 is adopted, and FIG. 10 is an equivalent circuit diagram of an SRAM memory cell.

As shown in FIG. 1, in a semiconductor device 32 according to one embodiment of the present invention, an element isolation region (LOCOS) 36 formed by selective oxidation is formed on the surface of a semiconductor substrate 34 in an element isolation pattern. . The surface of the semiconductor substrate 34 that is not covered with the element isolation region becomes an active region. In this embodiment, an n-type silicon wafer is used as the semiconductor substrate 32. The LOCOS 36 is composed of a silicon oxide layer obtained by selective oxidation using the silicon nitride layer as a mask. The thickness of the LOCOS 36 is not particularly limited, but is about 300 nm.

In the semiconductor device 32 of this embodiment, since the n ⁺ first impurity diffusion layer 38 and the p ⁺ second impurity diffusion layer 40 are arranged close to each other, the n ⁺ first impurity diffusion layer 38 is formed below the first impurity diffusion layer 38. , P-type well 42 is formed. That is, the n ⁺ first impurity diffusion layer 38 is formed on the surface of the p-type well 42. Moreover, in this embodiment, the p-type well 42 is L
It is formed in self-alignment with the OCOS 36. The p-type well 42 is formed by the oblique ion implantation method described later.

Below the LOCOS 36 located in the vicinity of the p ⁺ second impurity diffusion layer 40, ap channel stopper region 42 into which an n-type impurity is introduced is formed. Also,
Although it is not always necessary because there is a p-type well, the LO located near the n ⁺ first impurity diffusion layer 38 is not necessary.
An n-channel stopper region 44 in which a p-type impurity is introduced may be previously formed under the COS 36.

In the semiconductor device 32 of this embodiment, the p-type well 42 formed below the first impurity diffusion layer 38 is L-shaped.
Since it is formed in self-alignment with OCOS 36,
The alignment margin dimension a between the p-type well 42 and the first impurity diffusion layer 38 formed thereon is unnecessary. Also,
For the same reason, the margin size b based on the variation in the size of the p-type well 42 is also unnecessary.

As a result, the adjacent first impurity diffusion layer 38 is formed.
The inter-pn distance L between the second impurity diffusion layer 40 and L is L ≧
It is determined so as to satisfy the relationship of 2 * c + d ₁ + d ₂ .
Here, d ₁ is the minimum distance required to prevent punch-through between the n ⁺ first impurity diffusion layer 38 formed on the p-type well 42 and the n-type semiconductor substrate, and d ₂ is the p ⁺ The minimum distance required to prevent punch-through between the second impurity diffusion layer 40 and the p-type well 42, c is the first and second impurity diffusion layers 38,
This is a margin dimension in consideration of the dimensional variation of 40.

Conventionally, the above-mentioned pn distance L is L ≧ 2 *
It was determined to be (a + b + c) + d ₁ + d ₂ . Therefore, in the present embodiment, the margin dimension of 2 * (a + b) is not necessary, and the higher integration can be achieved by that amount.
If a = 0.1 μm and b = 0.25 μm, the above-described pn distance L can be shortened by 0.7 μm in this embodiment. More specifically, in the semiconductor device manufactured by the conventional method, the minimum pn distance L is about 1.8 μm, whereas in the semiconductor device 32 of the present embodiment, p
The minimum distance L between n is about 1.1 μm. That is,
In the semiconductor device 32 according to the present embodiment, the inter-pn distance L can be reduced to about 60% as compared with the conventional semiconductor device.

Next, a method of manufacturing the semiconductor device 32 according to this embodiment will be described. As shown in FIG. 2, after the LOCOS 36 is formed on the surface of the semiconductor substrate 34 in an element isolation pattern, oblique ion implantation is performed using a resist film having a predetermined pattern as a mask in order to selectively form the p-type well 42. To do. The conditions for the oblique ion implantation are not particularly limited, but, for example, p-type impurities such as boron are used, the implantation angle θ is 45 degrees, and the implantation energy is 100.
Is preferably 2 conditions ^- KeV, a dose of 1 × 10 ¹³ cm. The semiconductor substrate 34 is rotated during the oblique ion implantation. After the ion implantation, annealing treatment is performed.
The annealing condition is not particularly limited, but is preferably a temperature of 900 ° C. for 30 minutes, for example.

From the viewpoint of reducing the distance d ₁ for preventing punch through shown in FIG. 1, it is preferable to increase the impurity concentration of the p-type well 42 to form it shallow. Therefore,
In order to suppress the variation in the well size due to diffusion, the diffusion in the depth direction and the lateral direction is controlled by the ion implantation condition and the annealing condition. From such a viewpoint, it is preferable that the ion implantation is high-energy oblique ion implantation with an implantation angle θ of 45 degrees.

In order to prevent punch through shown in FIG.
Distance d₂ In order to reduce ⁺Second impurity diffusion
In the area where the layer 40 is to be formed, phosphorus phos⁺Such
Ion implantation using the n-type impurity (θ = 45 degrees)
Implantation energy of 150 KeV and dose of 5 × 1
0¹²cm^-Even if the n-type well 46 is formed under the condition 2
good.

After the p-type well 42 is formed, a gate insulating layer and a gate electrode are formed on the surface of the semiconductor substrate 34, and then the p-type well 4 is formed by an ion implantation method.
An n + first impurity diffusion layer 38 is formed on the surface of No. 2, and a p ⁺ second impurity diffusion layer 40 is formed on the other portions.

Next, another embodiment of the present invention will be described. In the embodiment shown in FIG. 3, the trench type element isolation region 48 is formed on the surface of the semiconductor substrate 34 with an element isolation pattern, and then the trench type element isolation region 48 is formed by a normal ion implantation method other than oblique ion implantation. To form the p-type well 42a in a self-aligning manner. A resist film 50 is formed on the surface of the active region where the p-type well 42a is not formed, and serves as a mask during ion implantation.

After that, on the surface of the p-type well 42a, n
^{The +} first impurity diffusion layer 38a is formed, and the p ⁺ second impurity diffusion layer 40a is formed in the other portions. In the semiconductor device 32a according to this embodiment, the p-type well 42a can be formed without using oblique ion implantation.

Next, still another embodiment of the present invention will be described. In the embodiment shown in FIG. 4, the p-type well 42
b is composed of a non-self well portion 52 formed before the formation of the LOCOS 36, and a self-aligned well portion 51 formed in self-alignment with the LOCOS 36 so as to overlap the non-self well portion 52. To be done. The self-aligned well portion 51 is the p-type well 42 of the embodiment shown in FIGS.
It is formed in the same manner as. The non-self well portion 52 has a lower impurity concentration and is deeper than the self-aligned well portion 51, and is formed before the formation of the LOCOS 36.

On the surface of the p-type well 42b, the first n ⁺
The impurity diffusion layer 38b is formed, and the p ⁺ second impurity diffusion layer 40b is formed in the other portions. Note that, if necessary, the n-type well 54 may be formed below the p ⁺ second impurity diffusion layer 40b. n-type well 5
LOCOS 3 is formed by, for example, an oblique ion implantation method.
6 is formed in a self-aligned manner.

In the semiconductor device 32b according to this embodiment,
Compared to the semiconductor devices 32 and 32a of the above-described embodiment, the well 42b is not separated by the LOCOS 36 and has a deep well portion with a low impurity concentration, so that it is possible to prevent an increase in junction capacitance. Next, a method of manufacturing the semiconductor device shown in FIG. 4 will be described.

As shown in FIG. 5, the n-type semiconductor substrate 34 is
Prepare and, on its surface, a silicon nitride layer and a silicon oxide layer
And an oxidation resistant film 56 for forming LOCOS is formed.
Form a resist film on the surface of the
To achieve. Then, using the resist film as a mask,
Ion implantation is performed to form the self well portion 52.
Boron B is used as an impurity during ion implantation.⁺P-type such as
Impurities are used. As the ion implantation conditions,
For example, with an injection energy of 300 KeV, 5 × 10 ¹¹cm^-2
Is the condition of the dose amount. Also, after the ion implantation,
The conditions are, for example, 900 ° C. and 30 minutes.
It

After that, as shown in FIG. 6, ion implantation for forming the P channel stopper region 58 is performed. P
The channel stopper region 58 is composed of an n-type impurity diffusion layer. As ion implantation conditions for forming the stopper region 58, phosphorus Phos ⁺ is used, and 40 KeV is used.
Implantation energy, carried out with the dose conditions of 1 × 10 ¹² cm ^-2. The n-channel stopper region formed of the p-type impurity diffusion layer formed under the LOCOS 36 is
Since the self-aligned well portion 51, which will be described later, can also be used, it is not always necessary to form it.

Next, the LOCOS forming oxidation resistant film 56 (see FIG. 5) is etched with an element isolation pattern, and selective oxidation is performed by using this as an oxidation prevention mask to perform LOCOS3.
6 is formed. The conditions for forming the LOCOS 36 are, for example, H ₂ + O ₂ gas, a heating temperature of 950 ° C., and a heating time of 30 minutes. LOCOS3
The film thickness of 6 is, for example, about 300 nm.

Next, as shown in FIG. 7, the p-type well 42
In order to selectively form the self-aligned well portion 51 forming a part of the side adjacent to b, oblique ion implantation is performed using a resist film having a predetermined pattern as a mask. The conditions for the oblique ion implantation are, for example, p-type impurities such as boron B ⁺ , the implantation angle θ is 45 degrees, and the implantation energy is 100.
The conditions are KeV and a dose amount of 1 × 10 ¹³ cm ⁻² . The semiconductor substrate 34 is rotated during the oblique ion implantation. After the ion implantation, annealing treatment is performed. The annealing condition is, for example, a temperature of 900 ° C. for 30 minutes.

In order to prevent punch through shown in FIG.
Distance d₂ In order to reduce ⁺Second impurity diffusion
In the area where the layer is to be formed, phosphorus phos⁺N such as
Diagonal ion implantation (θ = 45 degrees) using a type impurity
Input energy 150 KeV and dose 5 × 10¹²c
m^-The n-type well 54 may be formed under the condition of 2.
Self-alignment as part of the n-type well 54 and p-type well 42b
Even if the well portion 51 is in contact with the lower portion of the LOCOS 36,
good.

After the p-type well 42b is formed, a gate insulating layer and a gate electrode are formed on the surface of the semiconductor substrate 34, and then the p-type well 42b is formed by an ion implantation method as shown in FIG. An n + first impurity diffusion layer 38b is formed on the surface, and ap ⁺ second impurity diffusion layer 40b is formed on the other portion.

An n + first impurity diffusion layer 38b is formed.
As an ion implantation condition for⁺For
Implant energy 10 KeV and dose 5 × 10
¹⁵cm ^-There are two conditions. The annealing conditions are as follows.
The conditions are 1000 ° C. and 10 seconds by RTA. p
Ion implantation for forming the + second impurity diffusion layer 40b
As the entry condition, for example, BF₂ ⁺Using injection energy
Gee 10 KeV and dose 3 × 10¹⁵cm^-2 conditions
Is. The annealing condition may be RTA, for example.
According to the conditions of 1000 ° C. and 10 seconds.

Next, an example of a bulk type complete CMOS-SRAM memory cell in which the structure of the semiconductor device 32b shown in FIG. 4 is adopted will be described with reference to FIGS. As shown in FIG. 10, this memory cell has a pair of drive transistors DQ1 and DQ2 that form a flip-flop circuit, select transistors SQ3 and SQ4 for selecting a memory cell, and load transistors LQ5 and LQ6. The selection transistors SQ3 and SQ4 turn on the transistors according to the gate voltage generated on the word line W, and the information stored in the flip-flop circuit formed by the drive transistors DQ1 and DQ2 is stored in the bit line b and the inverted bit line. It is designed to be sent to b '.

To construct the circuit shown in FIG. 10, FIG.
As shown in FIG. 6, in the memory cell MC, the impurity diffusion layers 64a and 64b are arranged in two columns for each cell, and the gate electrodes 62 are arranged in four columns in the direction orthogonal to the impurity diffusion layers 64a and 64b. is there. Outer two rows of the gate electrodes 62 out of the four rows of the gate electrodes 62 become word lines W1 and W2, and at the intersections of these word lines and the impurity diffusion layer 64,
Select transistors SQ3 and SQ4 are formed. Also,
Central two rows of gate electrodes 62, 62 and impurity diffusion layer 64
Load transistors LQ5 and LQ6 and drive transistors DQ1 and DQ2 are formed at the intersections with. The load transistors LQ5 and LQ6 are formed on the p-type impurity diffusion layer 64b, and the selection transistors SQ3 and SQ4 and the drive transistors DQ1 and DQ2 are formed on the n-type impurity diffusion layer 64a.

These transistors are connected by a first intermediate conductive layer 66, a second intermediate conductive layer 68 and a metal wiring layer 70, which are laminated thereon so as to form the circuit shown in FIG. The metal wiring layer 70 formed of an aluminum wiring layer or the like becomes the bit line b, the inverted bit line b ′, and the power supply line VSS.

As shown in FIG. 9, in this memory cell MC, an n-type impurity diffusion layer 64a and a p-type impurity diffusion layer 64b are provided.
And are placed close to each other, and the distance between them is required to be reduced. Therefore, a bulk type complete CMO as shown in FIG.
A semiconductor device having an S-SRAM memory cell is shown in FIG.
It is preferable to adopt the structure shown in (1) from the viewpoint of reducing the size of the memory cell.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, although the n-type semiconductor substrate is used in the above-described embodiments, the present invention is not limited to this, and the p-type semiconductor substrate is used, and the conductivity types of the well and the impurity diffusion layer are all opposite to each other. The invention can be applied.

[0052]

As described above, according to the semiconductor device obtained by the manufacturing method of the present invention, the pn distance L between the first impurity diffusion layer and the second impurity diffusion layer is significantly reduced. It is possible to achieve high integration of CMOS-LSI. In particular, it is effective in reducing the bulk type complete CMOS-SRAM cell. In addition, ASIC (Apllication Spe
When the SRAM is mounted on the cific IC), the cell size can be reduced without significantly increasing the number of processes.

Further, in the manufacturing method of the present invention, the channel stop step can be omitted, so that the ASIC is SR
When the AM is mounted, the compatibility with the ASIC manufacturing process is good. In particular, in the semiconductor device manufactured by the manufacturing method according to the third aspect of the present invention, a part of the well located in the vicinity of the first impurity diffusion layer and the second impurity diffusion layer is a self-aligned well portion. The other wells are composed of relatively deep low-concentration non-self wells.
An increase in junction capacitance can be avoided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts showing a method for manufacturing the semiconductor device shown in FIG.

FIG. 3 is a cross-sectional view of essential parts of a semiconductor device according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view of essential parts of a semiconductor device according to still another embodiment of the present invention.

FIG. 5 is a sectional view of a key portion showing the manufacturing process of the semiconductor device shown in FIG. 4;

FIG. 6 is a sectional view of a key portion showing a step following that shown in FIG.

FIG. 7 is a sectional view of a key portion showing a step following that shown in FIG. 6.

8 is a sectional view of a key portion showing a step that follows the step shown in FIG. 7.

9 is a main-portion plan view showing an example of an SRAM in which the structure of the semiconductor device shown in FIG. 4 is adopted.

FIG. 10 is an equivalent circuit diagram of an SRAM memory cell.

11A is a plan view of a main part of a CMOS-LSI, and FIG. 11B is a sectional view of FIG.

FIG. 12 is a cross-sectional view of an essential part of FIG. 11 (B).

13 is a sectional view of a key portion showing the manufacturing process of the CMOS-LSI shown in FIG. 11.

FIG. 14 is a sectional view of a key portion showing a step following that shown in FIG.

FIG. 15 is a sectional view of a key portion showing a step following that shown in FIG.

16 is a sectional view of a key portion showing a step following that shown in FIG.

FIG. 17 is a sectional view of a key portion showing a step following that shown in FIG. 16.

FIG. 18 is a schematic diagram showing a conventional problem.

19 (a) and 19 (b) are schematic diagrams showing conventional problems.

[Explanation of symbols]

 32, 32a, 32b ... Semiconductor device 34 ... Semiconductor substrate 36 ... Element isolation region (LOCOS) 38, 38a, 38b ... First impurity diffusion layer 40, 40a, 40b ... Second impurity diffusion layer 42, 42a, 42b ... P type Well 48 ... Trench type element isolation region 51 ... Self-aligned well portion 52 ... Non-self well portion DQ1, DQ2 ... Drive transistor SQ3, SQ4 ... Select transistor LQ5, LQ6 ... Load transistor b ... Bit line b '... Inverted bit line W ... Word line MC ... Memory cell

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/316 9274-4M H01L 21/94 A

Claims (6)

[Claims] 1. A semiconductor substrate having a first conductivity type first impurity diffusion layer and a second conductivity type second impurity diffusion layer opposite to the first conductivity type separated by an element isolation region and adjacent to each other. In the semiconductor device arranged as described above, at least a part of an adjacent side of a well formed below either the first impurity diffusion layer or the second impurity diffusion layer is self-aligned with the element isolation region. The semiconductor device formed on. 2. The semiconductor device according to claim 1, wherein the element isolation region is a trench type element isolation region. 3. The well is formed in self-alignment with the element isolation region so as to overlap the non-self well portion formed before the formation of the element isolation region and the non-self well portion. The semiconductor device according to claim 1, comprising a self-aligned well portion. 4. A step of forming an element isolation region by selective oxidation and an active region surrounded by the element isolation region on a surface of a semiconductor substrate, and a predetermined process surrounded by the element isolation region formed on the surface of the semiconductor substrate. Slanted ion implantation only in the active region of the well, selectively introducing impurities to form a well in a self-aligned manner with respect to the element isolation region, and the well surface opposite to the conductivity type of the well. And forming a second impurity diffusion layer of a conductivity type opposite to the conductivity type of the first impurity diffusion layer on the surface of the active region where the well is not formed. And a method of manufacturing a semiconductor device. 5. A step of forming a trench type element isolation region and an active region surrounded by the trench type element isolation region on the surface of the semiconductor substrate, and a trench type element isolation region formed on the surface of the semiconductor substrate. Ion implantation is performed only in a predetermined active region surrounded by
A step of selectively introducing impurities to form a well in a self-aligned manner with respect to the element isolation region; and forming a first impurity diffusion layer of a conductivity type opposite to that of the well on the surface of the well A method of manufacturing a semiconductor device, comprising: a step of forming a second impurity diffusion layer having a conductivity type opposite to that of the first impurity diffusion layer on a surface of an active region where the well is not formed. 6. A step of forming a non-self well portion which becomes a part of a well on the surface of a semiconductor substrate, and an element isolation region and an active region surrounded by the element isolation region on the surface of the semiconductor substrate. And a predetermined active region surrounded by the element isolation region formed on the surface of the semiconductor substrate by performing ion implantation in a pattern that partially overlaps the non-self well portion and selectively introducing impurities. A step of forming a self-aligned well portion in a self-aligned manner with respect to the element isolation region, and forming a well by the self-aligned well portion and the non-self well portion; and a conductive type of the well on the surface of the well. Forming a first impurity diffusion layer having a conductivity type opposite to that of the first impurity diffusion layer, and forming a second impurity diffusion layer having a conductivity type opposite to the conductivity type of the first impurity diffusion layer on the surface of the active region where the well is not formed. To form The method of manufacturing a semiconductor device having a degree.