JPH06140634A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of lithography steps by introducing first and second impurities having the same electrical conductivity into a MOSFET portion while an EPROM portion of a semiconductor substrate is entirely masked, and by forming source and drain regions which are made of two diffusion layers of the MOSFET having different concentrations of impurities. CONSTITUTION:A first p-type well 2 is created at a first portion 100 of a p-type silicon substrate 1 on which an EPROM is to be disposed, and a second p-type well 3 is created at a second portion 200 on which a peripheral MOSFET for driving the EPROM is to be disposed. A field oxide film 4 for isolating devices is selectively created. A polycrystal silicon layer 9 is deposited over the whole of the field oxide film 4 and a dielectric film 5. A control electrode 13 and source-drain regions 21 of the EPROM are created by a first lithography step. Then, a gate electrode 14 of the MOSFET is created by a second lithography step. Thereby, reduced number of lithography steps leads to the elimination of mask errors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a nonvolatile memory device (hereinafter referred to as EPR).
OM) and an insulated gate field effect transistor (hereinafter referred to as MO) as a peripheral transistor for driving an EPROM.
And a semiconductor integrated circuit device having a SFET).

[0002]

Peripheral MOSFET coexisting with EPROM
In the case of a semiconductor integrated circuit device in which the source and drain regions of the above are formed by a single diffusion layer, the source and drain regions of the EPROM and the source and drain regions of the peripheral MOSFET can have the same structure and impurity concentration. Are simultaneously formed and the manufacturing method thereof is simplified.

However, in recent years, in view of the reliability life of the device, the peripheral MOSFET is an offset type (LDD type) MOSFET or a double diffusion type (DDD) in which a source and drain regions are formed of two diffusion layers having different impurity concentrations. Type) MOSFETs. If the source and drain regions of the EPROM and the peripheral MOSFET are simultaneously formed in such a device, E
The source and drain regions of the PROM also become offset type, for example, and do not function as an EPROM. That is,
Peripheral M to increase resistance to hot electrons
Offset type or double diffusion type MOSFET of OSFET
This structure is contrary to the EPROM which uses hot electrons positively for programming.

Therefore, the formation of the source and drain regions of the EPROM and the formation of the source and drain regions of the peripheral MOSFET must be performed in different steps so that the structure and the impurity concentration are suitable for each.

6 to 7 show a conventional manufacturing method.

First, as shown in FIG. 6A, a first P well 2 is formed in a first portion 100 of the P type silicon substrate 1 forming an EPROM, and a second P well 2 is formed to form a MOSFET.
The second P well 3 is formed in the portion 200, and the field oxide film 4 for element isolation is selectively formed. A first gate insulating film 6 is formed on the first P well 2 of the first portion 100.
Is formed, the first polycrystalline silicon layer 7 containing impurities is selectively formed thereon, the insulating film 8 is formed on the surface of the first polycrystalline silicon layer 7, and the second polycrystalline silicon layer 7 of the second portion 200 of the substrate is formed on the insulating film 8. 2 P
A second polycrystalline silicon layer 9 is formed on the entire surface of the well 3 over the gate insulating film 5.

Next, as shown in FIG. 6B, a first resist pattern 31 is formed by the first lithography, and using this as a mask, the second polycrystalline silicon layer 9, the insulating film 8 and the first polycrystalline silicon layer 9 are formed. The polycrystalline silicon layer 7 is sequentially etched to form the control gate electrode 13, the second gate insulating film 12, and the floating gate electrode 11.

Since the conventional technique follows the method in which all the source and drain regions are a single diffusion layer, that is, the source and drain regions are formed after all the gate electrode structures are formed. As shown in (C), the second
Forming a second resist pattern 32 by lithography and using this as a mask for the second polycrystalline silicon layer 9
Is etched to form the gate electrode 14.

Next, as shown in FIG. 6 (D), a third resist pattern 33 is formed by a third lithography, and, for example, arsenic ions 15 are used with the gate electrode structure of the EPROM including this and the control electrode 13 as a mask. N ⁺ type source / drain regions 21 of the EPROM are formed by activation heat treatment after ion implantation and removal of the third resist pattern 33.

Next, as shown in FIG. 7, a fourth resist pattern 34 is formed by a fourth lithography, and a high-concentration arsenic ion 15 and a low-concentration phosphorus ion 16 are used as a mask with the gate electrode 14 of the MOSFET. By ion implantation and activation heat treatment after removing the fourth resist pattern 34, double diffusion type source / drain regions of the MOSFET are formed from the N ⁺ type diffusion layer 22 of arsenic and the N ⁻ type diffusion layer 23 of phosphorus. Form.

[0011]

As described above, according to the method of the prior art, after the step of FIG.
It is necessary to form a resist pattern by lithography four times until the source and drain regions of M and MOSFET are formed.

Therefore, the manufacturing period becomes long, and the manufacturing yield is greatly affected by the mask alignment error.

[0013]

A feature of the present invention is to provide a source and drain region having a first gate insulating film, a floating gate electrode, a second gate insulating film and a control gate electrode and having a single diffusion layer. A method of manufacturing a semiconductor integrated circuit device, comprising: an EPROM having the same; and a MOSFET having a gate insulating film, a gate electrode, and a MOSFET having a source region and a drain region formed of two diffusion layers having the same conductivity type and different in impurity concentration. A second portion for forming the MOSFET on the semiconductor substrate by forming the first gate insulating film on a first portion forming the EPROM;
The gate insulating film is formed on the first gate insulating film, the first polycrystalline silicon layer is selectively formed on the first gate insulating film, and the insulating film is formed on the surface of the first polycrystalline silicon layer. Then, after a series of steps of forming a second polycrystalline silicon layer over the entire surface from the insulating film to the gate insulating film of the second portion of the semiconductor substrate, the semiconductor substrate is removed by the first mask layer. Patterning is not performed on the second polycrystalline silicon layer on the second portion forming the MOSFET, and the state in which the entire surface of the second portion is covered with the second polycrystalline silicon layer is maintained. , E of the semiconductor substrate
The control gate electrode, the second gate insulating film, and the floating gate electrode are formed by sequentially patterning the second polycrystalline silicon layer, the insulating film, and the first polycrystalline silicon layer on the first portion forming the PROM. The process of forming each,
In a state where the entire surface of the second portion of the semiconductor substrate is covered with the second polycrystalline silicon layer, impurities are introduced by using the control gate electrode as a part of the mask in the first portion of the semiconductor substrate. Forming the source and drain regions, and the second polycrystalline silicon layer on the second portion of the semiconductor substrate with the second mask layer covering the entire surface of the first portion of the semiconductor substrate. And forming a gate electrode of the MOSFET by patterning the first electrode and the second impurity of the same conductivity type by using the gate electrode as a part of the mask while masking the entire surface of the first portion of the semiconductor substrate. Is introduced into the second portion of the semiconductor substrate to form source and drain regions consisting of two diffusion layers having different impurity concentrations in the MOSFET. In a method of manufacturing a semiconductor integrated circuit device having.

[0014]

The present invention will be described below with reference to the drawings.

1 and 2 are sectional views showing a first embodiment of the present invention in the order of steps. First, the intermediate product of FIG. 1A is manufactured in the same manner as that of FIG. 6A described above. That is, the first EPROM for arranging the EPROM of the P-type silicon substrate 1
The first P well 2 is formed in the portion 100 of the
The second P well 3 is formed in the second portion 200 where the peripheral MOSFET for driving the OM is arranged, and the field oxide film 4 for element isolation is selectively formed. First part 10
The first gate insulating film 6 is formed on the first P well 2 of 0, the gate insulating film 5 is formed on the second P well 3 of the second portion 200, and the first P well 2 is formed. A first polycrystalline silicon layer 7 containing impurities is selectively formed on the first gate insulating film 6, and an insulating film 8 is formed on the surface of the first polycrystalline silicon layer 7. A second polycrystalline silicon layer 9 is deposited on the entire surface over the gate insulating film 5 on the portion of the second P well 3. The second polycrystalline silicon layer 9 may be deposited in a state containing impurities, or may be deposited in a non-doped state containing no impurities to form a source / drain region after forming a gate electrode. At this time, N-type or P-type impurities may be introduced, or the impurities may be added and further deposited when the source and drain regions are formed.

Next, as shown in FIG. 1B, a first resist pattern 41, which is a first mask layer, is formed by first lithography, and using this as a mask, an EPROM for a semiconductor substrate is formed. The second polycrystalline silicon layer 9, the insulating film 8 and the first polycrystalline silicon layer 7 on the portion 100 are sequentially etched to form the control gate electrode 13 from the second polycrystalline silicon layer 9 and the insulating film 8 from the insulating film 8. The second gate insulating film 12 and the floating gate electrode 11 are formed from the first polycrystalline silicon layer 7. At this time, the MOSFET on the semiconductor substrate
The second polycrystalline silicon layer 9 on the second portion 200 forming the second polycrystalline silicon layer 9 is not patterned by the first resist pattern 41, and the entire surface of the second portion 200 is covered with the second polycrystalline silicon layer 9. Maintain the condition.

Next, as shown in FIG. 1C, after removing the first resist pattern 41, the gate electrode structure of the EPROM including the control electrode 13 formed from the second polycrystalline silicon layer 9 and the semiconductor. Using the second polycrystalline silicon layer covering the entire surface of the second portion of the substrate as a mask, for example, arsenic ions 15 are accelerated at a voltage of 70 keV and the dose is 5
N ⁺ type source / drain region 2 of EPROM is formed by ion implantation at × 10 ¹⁵ / cm ² and subsequent activation heat treatment.
1 is formed. In this case, after the step of FIG.
After the ion implantation is performed without removing the resist pattern 41, the first resist pattern 41 may be removed and the activation heat treatment may be performed. In any case, E
Lithography for forming the gate electrode structure of the PROM and forming the source and drain regions is performed only once.

Next, as shown in FIG. 1D, a second resist pattern 42, which is a second mask layer, is formed by second lithography, and this is used as a mask to form a second resist pattern 42 on the second portion 200. The polycrystalline silicon layer 9 is etched to form the gate electrode 14 of the MOSFET.

Next, as shown in FIG. 2, after removing the second resist pattern 42, a third resist pattern 43 which is a third mask layer is formed by a third lithography, and this and the gate of the MOSFET are formed. Using the electrode 14 as a mask, arsenic ions 15 are ion-implanted at a high concentration with an acceleration voltage of 70 keV and a dose amount of about 1 × 10 ¹⁵ / cm ² , and phosphorus ions 16 are accelerated with an acceleration voltage of 40 keV and a dose amount of about 1 × 10 ¹⁴ / cm ^2.
Double diffusion of MOSFET from N ⁺ type diffusion layer 22 of arsenic and N ⁻ type diffusion layer 23 of phosphorus by activation heat treatment after removing third resist pattern 43 by ion implantation to a low concentration of cm ^2. Form source and drain regions 24 are formed.

In the above description, the second resist pattern 4 is used.
After removing 2, the third resist pattern 43, which is the third mask layer, is formed by the third lithography. However, without removing the second resist pattern 42, the arsenic in the process of FIG. It can be used as a mask when implanting ions 15 and phosphorus ions 16. However, if the peripheral MOSFET has a CMOS structure as in the second embodiment described later, the EPROM
P-channel MOSFET of CMOS with formation part
Since the formation portion is masked, it is necessary to newly form a third resist pattern as shown in FIG.

As described above, according to the method of the first embodiment, after the same step of FIG. 1A as that of FIG.
Since the resist pattern formation by lithography need only be performed twice or three times until the source and drain regions of the PROM and MOSFET are formed, the manufacturing period is shorter than that of the prior art method that requires four times of lithography. Therefore, the number of photomasks is reduced, and the influence of mask alignment error on the manufacturing yield is reduced.

FIG. 3 shows a modified example of the first embodiment, in which the source and drain regions of the peripheral MOSFET are of offset type.

After the step of FIG. 1D, as shown in FIG. 3A, a third resist pattern 43, which is a third mask layer, is formed by third lithography, and a third resist pattern 43 is formed thereon.
With the arsenic ions 15 of low concentration being ion-implanted by using the gate electrode 14 of the SFET as a mask to remove the third resist pattern 43, the activation heat treatment is performed to remove N by arsenic.
^A- type diffusion layer 52 is formed.

Next, as shown in FIG. 3B, an insulating film, for example, a silicon oxide film is deposited on the entire surface and anisotropic reactive ion etching is performed to form side walls 51 of the silicon oxide film on the side surfaces of the gate electrode 14. Forming the fourth
To form a fourth resist pattern 44 which is a fourth mask layer. And the fourth resist pattern 44, and the gate electrode 14 and the sidewall 51 of high concentration of phosphorus ions 16 are ion-implanted as a mask, the activation heat treatment after removing the fourth resist pattern 44, with phosphorus N ⁺ A type diffusion layer 53 is formed to form an offset source / drain region 54 of the MOSFET together with the N ⁻ type diffusion layer 52.

In this embodiment, a large number of fourth lithography steps are required to make the offset type, but FIG.
In the conventional technology of
When the drain region is adopted, a large amount of fifth lithography is required in order to make the offset type similarly, and thus the present embodiment is still one or two times smaller than that of the conventional technique.

4 and 5 show, as a second embodiment of the present invention, a P-channel MOSFET is formed on the second portion 200 of the semiconductor substrate in addition to the N-channel MOSFET of the first embodiment. The CMOS that has been
This is the case when T is set. 4 and 5, the portions having the same or similar functions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and (A), (B), (C) and (D) in FIG.
Are (A), (B), (C) and (D) of FIG. 1, respectively.
5A corresponds to FIG. 2 and therefore duplicated description will be omitted.

First, in FIG. 4A corresponding to FIG. 1A, the second P well 3 for forming the N channel type MOSFET in the second portion 200 of the P type silicon substrate 1 is formed.
At the same time, an N well 63 for forming a P channel type MOSFET is provided. Further, the contact portion 62 for the first P well 2 is arranged, and the first gate insulating film 6 is formed thereon.
At the same time, a thin silicon oxide film 6'is formed.

In FIG. 4B, which corresponds to the next FIG. 1B, the first resist pattern 41 formed by the first lithography is used as a second resist pattern 41 on the second portion 200 including the N well 63. The crystalline silicon layer 9 is entirely covered, and the contact portion 62 is also covered.

In FIG. 4C corresponding to FIG. 1C, a gate electrode structure including a control electrode 13 of the EPROM,
Arsenic ions 15 are ion-implanted by using the second polycrystalline silicon layer 9 covering the entire surface of the second portion 200 and the contact portion 62 as a mask, and the source / drain regions 21 of the EPROM are formed by subsequent activation heat treatment. Form.

In FIG. 4D, which corresponds to the next FIG. 1D, the second polycrystalline silicon layer 9 on the second portion 200 is masked with the second resist pattern 42 formed by the second lithography. Etching the N channel type MO
P-channel type MO together with the gate electrode 14 of SFET
The gate electrode 64 of the SFET is formed.

In FIG. 5A, which corresponds to the next FIG.
And the N well 63 of the second portion 200 is masked by the third resist pattern 43 formed by the above-mentioned lithography and the N well 63 of the second portion 200 is also ion-implanted. Then, an activating heat treatment is performed after removing the third resist pattern 43, so that 200 second P wells 3 of the second portion are formed.
A double-diffused source / drain region 24 of an N-channel MOSFET is formed in the.

Next, as shown in FIG. 5B, the contact of the first P well 2 of 100 of the first portion is formed by the fourth resist pattern 44 which is the fourth mask layer by the fourth lithography. The entire surface except the portion 62 is masked, and also the second P well 3 of 200 in the second portion is masked, boron ions 17 are ion-implanted, and the fourth resist pattern 44 is removed and then activated. By heat treatment, a P channel MOS is formed in the 200 N wells 63 of the second portion.
A P ⁺ type source / drain region 67 of the FET is formed, and a P ⁺ type contact region 73 is formed in the first P well 2 of the first portion 100.

Next, as shown in FIG. 5C, the thin silicon oxide film 6'formed simultaneously with the first gate insulating film 6 on the P ⁺ type contact region 73 is removed, and the interlayer insulating film 72 is removed.
Then, a contact hole 74 is formed therein, and an aluminum electrode wiring 71 connected to each region through the contact hole 74 is formed.

In the second embodiment, a lot of fourth lithography is required to form the CMOS P-channel MOSFET, but the conventional technique of FIG. 6 also uses the CM.
Similarly, when forming a P-channel MOSFET of OS, a lot of fifth lithography is required,
Even in this embodiment, the lithography is reduced once compared with the conventional technique. Further, also in the conventional techniques of FIGS. 6 and 7, when the structure shown in FIG. 5C is required in the subsequent process, the same process and lithography are added.

[0035]

As described above, according to the present invention, E
A semiconductor integrated circuit device having MOSFETs for driving a PROM and an EPROM can be manufactured with a small number of times of lithography, which shortens the manufacturing period.
The number of types of photomasks is reduced, and adverse effects on the manufacturing yield due to mask alignment errors are reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing the next process of FIG. 1D of the first embodiment of the present invention.

FIG. 3 is an embodiment in which a part of the first embodiment of the present invention is modified, and is a cross-sectional view showing a step subsequent to that of FIG.

FIG. 4 is a sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 5 is a cross-sectional view showing a process subsequent to that of FIG. 4D of the second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a conventional technique in order of steps.

FIG. 7 is a cross-sectional view showing the next step of FIG. 6D of the conventional technique.

[Explanation of symbols]

1 P-type silicon substrate 2 First P-well 3 Second P-well 4 Field oxide film 5 Gate insulating film 6 First gate insulating film 6'Thin silicon oxide film 7 First polycrystalline silicon layer 8 Insulating film 9 Second polycrystalline silicon layer 11 Floating gate electrode 12 Second gate insulating film 13 Control gate electrode 14,64 Gate electrode 15 Arsenic ion 16 Phosphorus ion 17 Boron ion 21 EPROM source / drain region 22,53 N ⁺ type diffusion layer 23,52 N ⁻ type diffusion layer 24,54 MOSFET source / drain regions 31, 32, 33, 41, 42, 43, 44 Resist pattern 62 Contact part 63 N well 71 Aluminum electrode wiring 72 Interlayer insulation film 73 P ⁺ type Contact area 74 Contact hole 100 First part forming EPROM 200 MO A second portion forming the FET

Claims (8)

[Claims] 1. A first gate insulating film, a floating gate electrode,
A non-volatile memory element having a second gate insulating film and a control gate electrode and having source and drain regions formed of a single diffusion layer, and a non-volatile memory element having a gate insulating film and a gate electrode and having different impurity concentrations. A method of manufacturing a semiconductor integrated circuit device, comprising: an insulated gate field effect transistor having a source region and a drain region formed of two diffusion layers, the first gate being formed on a first portion of the semiconductor substrate forming the nonvolatile memory element. An insulating film is formed, the gate insulating film is formed on a second portion of the semiconductor substrate forming the insulated gate field effect transistor, and a first polycrystalline silicon layer is formed on the first gate insulating film. The insulating film is selectively formed, and an insulating film is formed on the surface of the first polycrystalline silicon layer, and a second portion of the semiconductor substrate is formed on the insulating film. After a series of steps of forming a second polycrystalline silicon layer on the entire surface of the gate insulating film, the first mask layer is used to form the insulated gate field effect transistor on the second portion of the semiconductor substrate. The non-volatile memory element of the semiconductor substrate is formed by not patterning the second polycrystalline silicon layer and maintaining the state where the entire surface of the second portion is covered with the second polycrystalline silicon layer. Forming a control gate electrode, a second gate insulating film and a floating gate electrode by sequentially patterning the second polycrystalline silicon layer, the insulating film and the first polycrystalline silicon layer on the first portion. And introducing the impurities with the control gate electrode as a part of a mask in a state where the entire surface of the second portion of the semiconductor substrate is covered with the second polycrystalline silicon layer. Performing a first portion of the plate to form source and drain regions of the non-volatile memory device; and a second mask layer covering the entire first portion of the semiconductor substrate to form a first portion of the semiconductor substrate. Patterning the second polycrystalline silicon layer on the second portion to form a gate electrode of the insulated gate field effect transistor; and the gate electrode with the first portion of the semiconductor substrate entirely masked. With the same conductivity type as a part of the mask
And introducing a second impurity into the second portion of the semiconductor substrate to form a source and drain region composed of two diffusion layers having different impurity concentrations of the insulated gate field effect transistor. Method for manufacturing semiconductor integrated circuit device. 2. The entire mask of the first portion of the semiconductor substrate when introducing the first and second impurities of the same conductivity type into the second portion of the semiconductor substrate is the second mask layer. 2. The process is performed as it is according to claim 1.
A method of manufacturing a semiconductor integrated circuit device according to item 1. 3. The entire mask of the first portion of the semiconductor substrate when introducing the first and second impurities of the same conductivity type into the second portion of the semiconductor substrate is the second mask. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the third mask is formed after the layer is removed. 4. The insulated gate field effect transistor is a CMOS N-channel type transistor, wherein the C
A MOS P-channel transistor is also formed in the second portion of the semiconductor substrate, and the entire surface of the first portion of the semiconductor substrate is masked by the third mask and the second portion of the semiconductor substrate is also masked. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the entire surface of the portion where the CMOS P-channel transistor is formed is also masked. 5. The first, second impurities of the same conductivity type are impurities having different diffusion coefficients, respectively, and claim 1, claim 2, claim 3 or claim 4.
A method of manufacturing a semiconductor integrated circuit device according to item 1. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the first and second impurities of the same conductivity type are arsenic and phosphorus. 7. The method according to claim 1, wherein the first and second impurities of the same conductivity type are both introduced with the side surfaces of the gate electrode being in the same state. A method for manufacturing a semiconductor integrated circuit device according to claim 4, claim 5, or claim 6. 8. The introduction of the first and second impurities of the same conductivity type forms a sidewall on a side surface of the gate electrode after the introduction of the first impurity, and thereafter, the second impurity. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, claim 2, claim 3, claim 4, claim 5, or claim 6, wherein