JPS6043865A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6043865A JPS6043865A JP15265183A JP15265183A JPS6043865A JP S6043865 A JPS6043865 A JP S6043865A JP 15265183 A JP15265183 A JP 15265183A JP 15265183 A JP15265183 A JP 15265183A JP S6043865 A JPS6043865 A JP S6043865A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- gate electrode
- source
- material layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title description 10
- 239000012535 impurity Substances 0.000 claims abstract description 31
- 239000007772 electrode material Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 6
- 229910052785 arsenic Inorganic materials 0.000 abstract description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 35
- 238000001020 plasma etching Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 210000004072 lung Anatomy 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置の製造方法の改良に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to an improvement in a method for manufacturing a semiconductor device.
周知の如く、半導体装置例えばチャネル長１μｍ前後の
ＭＯＳ ＬＳＩは、縮小側に従って開発されつつあるが
、周辺装置との整合をとるためにその電源電圧を低下す
ることは困難である。そのため、微細なＭＯＳ ＬＳＩ
ではソース、ドレイン領域間の電界が非常に大きくシシ
、種々の問題が生じてくる。As is well known, semiconductor devices, such as MOS LSIs with a channel length of about 1 μm, are being developed on the downsizing side, but it is difficult to lower their power supply voltage in order to match with peripheral devices. Therefore, fine MOS LSI
In this case, the electric field between the source and drain regions is extremely large, causing various problems.
このようなことから、最近、ソース、ドレイン領域間の
電界を緩和すべく新しい構造のＭＯ８型半導体装置が提
案されている（例えば、Ｄ＠ｓ１ｇｎａｎｄ Ｃｈａｒ
ａｃｔｅｒｉｓｔｉｃｓ ｏｆ ｔｈｅ Ｌｉｇｈｔｌ
ｙ Ｄｏｐｅｄ Ｄｒａｌｎ−８ｏｕｒｃｅ（ＬＤＤ）
Ｉｎ５ｕｌａｔｅｄ Ｇａｔｅ Ｆｉｅｌｄ−Ｅｆｆ
ｅｃｔ ＴｒａｎｓｌｓｔｏｒｏＩＥＥＥＴＲＡＮＳＡ
ＣＴＩＯＮＳ ＯＮ ＥＬＥＣＴＲＯＮ ＤＥＶＩＣＥ
、 ＶＯＬ、 ＥＤ−２７Ａ８ ＡＵＧＵＳＴ １９８
０ ｐｔａｓ９）。かかる半導体装置では、ゲート電極
近傍のソース、ドレイン領域は不純物濃度が低く、その
他のソース、ドレイン領域は不純物濃度が高くなってお
り、これによりソース、ドレイン領域間の電界を緩和す
ることができる。For this reason, recently, MO8 type semiconductor devices with a new structure have been proposed in order to alleviate the electric field between the source and drain regions (for example, D@s1gnand Char
acteristics of the Lightl
y Doped Draln-8source (LDD)
In5lated Gate Field-Eff
ect TranslstoroIEEEETRANSA
CTIONS ON ELECTRON DEVICE
, VOL, ED-27A8 AUGUST 198
0ptas9). In such a semiconductor device, the source and drain regions near the gate electrode have a low impurity concentration, and the other source and drain regions have a high impurity concentration, thereby making it possible to alleviate the electric field between the source and drain regions.
従来、Ｎ−チャネルＭＯ８型）ランジヌタは、例えば第
１図（８）〜（ｄ） Ｋ示すように製造されている。Conventionally, an N-channel MO8 type lung nut has been manufactured, for example, as shown in FIGS. 1(8) to 1(d)K.
まず、Ｐ型の半導体基板１表面に常法により素子分離領
域２を形成した後、この素子分離領域２で囲まれた島領
域３上にケ゛−ト絶縁膜４を介してダート電極５を形成
する。つづいて、このケ゛−ト電極５をマスクとして島
領域３表面にｎ型不純物をイオン注入し、低濃度で浅い
第１の不純物層６１＋７１を形成する（第１図（、）図
示）。次に、全面にＳ ｓ Ｏ２膜８を堆積させる（第
１図（ｂ）図示）。次いで、このＳ ｉＯ２膜８を例え
ばＲＩＥ （反応性イオンエツチング）により異方性エ
ツチング除去し、前記ゲート絶縁膜４及びゲート電極５
の側壁にのみ５ＩＯ２膜８′を残存させる℃幣〒静勅咽
オ→、更に、この残存５ｔＯ２膜８′及びゲート電極５
をマスクとして前記島領域３表面に再度ｎ型不純物をイ
オン注入し、高濃度で−深い第２の不純物層６２＋７２
を形成する。この結果、一方の第１．、第２の不純物層
６１６！からＮ型のソース領域９が形成され、他方の第
１、第２の不純物層７１＋７１からＮ型のドレイン領域
１０が形成される（第１図（ｃ）図示）。First, an element isolation region 2 is formed on the surface of a P-type semiconductor substrate 1 by a conventional method, and then a dirt electrode 5 is formed on an island region 3 surrounded by this element isolation region 2 via a gate insulating film 4. do. Next, using this gate electrode 5 as a mask, n-type impurity ions are implanted into the surface of the island region 3 to form a shallow first impurity layer 61+71 with a low concentration (as shown in FIG. 1(a)). Next, an S s O2 film 8 is deposited on the entire surface (as shown in FIG. 1(b)). Next, this SiO2 film 8 is removed by anisotropic etching, for example, by RIE (reactive ion etching), and the gate insulating film 4 and gate electrode 5 are removed.
The remaining 5tO2 film 8' and the gate electrode 5
Using as a mask, n-type impurity ions are again implanted into the surface of the island region 3 to form a high concentration and -deep second impurity layer 62+72.
form. As a result, one of the first. , second impurity layer 616! An N-type source region 9 is formed from the first and second impurity layers 71+71, and an N-type drain region 10 is formed from the other first and second impurity layers 71+71 (as shown in FIG. 1(c)).
以下、常法によｐ１全面に層間絶縁膜１ノを形成した後
、前記ソース、ドレイン領域９，１゜の夫々の一部に対
応する層間絶縁８１１部分にコンタクトホール１２，１
２を開孔し、層間絶縁膜１１土にコンタクトホール１２
，１２を介して前記ソース、ドレイン領域９ 、 Ｊ
ＯＫ夫々接続する取出し電極１３．１３を形成してＮ−
チャネルＭＯ８型トランジスタを製造する（第１図（ｄ
）図示）・
しかしながら、こうしたＬＤＤ構造のＭＯ８型トランジ
スタの製造方法によれは、次に示す欠点を有する。After forming an interlayer insulating film 1 on the entire surface of p1 by a conventional method, contact holes 12 and 1 are formed in the interlayer insulating film 811 corresponding to parts of the source and drain regions 9 and 1°, respectively.
2, and a contact hole 12 is formed in the interlayer insulating film 11.
, 12 through the source and drain regions 9, J
OK, form the extraction electrodes 13 and 13 to be connected respectively and N-
Manufacture a channel MO8 type transistor (Fig. 1(d)
) However, this method of manufacturing an MO8 type transistor having an LDD structure has the following drawbacks.
■ ダート電極５近傍のソース、ドレイン領域９ 、１
０．即ち第１の不純物層６１＋６１は低濃度となってい
るため、抵抗が高く々す、コンタ゛クタンヌの低下を生
じる。■ Source and drain regions 9 and 1 near the dirt electrode 5
0. That is, since the first impurity layer 61+61 has a low concentration, the resistance tends to be high, resulting in a decrease in contact.
■ 第１の不純物層６１．７１の幅は、第１図（ｃ）の
残存５ｌｏ２膜８′の状態で決まり、その残存量は５Ｉ
０２１１臭８が堆積する膜厚に大きく依存するとともに
、ＲＩＥによるエツチング時件に依存する。従って、第
１の不純物層６Ｉ 、７Ｈの幅を正確Ｋ １ｌｒＩＪ御
するととｒｒＪ因離で、素子特性のバラツキを生じる。■ The width of the first impurity layer 61.71 is determined by the state of the remaining 5lo2 film 8' in FIG. 1(c), and the remaining amount is 5I
It depends largely on the film thickness in which the 0211 odor 8 is deposited, and also on the etching time conditions by RIE. Therefore, if the widths of the first impurity layers 6I and 7H are precisely controlled by K1lrIJ, variations in device characteristics will occur due to rrJ.
■ ＲＩＥ Ｋよるエツチング時にソース、ドレイン領
域９．１０カ１に出しているため、そ！しらの領域９，
１ｏの表面にダメージ層が形成され、素子特性が劣化す
る。■ Because it is exposed to the source and drain regions 9.10 and 1 during RIE K etching, it is! Shirano area 9,
A damaged layer is formed on the surface of 1o, deteriorating the device characteristics.
本夕へ明は上記事情に鑑かてなされ／ξもので、ソース
、ドレイン領域間の電界を緩和できるとともに、ケ゛−
ト電極近傍のソース、ドレイン領域の低濃度部分の幅を
微釉Ｉ Ｋ １ｌｔｌＪ却しがっソース、ドレイン領域
表面にダメージ層が形成されるのを回避して素子特性を
良好にし得る半導体装置の製造方法を提供することを目
的とするものである。The proposal for this evening was made in view of the above circumstances, and it is possible to alleviate the electric field between the source and drain regions, and also to
The width of the low-concentration part of the source and drain regions near the electrode is slightly glazed to prevent the formation of a damaged layer on the surface of the source and drain regions, thereby improving the device characteristics of the semiconductor device. The purpose is to provide a manufacturing method.
本発明は、素子分離領域で囲まれた半導体基板の島領域
上に絶縁膜を形成した後、全面に電極材料層を形成し、
この電極側斜層上にマスク材を形成し、このマスク材を
用いて前記電極材料層をエツチング除去して側面に下爪
が９のテーパ部を有する電極材料層ノリーンを形成し、
このパターンをマスクとして前記基板の島・領域表面に
＠１の不純物層を形成し、前記マスク利を用いて前記電
極材料層・リーンのテーパ部を除去しケ゛〜ト電極ケ形
成し、前記マスク利もしくはゲート電極を用いて前記島
領域表面に第２の不純物層を形成するこ゛とによって、
既述した目的を達成することを骨子とするものである。In the present invention, after forming an insulating film on an island region of a semiconductor substrate surrounded by an element isolation region, an electrode material layer is formed on the entire surface,
forming a mask material on this electrode side diagonal layer, etching and removing the electrode material layer using this mask material to form an electrode material layer Noreen having a tapered portion with a lower claw of 9 on the side surface;
Using this pattern as a mask, an impurity layer @1 is formed on the surface of the island/region of the substrate, and the tapered portion of the electrode material layer is removed using the mask to form a gate electrode. By forming a second impurity layer on the surface of the island region using a gate electrode,
The main objective is to achieve the objectives mentioned above.
以下、本発明をＮ−チャネルＭＯ８型トランジスタの製
造に適用した場合について第２図（！Ｌ）〜（ｅ）を参
照して説明する。Hereinafter, a case in which the present invention is applied to the manufacture of an N-channel MO8 type transistor will be described with reference to FIGS. 2(!L) to (e).
〔ｌ） まず、Ｐ型の半導体基体としてのｓｉ基板２１
表面に常法により素子分離領域としてのフィールド領域
２２を形成した後、このフィールド領域２２で囲まれた
島領域２３上に一部がダート絶縁膜となる絶縁膜２４を
形成した。つづいて、全面Ｋ例えは多結晶シリコンから
力るゲート電極材料層２５．５１０２膜２６を順次形成
した（第２図（、）図示）。次いで、写真蝕刻技術を用
いてこのＳ’＋ ０２膜２６を後記ダート電極に対応し
た形状に選択的にエツチング除去し、マスク拐としての
Ｓ ｒ ０２膜・ぞターン２６′を形成した。更に、前
記Ｓ ｓ Ｏ２膜・ぐターン２６′ををマスクとして前
記ゲート電極胴材層２’５にテーパエツチングを施した
。このテーパエツチングは、具体的には、プラズマエツ
チング技術により基板２ノが載置された試料台を電界方
向に対して傾けることにより行なった。その結果、側面
に下床がりのチー／４部２７を有するグー）！極材材層
パターン２５′を形成した。しかる後、このノぞターン
２５′をマスクして前記島領域２３表面にｎ型不純物例
えば砒素を加速電圧６０ ｋｓＶ、ドーズ量３ Ｘ １
０ ７ｃｍ”でイオン注入し、高濃度で深い第１の不純
物層２８１．２９． を形成した（第２図（ｂ）図示）
６
〔１１〕 次に、前記ＳｉＯ２膜・臂ターン２６′をマ
スクとして前記電極材料層パターン２５′のチー・９部
２７のみをＲＩＥによυ選択的にエツチング除去し、ダ
ート電極３０を形成した（第２図（、）図示）。[l) First, the Si substrate 21 as a P-type semiconductor substrate
After forming a field region 22 as an element isolation region on the surface by a conventional method, an insulating film 24 having a part as a dirt insulating film was formed on an island region 23 surrounded by this field region 22. Subsequently, gate electrode material layers 25 and 5102 films 26 made of polycrystalline silicon were successively formed on the entire surface (as shown in FIG. 2(a)). Next, this S'+02 film 26 was selectively etched away using a photolithographic technique in a shape corresponding to a dirt electrode described later, to form an Sr02 film groove 26' as a mask strip. Further, taper etching was performed on the gate electrode body layer 2'5 using the S s O2 film/gutter 26' as a mask. Specifically, this taper etching was performed by tilting the sample stage on which the substrate 2 was placed with respect to the direction of the electric field using plasma etching technology. As a result, the side has a lower floor Qi/4 part 27)! A polar material layer pattern 25' was formed. Thereafter, this nozzle turn 25' is masked and an n-type impurity such as arsenic is applied to the surface of the island region 23 at an accelerating voltage of 60 ksV and a dose of 3 x 1.
A deep first impurity layer 281.29. with a high concentration was formed by ion implantation at a depth of 0.7 cm (as shown in FIG. 2(b)).
6 [11] Next, using the SiO2 film/arm turn 26' as a mask, only the Q/9 portion 27 of the electrode material layer pattern 25' was selectively etched away by RIE to form a dart electrode 30. (Illustrated in Figure 2(,)).
つづいて、露出する前記５ＩＯ２膜・９ターン２６′及
び絶縁膜２４を選択的に除去した。なお、残存した絶縁
膜２４′はダート絶縁膜となる。次いで、ゲート電極３
０をマスクとして前記島領域２３表面に再度砒素を加速
電圧３０ｋｅＶ、ドーズ量１×１０ ／ｃｍ２でイオン
注入し、ケ゛−ト電極３１近傍に低濃度で浅い１２の不
純物層２Ｂ２．２９゜を形成した。乙の結果、第１、第
２の不純物層２８１．２８ｇからなるＮ型のソース領域
３ノが形成され、かつ第１、第２の不純物層２８２゜２
９怠からＮ型のドレイン領域３２が形成された（第２図
（ｄ）図示）。以下、常法により、全面に層間絶縁膜３
４を形成した後、前記ソース、ドレイン領域３１．３２
の夫々の一部に対応する層間絶縁膜３３部分にコンタク
トホール３４゜３４を開孔し、眉間絶縁膜３３上にコン
タクトホール３４．３４を介して前記ソース、ドレイン
領域３１．３２に夫々接続する取出し電極３５．３５を
形成してＬＤＤ構造のＮ−チャネルＭＯ８型トランジス
タを製造した（第２図（、）図示）。Subsequently, the exposed 5IO2 film/9 turns 26' and the insulating film 24 were selectively removed. Note that the remaining insulating film 24' becomes a dirt insulating film. Next, gate electrode 3
0 as a mask, arsenic is again implanted into the surface of the island region 23 at an acceleration voltage of 30 keV and a dose of 1×10 /cm 2 to form 12 low concentration and shallow impurity layers 2B2.29° near the gate electrode 31. did. As a result of (B), an N-type source region 3 consisting of the first and second impurity layers 281.28g is formed, and the first and second impurity layers 282.28g are formed.
From this step, an N-type drain region 32 was formed (as shown in FIG. 2(d)). Thereafter, the interlayer insulating film 3 is coated on the entire surface by a conventional method.
After forming the source and drain regions 31 and 32
A contact hole 34.34 is opened in a portion of the interlayer insulating film 33 corresponding to a part of each of the contact holes 34.34 and connected to the source and drain regions 31.32 through the contact holes 34.34 on the glabella insulating film 33, respectively. Extracting electrodes 35 and 35 were formed to manufacture an N-channel MO8 type transistor with an LDD structure (as shown in FIG. 2(, )).
しかして、本発明によれば、ダート電極３０近傍のンー
７、ドレイン領域３１．３２の不純物一度を低く、かつ
その他のソース、ドレイン領域３１ 、３−２の不純物
濃度を高くしたＬＤＤ構造と々っているため、ソース、
ドレイン領域３１．３２間の′電界を緩和することがで
きる。According to the present invention, the LDD structure has a low impurity concentration in the drain regions 31 and 31 near the dirt electrode 30, and a high impurity concentration in the other source and drain regions 31 and 3-2. Source,
The electric field between the drain regions 31 and 32 can be relaxed.
また、５ＩＯ２膜ノやターン２６′をマスクとしてゲー
ト電極材料層２５にプラズマエツチング技術によりテー
パエツチングを施してテーパ部２７を有するケ゛−ト電
極材料層ノ！ターン２５′を形成するため、該パターン
２５′を制御性よく形成でき、該・やターン２５′をマ
スクとして第１の不純物層２８１，２９３ を自己整合
的に形成できる。Further, taper etching is performed on the gate electrode material layer 25 by plasma etching technology using the 5IO2 film and the turn 26' as a mask to form a gate electrode material layer having a tapered portion 27. Since the turn 25' is formed, the pattern 25' can be formed with good controllability, and the first impurity layers 281 and 293 can be formed in a self-aligned manner using the turn 25' as a mask.
一方、次工程で５１０２膜パターン２６′をマスクとし
てゲート電極材料層パターン２５′をエツチング除去し
て自己整合的にゲート電極３ｏを形成でき、更に該ダー
ト電極３０をマスクとして第２の不純物層２Ｂ２，２９
．を自己整合的に形成できる。従って、ゲート電極３ｏ
近傍のソース、ドレイン領域３１．３２の低濃度部分の
幅を微細に制御性よく形成でき、もってコンダクタンス
の低下を極めて小さく抑えられるとともに、素子特性の
バラツキを小さくできる。On the other hand, in the next step, the gate electrode material layer pattern 25' can be etched away using the 5102 film pattern 26' as a mask to form the gate electrode 3o in a self-aligned manner, and the second impurity layer 2B2 can be formed using the dirt electrode 30 as a mask. ,29
．． can be formed in a self-consistent manner. Therefore, the gate electrode 3o
The width of the low concentration portions of the nearby source and drain regions 31 and 32 can be formed finely and with good controllability, thereby suppressing a decrease in conductance to an extremely small level and reducing variations in device characteristics.
更に、ダート電極材料層パターン２５′をＲＩＥにより
エツチング除去してダート電極３ｏを形成する際、基板
２１の島領域２３土に絶縁膜２４が形成されているため
、島領域２３表面にダメージ層が形成されることがなく
、素子特性のバラツキを小さくできる。Further, when removing the dirt electrode material layer pattern 25' by RIE to form the dirt electrode 3o, since the insulating film 24 is formed on the island region 23 of the substrate 21, a damaged layer is formed on the surface of the island region 23. This eliminates the need for formation of oxides, thereby reducing variations in device characteristics.
なお、上記実施例では、ケ゛−ト電極の駒材として多結
晶シリコンを用いたが、これに限らず、例えばＭｏ、Ｗ
等の高融点金属からなる化合物を用いてもよい。In the above embodiment, polycrystalline silicon was used as the piece material of the gate electrode, but the material is not limited to this, and for example, Mo, W, etc.
Compounds made of high melting point metals such as
また、上記実施例では、半導体基体としてｓｉ基板を用
いたが、これに限らず、例えばサファイア青の絶縁性基
板上に半導体層を形成したものを用いてもよい。Further, in the above embodiments, an Si substrate is used as the semiconductor substrate, but the present invention is not limited to this, and, for example, a sapphire blue insulating substrate on which a semiconductor layer is formed may be used.
更に、上記実施例では、Ｎ−チャネルＭＯ８型トランジ
スタに適用した場合について述べたが、これに限らす、
Ｐ−チャネルＭＯ８型トランジスタあるいは６ＭＯ８型
トランジスタ等にも同様に適用できる。Furthermore, in the above embodiment, the case where the present invention is applied to an N-channel MO8 type transistor is described, but the present invention is not limited to this.
The present invention can be similarly applied to a P-channel MO8 type transistor or a 6MO8 type transistor.
以上詳述した如く本発明によれは、ソース、ドレイン領
域間の電界を緩和できるとともに、ダート電極近傍のソ
ース、ドレイン領域の低濃度部分の幅を微細に制御等し
て素子特性を良好にし得るＮ−チャネルＭＯ３型トラン
ジスタ等の半導体装置の製造方法を提供できるものであ
る。As detailed above, according to the present invention, the electric field between the source and drain regions can be relaxed, and the width of the low concentration portion of the source and drain regions near the dirt electrode can be finely controlled, thereby improving device characteristics. A method for manufacturing a semiconductor device such as an N-channel MO3 type transistor can be provided.
第１図（、）〜（ｄ）は従来のＮ−チャネルＭＯ８型ト
ランジヌタの製造方法を工程順に示す断面図、第２図（
、）〜（、）は本発明の一実施例に係るＮ−チャネルＭ
Ｏ８型トランジスタの製造方法を工程順に示す断面図で
ある。
２１・・・Ｓｔ基板（半導体基体）、２２・・・フィー
ルド領域（素子分離領域）、２３・・・島領域、２４・
・・絶縁膜、２４′・・・ゲート絶縁膜（残存絶縁膜）
、２５・・ゲート電極胴材層、２５′・・・り゛−ト電
極材料層ノ４ターン、２６・・・ＳｉＯ２膜、２６′・
・・ｓｔｏ２ｇ−＋ターン（マスク材）、２７・・・チ
ー・ヤ部、２８１．２８ｍ＋２９１．２９１・・・不純
物層、３ｏ・・・ダート電極、３１・・・ソース領域、
３２・・・ドレイン電極、３３・・・層間絶縁膜、３４
・・・コンタクトホール、３５・・・取出し電極。
出願人代理人 弁理士 鈴 江 武 彦第２図
第２図FIGS. 1(a) to (d) are cross-sectional views showing the conventional N-channel MO8 type transistor manufacturing method in order of process, and FIG.
, ) to (, ) are N-channel M according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a method for manufacturing an O8 type transistor in order of steps. 21... St substrate (semiconductor base), 22... field region (element isolation region), 23... island region, 24...
... Insulating film, 24'... Gate insulating film (remaining insulating film)
, 25... Gate electrode body material layer, 25'... 4 turns of straight electrode material layer, 26... SiO2 film, 26'...
... sto2g-+turn (mask material), 27... Chee-ya part, 281.28m+291.291... impurity layer, 3o... dirt electrode, 31... source region,
32... Drain electrode, 33... Interlayer insulating film, 34
...Contact hole, 35...Extraction electrode. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 2
Claims (1)
素子分離領域で囲まれた前記基体の島領域上に絶縁膜を
形成した後、全面にゲート電極材料層を形成する工程と
、このゲート電極材料層上にマスク材を形成する工程と
、このマスク材を用いて前記ダート電極材料層をエツチ
ング除去し、側面に下床がりのチー・９部を有するゲー
ト電極材料／ｆｊ ハターンを形成する工程と、この・
・ター夛り−クとして前記基体の島領域表面に第１の不
純物層を形成する工程と、前記マスク材を用いて前記ゲ
ート電極材料層・ンターンのテーパ部を除去しゲート電
極を形成する工程と、前記マスク材もしくはゲート電極
を用いて前記島領域表面に第２の不純物層を形成する場
とを具備することを特徴とする半導体装−“の製造方法
。a step of forming an element isolation region on the surface of a semiconductor substrate; a step of forming an insulating film on the island region of the substrate surrounded by the element isolation region; and a step of forming a gate electrode material layer on the entire surface; A step of forming a mask material on the material layer, and a step of etching and removing the dirt electrode material layer using this mask material to form a gate electrode material/fj pattern having a bottom-hanging chi-9 part on the side surface. And this...
・A step of forming a first impurity layer on the surface of the island region of the substrate as a tar-rep; and a step of removing the tapered portion of the gate electrode material layer/turn using the mask material to form a gate electrode. and forming a second impurity layer on the surface of the island region using the mask material or the gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15265183A JPS6043865A (en) | 1983-08-22 | 1983-08-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15265183A JPS6043865A (en) | 1983-08-22 | 1983-08-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6043865A true JPS6043865A (en) | 1985-03-08 |
Family
ID=15545078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15265183A Pending JPS6043865A (en) | 1983-08-22 | 1983-08-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6043865A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01251490A (en) * | 1988-03-31 | 1989-10-06 | Shin Etsu Chem Co Ltd | Vibrationproofing rubber material and damping material for optical disk device |
| JPH0534266U (en) * | 1991-10-09 | 1993-05-07 | 三菱自動車工業株式会社 | Door outside handle device |
| US6489402B2 (en) | 1998-07-31 | 2002-12-03 | Yamauchi Corporation | Vibration insulator from partially crosslinked butyl rubber |
-
1983
- 1983-08-22 JP JP15265183A patent/JPS6043865A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01251490A (en) * | 1988-03-31 | 1989-10-06 | Shin Etsu Chem Co Ltd | Vibrationproofing rubber material and damping material for optical disk device |
| JPH0565956B2 (en) * | 1988-03-31 | 1993-09-20 | Shinetsu Chem Ind Co | |
| JPH0534266U (en) * | 1991-10-09 | 1993-05-07 | 三菱自動車工業株式会社 | Door outside handle device |
| US6489402B2 (en) | 1998-07-31 | 2002-12-03 | Yamauchi Corporation | Vibration insulator from partially crosslinked butyl rubber |
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