JPS58131773A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPS58131773A JPS58131773A JP57013260A JP1326082A JPS58131773A JP S58131773 A JPS58131773 A JP S58131773A JP 57013260 A JP57013260 A JP 57013260A JP 1326082 A JP1326082 A JP 1326082A JP S58131773 A JPS58131773 A JP S58131773A
- Authority
- JP
- Japan
- Prior art keywords
- film
- drain
- source
- substrate
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 230000001681 protective effect Effects 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000011347 resin Substances 0.000 abstract description 10
- 229920005989 resin Polymers 0.000 abstract description 10
- 238000009826 distribution Methods 0.000 abstract description 8
- 150000004767 nitrides Chemical class 0.000 abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- 238000002513 implantation Methods 0.000 abstract description 4
- -1 phosphorus ions Chemical class 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 239000005368 silicate glass Substances 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
従来、ＭＯＳトランジスタと呼ばれるものは１第１図（
ａ）に示すように、半導体基板１上に、ゲート絶縁膜７
を介してゲート導体６を形成し、そのゲートの両側にソ
ース・ドレイン２の拡散層を持っている構造を有してい
る。図中、３および５は保護膜、４はソースおよびドレ
イン電極を示す８・そのとき、拡散層の不純物濃度のピ
ークは８１表面近くにある。そのため、ゲート導体６の
寸法が短かくなるにしたがって、ＭＯＳトランジスタの
動作時のドレイン端の電界が非常に大きくなり、１）ソ
ース・ドレイン耐圧、２）ドレイン端に発生するホット
エレクトロンの注入による耐圧低下が大きな問題となる
。素子寸法が小さくなることにより、それに伴なって閾
値電圧ｖｔｈを制御するためにチャネル・インプランテ
ーシ冒ン１０を高濃度にしなければならないので、この
傾向はさらに強くなる。第２図に示すように、実効チャ
ネル長さμｍの素子でホットエレクトロン耐圧は４．５
Ｖ程度に低下するので、この耐圧を上げる必要がある。[Detailed Description of the Invention] Conventionally, what is called a MOS transistor is shown in Fig. 1 (
As shown in a), a gate insulating film 7 is formed on the semiconductor substrate 1.
It has a structure in which a gate conductor 6 is formed through the gate conductor 6, and source/drain 2 diffusion layers are provided on both sides of the gate. In the figure, 3 and 5 indicate protective films, and 4 indicates source and drain electrodes.8 At that time, the peak of the impurity concentration of the diffusion layer is near the surface of 81. Therefore, as the dimensions of the gate conductor 6 become shorter, the electric field at the drain end becomes extremely large during operation of the MOS transistor, resulting in 1) source-drain breakdown voltage, and 2) breakdown voltage due to injection of hot electrons generated at the drain end. The decline is a big problem. This tendency becomes even stronger as device dimensions become smaller, requiring a correspondingly higher concentration of the channel implantation agent 10 to control the threshold voltage vth. As shown in Figure 2, the hot electron breakdown voltage is 4.5 for a device with an effective channel length of μm.
Since the voltage decreases to about V, it is necessary to increase this breakdown voltage.
第２図は実効チャネル長の関数とする耐圧の変化を示し
、図は２１はホットエレクトロン耐圧を示し１２２はド
レイン耐圧を示し、実線が従来のＭＯＳトランジスタの
耐圧を表わし、比較のために後に述べる本発明によるＭ
Ｏ８）ランジスタの耐圧が点線で一緒に記載されている
。Figure 2 shows the change in breakdown voltage as a function of effective channel length, in which 21 indicates the hot electron breakdown voltage, 122 indicates the drain breakdown voltage, and the solid line represents the breakdown voltage of a conventional MOS transistor, which will be discussed later for comparison. M according to the invention
O8) The breakdown voltage of the transistor is also indicated with a dotted line.
本発明の目的は、したがって、素子寸法が小さくても高
い耐圧を有するＭＯ８）ランジスタおよびそれを製造す
るための方法を提供することである。The object of the present invention is therefore to provide an MO8) transistor with a high breakdown voltage even with small component dimensions and a method for manufacturing the same.
上記目的を達成するために、本発明による絶縁効果トラ
ンジスタは、ソースおよびドレインの少なくとも一方の
不純物濃度のピークが半導体基板表面ではなく、基板内
に埋−め込まれていることを要旨とする。In order to achieve the above object, the insulating effect transistor according to the present invention is characterized in that the impurity concentration peak of at least one of the source and drain is not at the surface of the semiconductor substrate but is buried within the substrate.
本発明による絶縁効果トランジスタの製造方法は、半導
体基板表面にゲート酸化膜を形成する工程、上記ゲート
酸化膜上にゲートとなる導体を被着させる工程、上記導
体上にイオン・インプランテーションのストッパとなる
膜を形成する工程、以上のようにして形成された積層膜
を所定のパターンに形成する工程、不純物濃度のピーク
が半導体基板表面ではなく、基板内に埋め込まれるよう
に、所定のパターンに形成されたストッパをマスクとし
て高エネルギのイオンを上記半導体基板表面に打ち込み
、ソース・ドレインを形成する工程九全面を保護膜で被
覆する工程、上記保護膜の所定の位置に孔をあけ、ソー
スおよびドレイン電極を設ける工程を含む。The method for manufacturing an insulation effect transistor according to the present invention includes a step of forming a gate oxide film on the surface of a semiconductor substrate, a step of depositing a conductor to become a gate on the gate oxide film, and a step of depositing an ion implantation stopper on the conductor. A process of forming the laminated film formed in the above manner into a predetermined pattern.A process of forming a laminated film formed as described above into a predetermined pattern so that the peak of impurity concentration is not on the surface of the semiconductor substrate but embedded within the substrate. Using the stopper as a mask, high-energy ions are implanted into the surface of the semiconductor substrate to form sources and drains. 9. A step of covering the entire surface with a protective film. Holes are formed at predetermined positions in the protective film to form sources and drains. The method includes a step of providing an electrode.
本発明により、不純物濃度ピークが８１表面から離れて
基板内に埋め込まれ、ドレイン端がチャネル・インプラ
ンテーションからも離れることになり、そこの電界が著
しく減少し、そのことによって素子の耐圧が改善される
。According to the present invention, the impurity concentration peak is moved away from the 81 surface and buried in the substrate, and the drain end is also moved away from the channel implantation, which significantly reduces the electric field there, thereby improving the breakdown voltage of the device. Ru.
以下に実施例を用いて本発明を一層詳しく説明するがそ
れらは例示に過ぎず、本発明の枠を越えることなく、い
ろいろの改良や変形があり得るこ−とは勿論である。The present invention will be described in more detail below using examples, but these are merely illustrative, and it goes without saying that various improvements and modifications may be made without going beyond the scope of the present invention.
実施例 １
第３図（ａ）に示すように、チャネル・インプランテー
ション１０を有する１００Ω・伽のｐ型Ｓ１基板１上に
、ゲート酸化膜７を２０ｎｍ成長させ、その上に、ＣＶ
Ｄ法により多結晶Ｓ１から成る導体６（メタルシリサイ
ド、純メタルＷまたはＭＯでもよい。）を約３００ ｎ
ｍ堆積する。その導体の上に、イオン・インプランテー
ションのストッパー８になるもの、ここではＳ１窒化膜
２００ ｎｍを堆積する。その上に感光性樹脂膜９を塗
り、写真蝕刻法によりパターンを形成し、下の積層膜７
．６．８を・エツチングし、ゲート部分を形成する。こ
のエツチングには、μ波プラズマエッチを用いた。Example 1 As shown in FIG. 3(a), a gate oxide film 7 of 20 nm is grown on a 100Ω p-type S1 substrate 1 having a channel implant 10, and a CV
A conductor 6 (metal silicide, pure metal W or MO may be used) made of polycrystalline S1 is formed by the D method to a thickness of about 300 nm.
Deposit m. On top of the conductor, a 200 nm thick S1 nitride film, which will become the stopper 8 for ion implantation, is deposited. A photosensitive resin film 9 is applied thereon, a pattern is formed by photolithography, and a laminated film 7 below is formed.
．． 6. Etch 8 to form a gate part. For this etching, μ-wave plasma etching was used.
つぎに感光性樹脂膜を除去し、ウェハ全体を酸化する。Next, the photosensitive resin film is removed and the entire wafer is oxidized.
この実施例では、ゲート導体６として多結晶Ｓ１を用い
たため、酸化することができるが、もしゲート導体とし
て純メタルＭＯまたはＷを用いる場合には、酸化する必
要はない。この時、酸化膜１１が約２０ ｎｍ形成され
た。つぎに、この上か）、第３図（ｂ）に図式的に矢印
で示すように、ソース・ドレイン耐圧を形成するため、
高エネルギのイオン・インプランテーションを行なう。In this embodiment, since polycrystalline S1 is used as the gate conductor 6, it can be oxidized, but if pure metal MO or W is used as the gate conductor, oxidation is not necessary. At this time, the oxide film 11 was formed to a thickness of about 20 nm. Next, as shown schematically by the arrows in FIG. 3(b), in order to form a source/drain breakdown voltage,
Perform high-energy ion implantation.
ここでは１５０ ｋｅＶの燐イオンを打ち込んだ。その
時の形成される不純物濃度分布のピークは、第４図に２
３で示すように、Ｓｉ表面から、約０．２〜０．３μｍ
の距離にあった。Here, 150 keV phosphorus ions were implanted. The peak of the impurity concentration distribution formed at that time is shown in Figure 4.
As shown in 3, about 0.2 to 0.3 μm from the Si surface.
It was at a distance of
つぎに、第３図（Ｃ）に示すように、イオン・インプラ
ンテーションのストン／パー８を除き、ウェハ全体を燐
硅酸ガラスの保護膜３で覆う。その保護膜３に、ソース
・ドレイン部にコンタクトを取るためのフンタクト孔を
あけ、その孔を通して、Ａｓのイオン打込みを行なう。Next, as shown in FIG. 3C, the entire wafer except for the ion implantation stone/par 8 is covered with a protective film 3 of phosphosilicate glass. A hole is made in the protective film 3 to make contact with the source/drain portion, and As ions are implanted through the hole.
その条件は％ ６０ ｋｅＶ５ Ｘ １０１５ｃｒ；”
であった。このときのイオン打込みによって得られる不
純物濃度分布を第４図に２４で示す。勿論１燐のイオン
を打ち込むこともできる。この工程まででできあがった
素子構造は、第３図（ｃ）に示すような断面構造になっ
ている。最後に為第３図（ｄ）に示すようにソースおよ
びドレイン電極４を設ける。The conditions are %60 keV5 x 1015cr;”
Met. The impurity concentration distribution obtained by the ion implantation at this time is shown at 24 in FIG. Of course, it is also possible to implant 1 phosphorus ions. The element structure completed up to this step has a cross-sectional structure as shown in FIG. 3(c). Finally, source and drain electrodes 4 are provided as shown in FIG. 3(d).
以上説明したように、本発明によれば、ドレイン端１５
はチャネル・インプランテーション１０からも離れるこ
とになり、そこの電界は著しく減少し、そのことによっ
て素子の耐圧が向上する。As explained above, according to the present invention, the drain end 15
is also moved away from the channel implant 10, and the electric field there is significantly reduced, thereby improving the breakdown voltage of the device.
以上において、ソース・ドレインは対称的な構造になっ
ているため、多少ソース側のチャネル抵抗が大きくなる
可能性があるので、これを避るためには、第５図（ｂ）
に示すプロセス工程を用いればよい。In the above, since the source and drain have a symmetrical structure, there is a possibility that the channel resistance on the source side becomes somewhat large.
The process steps shown in can be used.
第５図（ａ）までは、前記の第３図（ｂ）までのプロセ
ス工程を用い、つぎに第５図（ｂ）に示すように、感光
性樹脂膜９′をパターン形成する。この場ら
合、ソース部分全体には感光性樹脂膜がかぶさな八
いようにし、また、ドレイン部分は１コンタクト・サイ
ズと同程度の孔をあけるようにする。その後、この感光
性樹脂膜９′をマスクにして、前記と同じ条件でＡ８の
イオン打込みを行なう。このプロセス工程を用いること
により第５図（ｃ）に示すような、片方の拡散層部だけ
埋め込まれたＭＯＳ）ランジスタを形成することができ
た。これによつτ作られた素子の耐圧は、従来型と較べ
て第２図に示す様に約２ｖの耐圧向上を図ることができ
ｂ実施例 ２
第６図（ａ）に示すように、８１基板１上にゲート酸化
膜７′を２０ ｎｍ形成し、その上に８１窒化膜１２を
５０ ｎｍ堆積する。その後、第６図（ａ）に示すよう
にパターニングし、第６図（ｂ）のようにＬＯＣＯ８酸
化を行なった。そのＬＯＯＯ８酸化膜は約０．６μｍで
あった。その後、このＬＯＯＯ８酸化膜をエツチングし
て除去する。その断面図が第６図（Ｃ）である。この状
態で、ドレイン２を形成するため、ＡＥ］のイオン打込
みを６０ｋｅＶ、５Ｘ１０”ｃｒｎ−２の条件で行なう
。そのときの不純物濃度分布を第７図に示す。Up to FIG. 5(a), the process steps up to FIG. 3(b) described above are used, and then, as shown in FIG. 5(b), the photosensitive resin film 9' is patterned. In this case, the entire source portion should not be covered with a photosensitive resin film, and the drain portion should have a hole about the same size as one contact. Thereafter, using this photosensitive resin film 9' as a mask, ion implantation of A8 is performed under the same conditions as above. By using this process step, it was possible to form a MOS transistor in which only one diffusion layer portion was buried, as shown in FIG. 5(c). As a result, the breakdown voltage of the element made with τ can be improved by about 2V compared to the conventional type as shown in Fig. 2.Example 2 As shown in Fig. 6(a), A gate oxide film 7' is formed to a thickness of 20 nm on an 81 substrate 1, and an 81 nitride film 12 is deposited thereon to a thickness of 50 nm. Thereafter, patterning was performed as shown in FIG. 6(a), and LOCO8 oxidation was performed as shown in FIG. 6(b). The LOOO8 oxide film had a thickness of about 0.6 μm. Thereafter, this LOOO8 oxide film is removed by etching. Its cross-sectional view is shown in FIG. 6(C). In this state, in order to form the drain 2, ion implantation using AE is performed under the conditions of 60 keV and 5×10'' crn-2.The impurity concentration distribution at that time is shown in FIG.
その後、第６図（ｄ）に示すように、Ｓｉ基板が見えて
いる所だけに選択的にエピタキシャル成長を行なう。１
３はこのとき得られるエピタキシャル成長層を示す。つ
ぎに８１窒化膜１２と酸化膜７′を一度削除する。その
後、改めて、ゲート酸化膜７を第６図（ｃ）のように約
２０ ｎｍ形成する。その酸化膜７を通して閾値電圧ｖ
ｔｈを制御するために。Thereafter, as shown in FIG. 6(d), epitaxial growth is selectively performed only where the Si substrate is visible. 1
3 shows the epitaxially grown layer obtained at this time. Next, the 81 nitride film 12 and the oxide film 7' are removed once. Thereafter, a gate oxide film 7 is again formed to a thickness of about 20 nm as shown in FIG. 6(c). Threshold voltage v through the oxide film 7
To control th.
チャネルドープ１０を行なう。Channel doping 10 is performed.
つぎに、ゲート・メタル６（または多結晶５１）３００
ｎｍを堆積し、第６図（ｆ）のように形成する。この
場合、実質的チャネルは第６図（ｆ）ノ１４に相当する
ので、ゲート・メタル６の寸法はそれほど小さくする必
要はない。Next, gate metal 6 (or polycrystalline 51) 300
nm is deposited and formed as shown in FIG. 6(f). In this case, since the actual channel corresponds to No. 14 in FIG. 6(f), the dimensions of the gate metal 6 do not need to be so small.
ゲート・メタル６を形成したのち、第６図（ｇ）に示す
ように、感光性樹脂膜９をゲート・メタルノドレイン側
の一部を覆うようにパターニングする。その後、この感
光性樹脂膜９をマスクにしてＡθまたはＰを通常のプロ
セス条件でイオン打込しソース・ドレインを形成する。After forming the gate metal 6, as shown in FIG. 6(g), the photosensitive resin film 9 is patterned to cover a part of the gate metal node side. Thereafter, using this photosensitive resin film 9 as a mask, Aθ or P ions are implanted under normal process conditions to form sources and drains.
この様にして、ドレイン側の拡散層が埋め込まれたＭＯ
Ｓ）ランジスタが形成され、高耐圧化が第２図に示すよ
うに実現された。In this way, the MO with the drain side diffusion layer buried
S) A transistor was formed, and a high breakdown voltage was realized as shown in FIG.
以上説明した通り本発明によれば高い耐圧を有するＭＯ
Ｓ）ランジスタを得ることができる。As explained above, according to the present invention, an MO having a high breakdown voltage
S) A transistor can be obtained.
第１図は従来のＭＯＳ）ランジスタの断面図、第２図は
実効チ、ヤネルと耐圧の間の関係を示す図、第３図は本
発明に、よるＭＯＳ）ランジスタの製造工程を示す断面
図、第４図は第３図に示す装置における不純物濃度分布
を示す図、第５図は他の実施の態様における本発明によ
るＭＯＳ）ランジスタの製造工程を示す断面図、第６図
はさらに他の一つの実施の態様における本発明によるＭ
ＯＳ）ランジスタの製造工程を示す断面図、第７図は第
６図にテす装置における不純物濃度分布を示す図である
。
１°・°半導体基板１２・・・ソース拳ドレイン、３゜
５・・・保護膜、４・・・ソースおよびドレイン電極１
６・・・ゲート導体、７・・・ゲート酸化膜、７′・・
・酸化膜、８・・・ストッパー、９，９′・・・感光性
樹脂膜、１ｏ・・・チャネルＯインプランテーション、
１１・・・酸化膜１２・・・Ｓ１窒化膜、１３・・・エ
ピタキシャル成長層１１４・・・実効チャネル長、１５
・・・ドレイン端、２１・・・従来のＭＯＳ）ランジス
タの耐圧の変化を示す曲線、２２・・・本発明によるＭ
ＯＳ）ランジスタの耐圧の変化を示す曲線、２３・・・
打ち込まれた燐イオン濃度分布を示す曲線、２４・・・
打ち込まれた砒素イオン濃度分布を示す曲線。
代理人弁理士 中 村 純之助
１’１図
１’３図
４−２園
賃効手ａル４ン□１
才３図
（Ｑ）
（ｂ）
才４図
５ｉ ４（ｇ６・う、ｎｖｔ１ｍシ々−第５図
（Ｃ）
オ６区FIG. 1 is a cross-sectional view of a conventional MOS transistor, FIG. 2 is a diagram showing the relationship between effective channel, channel, and withstand voltage, and FIG. 3 is a cross-sectional view showing the manufacturing process of a MOS transistor according to the present invention. , FIG. 4 is a diagram showing the impurity concentration distribution in the device shown in FIG. 3, FIG. 5 is a cross-sectional view showing the manufacturing process of a MOS transistor according to the present invention in another embodiment, and FIG. M according to the invention in one embodiment
FIG. 7 is a cross-sectional view showing the manufacturing process of the OS) transistor, and is a diagram showing the impurity concentration distribution in the device shown in FIG. 6. 1°·°Semiconductor substrate 12...source fist drain, 3°5...protective film, 4...source and drain electrode 1
6...Gate conductor, 7...Gate oxide film, 7'...
・Oxide film, 8...Stopper, 9,9'...Photosensitive resin film, 1o...Channel O implantation,
11... Oxide film 12... S1 nitride film, 13... Epitaxial growth layer 114... Effective channel length, 15
...Drain end, 21...Curve showing changes in breakdown voltage of a conventional MOS transistor, 22...M according to the present invention
OS) Curve showing changes in resistor voltage resistance, 23...
Curve showing the implanted phosphorus ion concentration distribution, 24...
A curve showing the implanted arsenic ion concentration distribution. Representative Patent Attorney Junnosuke Nakamura 1'1 Figure 1'3 Figure 4-2 School fee a4n□1 Age 3 Figure (Q) (b) Age 4 Figure 5i 4 (g6・U, nvt1mshishi) -Figure 5 (C) O 6th ward
Claims (2)
において、ソースおよびドレインの少なくとも一方の不
純物濃度のピークが半導体基板表面ではなく、基板内に
埋め込まれていることを特徴とする半導体装置。(1) A semiconductor device characterized in that, in an insulating effect transistor fabricated on a semiconductor substrate, the impurity concentration peak of at least one of the source and drain is buried in the substrate rather than at the surface of the semiconductor substrate.
上記ゲート酸化膜上にゲートとなる導体を被着させる工
程、上記導体上にイオン・インプランテーシフンのスト
ッパとなる膜を形成する工程、以上のようにして形成さ
れた積層膜を所定のパターンに形成する工程、不純物濃
度のピークが半導体基板表面ではなく、基板内に埋め込
まれるように、所定のパターンに形成されたストッパを
マスクとして高エネルギのイオンを上記半導体基板表面
に打ち込み、ソース・ドレインを形成する工程全面を保
護膜で被覆する工程、上記保護膜の所定の位置に孔をあ
け、ソースおよびドレイン電極を設ける工程を含゛む、
ことを特徴とする半導体装置の製造方法。(2) forming a gate oxide film on the surface of the semiconductor substrate;
A step of depositing a conductor to serve as a gate on the gate oxide film, a step of forming a film to serve as a stopper for ion implantation on the conductor, and a step of forming a laminated film formed in the above manner into a predetermined pattern. High-energy ions are implanted into the surface of the semiconductor substrate using a stopper formed in a predetermined pattern as a mask so that the impurity concentration peak is not at the surface of the semiconductor substrate but buried within the substrate. The process includes the steps of: coating the entire surface with a protective film; forming holes at predetermined positions in the protective film to provide source and drain electrodes;
A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57013260A JPS58131773A (en) | 1982-02-01 | 1982-02-01 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57013260A JPS58131773A (en) | 1982-02-01 | 1982-02-01 | Semiconductor device and its manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58131773A true JPS58131773A (en) | 1983-08-05 |
| JPH05870B2 JPH05870B2 (en) | 1993-01-06 |
Family
ID=11828244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57013260A Granted JPS58131773A (en) | 1982-02-01 | 1982-02-01 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58131773A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61259574A (en) * | 1985-04-12 | 1986-11-17 | ゼネラル・エレクトリツク・カンパニイ | Hybrid extension drain construction for reducing effect of hot electron |
| JP2008235407A (en) * | 2007-03-19 | 2008-10-02 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5315773A (en) * | 1976-07-28 | 1978-02-14 | Hitachi Ltd | Mis type semiconductor device and its production |
| JPS5318982A (en) * | 1976-08-05 | 1978-02-21 | Nec Corp | Insulated gate type semiconductor device |
| JPS5530873A (en) * | 1978-08-28 | 1980-03-04 | Fujitsu Ltd | High withstand field-effect transistor of mis type |
-
1982
- 1982-02-01 JP JP57013260A patent/JPS58131773A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5315773A (en) * | 1976-07-28 | 1978-02-14 | Hitachi Ltd | Mis type semiconductor device and its production |
| JPS5318982A (en) * | 1976-08-05 | 1978-02-21 | Nec Corp | Insulated gate type semiconductor device |
| JPS5530873A (en) * | 1978-08-28 | 1980-03-04 | Fujitsu Ltd | High withstand field-effect transistor of mis type |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61259574A (en) * | 1985-04-12 | 1986-11-17 | ゼネラル・エレクトリツク・カンパニイ | Hybrid extension drain construction for reducing effect of hot electron |
| JP2008235407A (en) * | 2007-03-19 | 2008-10-02 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05870B2 (en) | 1993-01-06 |
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