JP2008235407A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simply and easily realize a structure for reducing an electric field applied to a gate insulating film between a gate electrode and a drain electrode regarding a semiconductor device and a manufacturing method for the semiconductor device. <P>SOLUTION: In the semiconductor device, a plurality of kinds of digital transistors and analog transistors are mixed and integrated on the same wafer. The semiconductor device has source impurity-diffusion regions 4 and drain impurity-diffusion regions 5 having different impurity-diffusion profiles. The channel-side end of an LDD region 5A in the impurity-diffusion profile for the drain impurity-diffusion region 5 is isolated from the gate insulating film 2 in the semiconductor device, and the semiconductor device contains a transistor embedded into a substrate. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a high breakdown voltage MOSFET and a method for manufacturing the same.

  Currently, semiconductor devices such as those described above, that is, semiconductor devices in which a plurality of types of MOSFETs are mixedly mounted are widely used, and there is a demand for improvement in performance. However, there are various problems in realizing this.

  In order to operate a power amplifier MOSFET included in such a semiconductor device, a relatively high drain voltage is required. Therefore, the breakdown voltage of the gate insulating film must be increased.

  For example, when a power amplifier MOSFET is mixedly mounted using a process for manufacturing a 3.3V transistor used for I / O, a high drain voltage such as a gate voltage of 3.3V and a drain voltage of 10V is required.

   In a 3.3V I / O transistor, the voltage applied to the gate insulating film is 3.3V between the gate electrode and the source electrode and between the gate electrode and the drain electrode. When the drain voltage is increased to 10V, a voltage difference of 10V occurs between the gate electrode and the drain electrode, and the high electric field causes deterioration and destruction of the gate insulating film.

  It is well known that an asymmetric source / drain structure is useful for improving the drain breakdown voltage. For example, the breakdown voltage is improved by using a relatively low concentration impurity region on the drain side.

  However, a sufficient voltage drop cannot be obtained only by using such a structure, that is, a low-concentration impurity region, and the electric field applied to the gate insulating film between the gate electrode and the drain electrode is hardly relaxed and is insufficient.

  From the above, p-type impurity ions are obliquely implanted from the side, and then n-type impurity ions are implanted from the vertical direction, thereby canceling out impurities in the n-type LDD (lightly doped drain) region. A method of forming a p-type buried region on the channel side at the tip of an n-type LDD region has been disclosed (for example, see Patent Document 1).

  This method improves the breakdown voltage of the element by offsetting impurities in the n-type LDD region with p-type impurities and increasing the LDD resistance.

In this case, the p-type buried region adjacent to the LDD region is characterized in that a structure capable of obtaining the same effect as the well-known pocket implantation is provided only on one side of the gate. However, a problem with analog devices and high-voltage power amplifier MOSFETs is that the p-type buried region, so-called pocket implantation, causes deterioration in drive capability and increased variation.
JP-A-5-275893

  In the present invention, a structure for reducing the electric field applied to the gate insulating film between the gate electrode and the drain electrode is to be realized simply and easily.

  In the semiconductor device and the manufacturing method thereof according to the present invention, a semiconductor device in which a plurality of types of digital transistors and analog transistors are integrated and integrated on the same wafer, and has different impurity diffusion profiles. And a transistor including an impurity diffusion region and a drain impurity diffusion region, and a channel side end in the impurity diffusion profile of the drain impurity diffusion region being separated from the gate insulating film and embedded in the substrate. .

  By adopting the above means, in the source impurity region and the drain impurity diffusion region, the profile in the LDD region on the drain side has a shape in which the tip portion of the LDD region is embedded in the substrate apart from the gate insulating film. Therefore, the electric field applied to the gate insulating film between the gate electrode and the drain electrode can be relaxed, and the gate position can be controlled by controlling the occupation position of the LDD region tip in the drain impurity diffusion region. Both insulation resistance and hot carrier resistance can be improved.

  In the present invention, in order to reduce the electric field applied to the gate insulating film between the gate electrode and the drain electrode, the drain end is separated from the gate insulating film and embedded in the substrate.

  FIG. 1 is a cutaway side view of a main part for explaining a MOSFET which is a semiconductor device according to the first embodiment of the present invention in comparison with a conventional MOSFET. FIG. 1A is a MOSFET according to the present invention. Is a conventional MOSFET.

  In the figure, 1 is a silicon substrate, 1A is a high resistance region, 2 is a gate insulating film, 3 is a gate electrode, 4 is a source impurity diffusion region, 4A is a source side LDD region, 5 is a drain impurity diffusion region, and 5A is Drain side LDD regions 6 are sidewalls. Note that the term LDD is also used for the source side region by convention.

  In the MOSFET according to the present invention, as is apparent from the drawing, the tip portion in the profile of the LDD region 5A is embedded in the substrate 1 and is separated from the gate insulating film 2. Be taken care of. The position at which the tip of the LDD region 5A occupies can be controlled in the manufacturing process, and the gate insulation resistance and hot carrier resistance change according to the occupancy position, so that control is possible. .

  In order to manufacture the MOSFET shown in FIG. 1A, an impurity counter is provided between the drain side LDD region 5A of the drain impurity diffusion region 5 and the gate insulating film 2 in the silicon substrate 1 immediately below the gate electrode 3. The high resistance region 1A is formed by doping.

  In the case of the n-channel type MOSFET, after the n-type LDD region 5A is formed, the LDD region 5A is buried in the substrate 1 by implanting p-type impurity ions shallowly into the surface thereof.

  Comparing the MOSFET shown in FIG. 1A and the MOSFET shown in FIG. 1B, the structure of the LDD region 5A in the MOSFET according to the present invention is significantly different from the structure of the conventional MOSFET. Can be seen.

  When the n-type impurity ions are implanted in the order of the p-type impurity ions, the p-type impurities are pushed into the substrate by the n-type impurities, so that the bottom of the p-type impurity profile spreads inside the substrate. A method of implanting p-type impurity ions after implanting n-type impurity ions may be employed.

  The implantation of the p-type impurity ions is preferably performed from an oblique direction with a shallow angle in order to suppress channeling, thereby forming the drain side LDD region 5A having the tip embedded in the substrate, and the gate electrode 3 and the drain. It is possible to reduce the electric field applied to the gate insulating film 2 between the electrodes.

  In the case of a p-channel MOSFET, it can be easily imagined that the same method can be used as in the case of the n-channel MOSFET described above.

  Further, according to a known technique (see, for example, Patent Document 1), a channel in which an n-type impurity ion is implanted following the implantation of a p-type impurity ion and the tip of the n-type LDD region is present A method of forming a p-type buried region in the region is employed, and in this case, there is a problem that the driving capability of the MOSFET is deteriorated or varies as described above, which is obtained by the present invention. The effect cannot be obtained.

In the second embodiment according to the present invention, instead of the counter-doping of the p-type impurity in the first embodiment described above, the high resistance region 1A is formed by shallowly implanting oxygen ions into the drain region. To form. However, if an excessive amount of oxygen ions is implanted, an oxide film having a reduced withstand voltage is generated due to ion implantation damage, so the dose amount of oxygen ions should be 1 × 10 ¹⁶ cm ⁻² or less. Is preferred.

  FIGS. 2 to 9 are side sectional views showing the main part of the MOSFET in the process steps for explaining the first embodiment of the present invention. The following description will be made with reference to these drawings. It should be noted that parts designated by the same symbols as those used in FIG. 1 represent identical or equivalent parts.

See Fig. 2 (1)
An element isolation region (not shown: located outside the range that can be shown) is formed on the silicon substrate 1 using an STI (shallow trench isolation) method, and then a p-type well region (not shown) is used using an ion implantation method. ). The STI method may be replaced with a LOCOS (local oxidation of silicon) method or the like.

(2)
A gate insulating film 2 made of SiO ₂ having a thickness of 3 nm is formed on the silicon substrate 1 by using a thermal oxidation method. The thickness of the gate insulating film 2 may be arbitrarily selected within the range of 3 nm to 10 nm.

(3)
Similarly, a polysilicon layer having a thickness of 30 nm to be a gate electrode is formed on the gate insulating film 2 by using the CVD method. The thickness of the polysilicon layer to be the gate electrode can be arbitrarily selected within the range of 30 nm to 300 nm, and the material can be selected from silicide, metal, etc. in addition to polysilicon.

See Fig. 3 (4)
Using a resist process in lithographic technology and a reactive ion etching (RIE) method, a polysilicon layer to be a gate electrode is patterned to form a gate electrode 3 having a gate length of 0.1 μm. The gate insulating film 2 is patterned. The gate length may be arbitrarily selected within the range of 0.1 μm to 10 μm.

See Fig. 4 (5)
Using an ion implantation method, impurity ions are implanted to form the source side LDD region 4A and the drain side LDD region 5A. Here, since the n-channel MOSFET is targeted, the impurity is selected from P, As, Sb, etc., and the ion implantation angle is selected in the range of 0 degrees (perpendicular to the substrate surface) to 30 degrees. Further, it is desirable that the ion acceleration energy is 100 keV or less and the dose is 1 × 10 ¹⁵ cm ⁻² or less.

See FIG. 5 (6)
Here, counter-doping is performed obliquely from the side of the LDD region 5A using an ion implantation method. In this case, an impurity having a conductivity type different from that of the LDD region 5A, that is, an n-channel MOSFET, is selected from p-type impurities such as In, B, and BF ₂ .

  At this time, since impurity ions are implanted only into the surface side of the LDD region 5A, a small acceleration energy is employed as compared with the ion implantation when the LDD region is formed, and the ion implantation angle is the same as that when the LDD region is formed. It is necessary to change the ion implantation conditions.

As an example, suppose that the ion implantation at the time of forming the LDD region is in the direction of 0 degree (perpendicular to the substrate surface), the acceleration energy is 30 keV, the ion species is P, and the dose is 1 × 10 ¹⁴ cm ^−2. In the counter dope, the tilt is 0 degree to 30 degrees, preferably 7 degrees, the acceleration energy is 1 keV, the ion species is B, and the dose amount is 8 × 10 ¹³ cm ⁻² .

For the counter-doping, in addition to using impurity ions, oxygen ions are used, and the same method as when impurity ions are used, that is, means for inactivating the surface of the LDD region 5A by implanting from an oblique direction. In that case, by selecting an oxygen ion dose of 1 × 10 ¹⁶ cm ⁻² or less, it is possible to suppress the formation of an oxide film having a reduced breakdown voltage due to ion implantation damage.

See FIG. 6 (7)
A short heat treatment is performed to activate the LDD region. Through this step, the impurities present on the surface of the drain side LDD region 5A are offset by the counter-doped p-type impurities. In the case of oxygen implantation, a high resistance layer is formed by inactivation.

  As a result, a profile in which the LDD region 5A is embedded inside the substrate 1 is generated only on the drain side. The heat treatment in the step (7) may be performed collectively after ion implantation for forming the high concentration source impurity diffusion region 4 and the high concentration drain impurity diffusion region 5 is performed.

Refer to FIG. 7 (8)
A CVD method is employed to deposit an insulating film made of SiO ₂ for the sidewall. Note that SiO ₂ can be replaced with other insulating materials such as SiN, SiON and the like.

(9)
The side wall 6 is formed by employing the RIE method and anisotropically etching the insulating film.

See FIG. 8 (10)
By adopting the ion implantation method, n-type impurity ions are implanted to form the source impurity diffusion region 4 and the drain impurity diffusion region 5.

Refer to FIG. 9 (11) Impurities in the source impurity diffusion region 4 and the drain impurity diffusion region 5 are activated by a short-time heat treatment, thereby realizing the impurity diffusion profile shown in the figure as a whole. Incidentally, the position control of the LDD region 5A of the drain impurity diffusion region 5 is controlled first depending on the impurity implantation of the LDD region 5A, and then counter-doping corresponding to this is performed.

  When the impurity implantation energy of the LDD region 5A is increased or implantation is performed at an angle, the overlap between the gate electrode and the LDD region 5A increases. Of course, although it can be controlled somewhat depending on the counter-doping conditions, the tip of the LDD region 5A is inherently determined by the impurity implantation of the LDD region 5A.

(12)
Thereafter, although not shown in the drawing, as in the manufacture of a normal semiconductor device, formation of a silicide film such as CoSi and NiSi on the surface of the source / drain / gate, deposition of an interlayer insulating film, formation of contact holes and contact plugs, The wiring is completed and completed.

  Since the present invention can be implemented in many forms including the above-described embodiment, it will be exemplified as an additional note hereinafter.

(Appendix 1)
In a field effect transistor comprising a gate electrode formed on a semiconductor substrate via a gate insulating film, a source impurity diffusion region, and a drain impurity diffusion region,
A channel side end of the drain impurity diffusion region is located under the gate insulating film and inside the semiconductor substrate separated from the gate insulating film.

(Appendix 2)
The semiconductor device according to (Appendix 1), wherein the channel-side end portion of the source impurity diffusion region is located under the gate insulating film and in contact with the gate insulating film on the surface portion of the semiconductor substrate.

(Appendix 3)
Forming a gate electrode on a semiconductor substrate via a gate insulating film;
Using the gate electrode and the gate insulating film as a mask, implanting one conductivity type impurity into the semiconductor substrate to form a drain impurity diffusion region;
Next, a method of manufacturing a semiconductor device, comprising: performing an impurity implantation of an opposite conductivity type on the surface of the drain impurity diffusion region from an oblique direction on the drain impurity diffusion region side with respect to the gate electrode. .

(Appendix 4)
Forming a gate electrode on a semiconductor substrate via a gate insulating film;
Using the gate electrode and the gate insulating film as a mask, implanting one conductivity type impurity into the semiconductor substrate to form a drain impurity diffusion region;
And a step of implanting oxygen ions into the surface of the drain impurity diffusion region from an oblique direction on the drain impurity diffusion region side with respect to the gate electrode.

(Appendix 5)
The method of manufacturing a semiconductor device according to (Appendix 3), wherein an implantation amount of the impurity of the opposite conductivity type is 1 × 10 ¹² cm ⁻² or more and 1 × 10 ¹⁶ cm ⁻² or less.

(Appendix 6)
The method for producing a field effect transistor according to (Appendix 4), wherein the oxygen ion implantation amount is 1 × 10 ¹² cm ⁻² or more and 1 × 10 ¹⁶ cm ⁻² or less.

It is a principal part cutting side view for demonstrating the MOSFET which is the semiconductor device of Embodiment 1 according to this invention compared with the conventional MOSFET. It is a principal part cutting side view showing MOSFET in the process important point for demonstrating Example 1 in this invention. It is a principal part cutting side view showing MOSFET in the process important point for demonstrating Example 1 in this invention. It is a principal part cutting side view showing MOSFET in the process important point for demonstrating Example 1 in this invention. It is a principal part cutting side view showing MOSFET in the process important point for demonstrating Example 1 in this invention. It is a principal part cutting side view showing MOSFET in the process important point for demonstrating Example 1 in this invention. It is a principal part cutting side view showing MOSFET in the process important point for demonstrating Example 1 in this invention. It is a principal part cutting side view showing MOSFET in the process important point for demonstrating Example 1 in this invention. It is a principal part cutting side view showing MOSFET in the process important point for demonstrating Example 1 in this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 1A High resistance region 2 Gate insulating film 3 Gate electrode 4 Source impurity diffusion region 4A Source side LDD region 5 Drain impurity diffusion region 5A Drain side LDD region 6 Side wall

Claims (5)

In a field effect transistor comprising a gate electrode formed on a semiconductor substrate via a gate insulating film, a source impurity diffusion region, and a drain impurity diffusion region,
A channel side end of the drain impurity diffusion region is located under the gate insulating film and inside the semiconductor substrate separated from the gate insulating film. 2. The semiconductor device according to claim 1, wherein a channel side end portion of the source impurity diffusion region is located under the gate insulating film and in contact with the gate insulating film on a surface portion of the semiconductor substrate. Forming a gate electrode on a semiconductor substrate via a gate insulating film;
Using the gate electrode and the gate insulating film as a mask, implanting one conductivity type impurity into the semiconductor substrate to form a drain impurity diffusion region;
Next, a method of manufacturing a semiconductor device, comprising: performing an impurity implantation of an opposite conductivity type on the surface of the drain impurity diffusion region from an oblique direction on the drain impurity diffusion region side with respect to the gate electrode. . Forming a gate electrode on a semiconductor substrate via a gate insulating film;
Using the gate electrode and the gate insulating film as a mask, implanting one conductivity type impurity into the semiconductor substrate to form a drain impurity diffusion region;
And a step of implanting oxygen ions into the surface of the drain impurity diffusion region from an oblique direction on the drain impurity diffusion region side with respect to the gate electrode. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the ion implantation amount of oxygen is 1 × 10 ¹² cm ⁻² or more and 1 × 10 ¹⁶ cm ⁻² or less.

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