WO2012066695A1

WO2012066695A1 - Semiconductor device and method for manufacturing same

Info

Publication number: WO2012066695A1
Application number: PCT/JP2011/002597
Authority: WO
Inventors: 鐘ヶ江健司
Original assignee: パナソニック株式会社
Priority date: 2010-11-18
Filing date: 2011-05-10
Publication date: 2012-05-24
Also published as: JP2012109425A

Abstract

Disclosed is a semiconductor device which is provided with: a first gate electrode (125) that has a relatively large width in the gate length direction and a second gate electrode (126) that has a relatively small width in the gate length direction, said gate electrodes being formed on a p-type well (102) and extending parallel to each other; an LDD low concentration region (135) that is formed in the p-type well (102) between the first gate electrode (125) and the second gate electrode (126); and LDD medium concentration regions (134) that are formed in the p-type well (102) respectively at positions outside the first gate electrode (125) and the second gate electrode (126). The impurity concentration of the LDD low concentration region (135) is lower than the impurity concentration of the LDD medium concentration regions (134).

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device such as a highly integrated CMIS (Complementary Metal Insulator semiconductor) transistor capable of driving a high voltage in the field of MISFET (Metal Insulator Semiconductor Transistor) and a manufacturing method thereof.

In recent years, with the high integration and miniaturization of semiconductor devices, miniaturization of transistors has been rapidly advanced. With the miniaturization of the transistors, the power supply voltage of the semiconductor integrated circuit device is lowered according to the scaling law. On the other hand, a high-performance LSI (Large Scale Integration) equipped with a high-breakdown voltage transistor is increasing in necessity for applications in the environmental field and in-vehicle field. In order to meet the demands of these markets, there are now fine CMOS (Complementary Metal Oxide Semiconductor) devices, for example, a low voltage driving transistor with a driving voltage of 1.2V and an I / O transistor with a driving voltage of 3.3V. In addition, there is a need for a high voltage transistor that requires a power supply voltage of 5 V, 12 V, 24 V, or higher for driving a power controller, motor controller, LCD, or the like. Development is accelerating.

In order to manufacture these high breakdown voltage transistors, it is necessary to sufficiently increase each breakdown voltage such as the breakdown voltage of the gate insulating film and the breakdown voltage between the source and drain (sustain breakdown voltage). Generally, the breakdown voltage of the gate insulating film is a thick film. Withstand voltage is improved. On the other hand, in order to improve the sustain breakdown voltage, normally, in a MOS transistor, as shown in FIG. 26, a lightly diffused diffusion layer 16 is formed in the drain region 15 near the gate electrode 19 using a resist mask. There is an extended drain type NMOS transistor 1A. Further, as shown in FIG. 27, a drain expansion type NMOS transistor 1B having a PN junction made of an impurity region having a low concentration under the gate electrode 19 has been proposed (see, for example, Patent Document 1). .

The NMOS transistor 1A shown in FIG. 26 is entirely formed in the p-type well region 12 of the semiconductor substrate 11. The source LDD region 14 adjacent to the source region 13 is formed by an n-type LDD (Lightly Doped Drain) implantation method applied to a normal CMOS. The drain LDD region 16 adjacent to the drain region 105 is an extremely lightly doped region having an n-type dopant concentration lower than that of the source LDD region 14.

In the manufacturing method of the NMOS transistor 1 </ b> A, first, the element isolation 17 is selectively formed on the semiconductor substrate 11, and the p-type well region 12 is further formed on the semiconductor substrate 11. Thereafter, a gate insulating film 18 is formed on the main surface of the semiconductor substrate 11, and then a gate electrode 19 is selectively formed on the gate insulating film 18.

Next, by ion implantation, ion implantation is performed on the p-type well region 12 using the gate electrode 19 as a mask to form the drain LDD region 16.

Next, the source LDD region 14 is formed in the p-type well region 12 by the core CMOS n-type LDD implantation method using the gate electrode 19 as a mask. At this time, the drain LDD region 16 previously formed is masked with a first resist mask (not shown).

Next, a silicon oxide film or a silicon nitride film is formed on the main surface of the semiconductor substrate 11 so as to cover the gate electrode 19. Thereafter, anisotropic etching is performed on the formed silicon oxide film or the like with the second resist mask protecting the drain LDD region 16 to form the sidewalls 20 and the silicide blocks 22.

Next, the source region 13 and the drain region 15 are formed in a self-aligned manner on the upper portion of the p-type well region 12 by using the gate electrode 19, the sidewall 20 and the silicide block 22 as a mask by the CMOS n-type source / drain implantation method. To do.

Next, after forming a refractory metal film on the semiconductor substrate 11, heat treatment is performed so that the upper portions of the source region 13 and the drain region 15 and the exposed surface of the gate electrode 19 from the silicide block 22 are respectively formed. The silicide layer 112 is formed in a self-aligned manner.

Thereby, the NMOS transistor 1A having the drain extension region which is the drain LDD region 16 having a very low concentration is formed.

On the other hand, as shown in FIG. 27, in the method of manufacturing the drain extension type NMOS transistor 1B, first, the first element isolation 17 and the second element isolation 25 are selectively formed on the semiconductor substrate 11. Thereafter, the p-type well region 12 and the n-type well are respectively formed on the upper portion of the semiconductor substrate 11 with respect to the regions defined by the resist mask by a twin well implantation method for manufacturing NMOS and PMOS transistors, which are usually applied to CMOS. Region 24 is formed.

Next, a gate insulating film 18 and a gate electrode 19 are sequentially formed on the main surface of the semiconductor substrate 11. At this time, the gate electrode 19 is formed so as to overlap a part of the second element isolation 25.

Next, the source LDD region 14 is formed by implanting impurities into the entire surface of the transistor region by an n-type LDD implantation method applied to a normal CMOS. At this time, the impurity is implanted only into a necessary portion in a self-aligned manner by the gate electrode 19 and the second element isolation 25.

Next, a silicon oxide film or a silicon nitride film is formed on the main surface of the semiconductor substrate 11 so as to cover the gate electrode 19. Thereafter, anisotropic etching is performed on the formed silicon oxide film or the like to form the sidewall 20.

Next, the p-type well region 12 and the n-type well region 24 are formed by the n-type source / drain implantation method of CMOS, using the gate electrode 19 and the sidewall 20, the first element isolation 17 and the second element isolation 25 as a mask. A source region 13 and a drain region 15 are formed in a self-aligned manner on each of the upper portions.

Next, after forming a refractory metal film on the semiconductor substrate 11, heat treatment is performed so that the silicide layer 23 is formed on the source region 13, the drain region 15, and the gate electrode 19 in a self-aligned manner. Form.

Here, the concentration of the p-type well region 12 and the lateral size and concentration of the n-type well region 24 are required to control the breakdown voltage from the drain to the bulk (for example, the breakdown voltage increases as the size increases). In addition, the breakdown voltage increases as the concentration decreases, and the transistor operating characteristics are optimized separately. Thereby, the drain extension type NMOS transistor 1B is connected to the diffusion layers of the source region 13 and the drain region 15 and is doped at a very low concentration immediately below the gate insulating film 18 below the gate electrode 19. By forming the PN junction 26, the breakdown voltage is improved.

JP 2001-168210 A

However, since the drain extension type NMOS transistor 1A shown in FIG. 26 uses a resist mask when masking the drain LDD region 16, the mask boundary 27 and the mask boundary 28 exist. It is necessary to consider. For this reason, it is necessary to keep a predetermined distance from the gate electrode 19 especially at the mask boundary 28 on the drain region 15, and the margin for that tends to cause a variation in sustain breakdown voltage, and the device area increases. Problems arise. In addition, in a pair type transistor having two gate electrodes 19 formed adjacent to each other and using two transistors 1A sharing either one of the source region 13 or the drain region 15 as a differential circuit, If the mask is misaligned in one direction, an asymmetric pair transistor is formed. This asymmetrically formed pair transistor has a problem in that device characteristics deteriorate due to variations in operating characteristics such as drive current.

In addition, although the drain extension type NMOS transistor 1B shown in FIG. 27 can be expected to improve the sustain breakdown voltage, it uses a resist mask to form a low-concentration PN junction 26 formed immediately below the gate insulating film 18. Yes. For this reason, the mask boundary 29 and the mask boundary 30 exist. Therefore, due to misalignment between the p-type well region 12 and the n-type well region 14, the concentration of the PN junction 26 is not constant, resulting in variations in breakdown voltage. In addition, as in the case of the drain extension type NMOS transistor 1A, in the pair type transistor using two transistors 1B sharing either one of the source region 13 or the drain region 15 as a differential circuit, the mask is misaligned. By shifting in one direction, an asymmetric pair transistor is formed. For this reason, there is a problem that operation characteristics such as drive current vary and device performance deteriorates.

In view of the above, the present invention improves the sustain breakdown voltage without increasing the area and manufacturing process by using a transistor with a simple structure, and suppresses variations in the sustain breakdown voltage, and the drain resistance and junction profile after forming the transistor. An object of the present invention is to realize a semiconductor device with a high degree of freedom that can be adjusted.

To achieve the above object, according to the present invention, a semiconductor device is formed in one semiconductor region, extends in parallel with each other, and has a first gate electrode having a relatively large width in the gate length direction and a relatively small first gate electrode. And the impurity concentration of the diffusion layer between the first gate electrode and the second gate electrode in the semiconductor region is different from the diffusion layer outside the first gate electrode and the second gate electrode in the semiconductor region, respectively. The impurity concentration is lower.

Specifically, a semiconductor device according to the present invention includes a first gate electrode formed on a first conductivity type first semiconductor region with a first gate insulating film interposed therebetween, and a first gate electrode formed on the first semiconductor region. A first gate electrode in the first semiconductor region, and a first gate electrode in the first semiconductor region, the first gate electrode being interposed in parallel with the first gate electrode and having a width in the gate length direction smaller than that of the first gate electrode. A first source region including a first impurity of a second conductivity type, a first drain region including a second impurity of a second conductivity type, and a second gate in the first semiconductor region, each formed in a region on both sides of the electrode; A second source region including a second impurity of a second conductivity type and a second drain region including a second impurity of a second conductivity type, which are formed in regions on both sides of the electrode, respectively. The concentration of one impurity is The second impurity concentration is higher than the second impurity concentration in the drain region, the third impurity concentration in the second source region is lower than the fourth impurity concentration in the second drain region, and the second source region is shared with the first drain region. Has been.

According to the semiconductor device of the present invention, the first gate electrode and the second gate electrode are formed in parallel, whereby the first drain region and the second source region between the first gate electrode and the second gate electrode are formed. The amount of impurity implantation can be reduced in a self-aligned manner without using a resist mask. As a result, since mask alignment is not required, there is no variation in sustain breakdown voltage, and an increase in cost due to an increase in device area and an increase in processes can be suppressed.

Also, since the impurity concentration of the first drain region and the second source region between the first gate electrode and the second gate electrode is low, an implantation profile with a gentle electric field can be formed at the end of the first gate electrode. For this reason, since the impact ionization rate can be reduced, it is possible to improve the decrease in the sustain breakdown voltage due to the increase in the substrate potential due to the increase in the substrate leakage current.

In addition, since the effective channel length between the first source region and the first drain region in the first gate electrode can be widened, the influence of the short channel effect can be reduced, so that the transistor region can be reduced and the chip size can be reduced. Can be planned.

Furthermore, since the width, resistance, and electric field of the depletion layer of the first drain region and the second drain region can be adjusted from the outside by applying an appropriate potential to the second gate electrode, the degree of freedom in circuit design is high, and the sustain breakdown voltage In addition to the improvement, the direction and position of the hot carrier can be changed, so that the deterioration of the hot carrier life can be improved.

The semiconductor device of the present invention further includes sidewalls formed on the respective side surfaces of the first gate electrode and the second gate electrode and made of an insulator, and the side surfaces of the first gate electrode and the second gate electrode facing each other. The sidewalls formed above may be in contact with each other.

In the semiconductor device of the present invention, the first source region, the first drain region, the second source region, and the second drain region may have joint surfaces having the same junction depth.

In the semiconductor device of the present invention, the first drain region includes the first impurity and is formed so as to overlap the first gate electrode. The first PN junction by the first impurity, and the second gate from the first PN junction. A second PN junction formed by a second impurity having a concentration higher than that of the first PN junction, and a region from the second PN junction to the second gate electrode side. You may have the 3rd PN junction by a 3rd impurity with a higher density | concentration than a 2nd PN junction.

In the semiconductor device of the present invention, the region of the first source region to which the first impurity is added and the region of the second drain region to which the fourth impurity is added have higher concentrations than the first impurity and the fourth impurity. The region to which the fifth impurity of the second conductivity type is added and the fifth impurity is added may be included in the region to which the first impurity is added and the region to which the fourth impurity is added.

The semiconductor device of the present invention further includes a metal layer formed on the first source region and the second drain region, and the metal layer is not formed on the first drain region and the second source region. Also good.

In the semiconductor device of the present invention, the first gate insulating film is interposed on the first semiconductor region, and the center lines along the gate width direction of the first gate electrode in the first source region are formed symmetrically with respect to each other. A third gate electrode having the same configuration as the first gate electrode, a fourth gate electrode having the same configuration as the second gate electrode, and a region on both sides of the third gate electrode in the first semiconductor region. The fourth source including the third impurity is formed in the third source region including the first impurity, the third drain region including the second impurity, and the regions on both sides of the fourth gate electrode in the first semiconductor region. A fourth drain region including a region and a fourth impurity, wherein the concentration of the first impurity in the third source region is higher than the concentration of the second impurity in the third drain region. In addition, the concentration of the third impurity in the fourth source region is lower than the concentration of the fourth impurity in the fourth drain region, the third source region is shared with the first source region, and the fourth source region is It may be shared with 3 drain regions.

In this way, even in a pair type transistor using adjacent transistors sharing a source region as a differential circuit, the mask is not misaligned, so that there is no deterioration in device performance due to increased characteristic variation.

In the semiconductor device of the present invention, the first gate insulating film is interposed on the first semiconductor region, and the center lines along the gate width direction of the second gate electrode in the second drain region are symmetrical with each other. A fourth gate electrode having the same configuration as the second gate electrode, a third gate electrode having the same configuration as the first gate electrode, and regions on both sides of the third gate electrode in the first semiconductor region; A third source region including the first impurity, a third drain region including the second impurity, and a region on both sides of the fourth gate electrode in the first semiconductor region, respectively, and including the third impurity. And a fourth drain region including a fourth impurity, wherein the concentration of the first impurity in the third source region is the concentration of the second impurity in the third drain region. The concentration of the third impurity in the fourth source region is lower than the concentration of the fourth impurity in the fourth drain region, the fourth drain region is shared with the second drain region, and the fourth source region is , May be shared with the third drain region.

In this way, even in a pair type transistor using adjacent transistors sharing a drain region as a differential circuit, the mask is not misaligned, so that there is no deterioration in device performance due to increased characteristic variation.

In the semiconductor device of the present invention, the first overlap amount of the overlapping portion of the first source region and the first gate electrode is larger than the second overlap amount of the overlapping portion of the first drain region and the second gate electrode. May be.

In the semiconductor device of the present invention, the third overlap amount of the overlapping portion of the second source region and the second gate electrode is greater than the fourth overlap amount of the overlapping portion of the second drain region and the second gate electrode. May be small.

In the semiconductor device of the present invention, the second source region and the second drain region may be in contact with each other and short-circuited at a lower portion of the second gate electrode in the first semiconductor region.

In the semiconductor device of the present invention, the conductivity type of the lower part of the central part of the first gate electrode in the first semiconductor region and the conductivity type of the lower part of the central part of the second gate electrode are opposite to each other. There may be.

In the semiconductor device of the present invention, the distance between the first gate electrode and the second gate electrode is 70% or less of the height of the first gate electrode and the second gate electrode, and the width of the second gate electrode in the gate length direction. May be not less than 1.3 times the height of the first gate electrode and the second gate electrode.

The semiconductor device of the present invention may further include a third gate electrode formed on the second semiconductor region with a second gate insulating film thinner than the first gate insulating film interposed.

In this way, there is no change from the diffusion by the normal MIS structure, and it becomes easy to mix with a logic core transistor driven by a low voltage with a simple structure.

In the method for manufacturing a semiconductor device according to the present invention, the first source region, the first drain region, the second source region, and the second drain region are used as a mask, and the first gate electrode and the second gate electrode are used as masks. Formed by ion implantation.

According to the method of manufacturing a semiconductor device of the present invention, ions are implanted using the first gate electrode and the second gate electrode formed in parallel with each other as a mask so that the first gate electrode and the second gate electrode are interposed. The amount of impurities implanted into the first drain region and the second source region can be reduced in a self-aligned manner without using a resist mask. As a result, since mask alignment becomes unnecessary, there is no variation in sustain breakdown voltage, and an increase in cost due to an increase in device area and process can be suppressed.

According to the semiconductor device and the manufacturing method thereof according to the present invention, the sustain breakdown voltage is improved without increasing the area and the manufacturing process, suppressing the variation in the sustain breakdown voltage, and adjusting the drain resistance and the junction profile after forming the transistor. Thus, a semiconductor device with a high degree of freedom can be realized.

FIG. 1 is a cross-sectional view of a main part showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 3 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 5 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 7A is a diagram showing a range of the maximum tilt angle in which the low concentration LDD region can be formed in the semiconductor device according to the embodiment of the present invention. FIG. 7B is a diagram showing the range of the maximum gate electrode interval in which the low concentration LDD region can be formed in the semiconductor device according to one embodiment of the present invention. FIGS. 8A and 8B are layout diagrams at the time of high breakdown voltage LDD implantation in the semiconductor device according to one embodiment of the present invention. FIG. 9 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 11 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 12 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 13 is a cross-sectional view showing the main part of a paired transistor sharing a source region, which is a semiconductor device according to a first modification of one embodiment of the present invention. FIG. 14 is a cross-sectional view showing a main part of a paired transistor sharing a drain region, which is a semiconductor device according to a second modification of one embodiment of the present invention. FIG. 15 is a schematic cross-sectional view showing each potential of the first gate electrode and the second gate electrode and a depletion layer in the semiconductor device according to the embodiment of the present invention. FIG. 16 is a schematic cross-sectional view showing each potential of the first gate electrode and the second gate electrode and a depletion layer in the semiconductor device according to the embodiment of the present invention. FIG. 17 is a schematic cross-sectional view showing each potential of the first gate electrode and the second gate electrode and a depletion layer in the semiconductor device according to the embodiment of the present invention. FIG. 18 is a schematic cross-sectional view showing each potential of the first gate electrode and the second gate electrode and a depletion layer in the semiconductor device according to the embodiment of the present invention. FIG. 19 is a cross-sectional view showing the main parts of a semiconductor device according to a third modification of one embodiment of the present invention. FIG. 20 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the fourth modification of the embodiment of the present invention. FIG. 21 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the fifth modification of the embodiment of the present invention. FIG. 22 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the fifth modification of the embodiment of the present invention. FIG. 23 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the sixth modification of the embodiment of the present invention. FIG. 24 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the seventh modification of the embodiment of the present invention. FIG. 25 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the seventh modification of the embodiment of the present invention. FIG. 26 is a sectional view showing a semiconductor device according to a first conventional example. FIG. 27 is a sectional view showing a semiconductor device according to a second conventional example.

(One embodiment)
A semiconductor device according to an embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 1, a semiconductor device according to an embodiment includes a high voltage transistor 120 connected to a power supply voltage of 5 V used in a portable device with a high efficiency power supply control function corresponding to environmental protection, for example. A configuration example in which a fine transistor 121 connected to a power supply voltage of 1.2 V and used for high-speed operation is embedded will be described.

In FIG. 1, only the NMIS transistor is shown in the high-voltage transistor 120, but it is obvious that, for example, an NMIS transistor and a PMIS transistor are formed on one semiconductor substrate 101 in order to constitute a CMIS. Therefore, only the NMIS transistor is shown. Similarly, only the NMIS transistor is illustrated in the fine transistor 121, and the PMIS transistor is omitted.

The high breakdown voltage transistor 120 is formed on the p-type well 102 formed on the semiconductor substrate 101 made of, for example, silicon (Si) and on the p-type well 102. The p-type well 102 is partitioned by element isolation 107 made of shallow trench isolation (STI), and a gate insulating film 108 made of, for example, silicon oxide (SiO ₂ ) is formed on the p-type well 102. A first gate electrode 125 and a second gate electrode 126 are formed so as to be interposed and extend in parallel with each other. Here, the width of the first gate electrode 125 in the gate length direction is relatively large, for example, set to about 500 nm to 1000 nm. On the other hand, the width in the gate length direction of the second gate electrode 126 is relatively small, for example, set to about 100 nm to 200 nm. The distance between the first gate electrode 125 and the second gate electrode 126 is set to about 80 nm to 200 nm.

Side walls 110 made of stacked insulating films are formed on both side surfaces of the

gate electrodes

125 and 126 in the gate length direction. The sidewall 110 includes an offset sidewall 145 formed in order from the inside, a sidewall lower layer film 149 having an L-shaped cross section, and a sidewall upper layer film 150. In the present embodiment, the sidewalls 110 formed in the region between the first gate electrode 125 and the second gate electrode 126 are formed in contact with each other.

An n-type LDD medium concentration region 134 is formed in the upper portion of the p-type well 102 and below and on the side of the first gate electrode 125 opposite to the second gate electrode 126. ing. Further, an n-type LDD low concentration region 135 is formed in a region between the first gate electrode 125 and the second gate electrode 126 in the upper part of the p-type well 102, and a region below the second gate electrode 126. An n-type LDD medium concentration region 134 is formed in a side region opposite to the first gate electrode 125. Here, the LDD low-concentration region 135 has an overlapping portion also below the side portion of the first gate electrode 125 on the second gate electrode 126 side. The LDD low concentration region 135 is shared as a drain region for the first gate electrode 125 and a source region for the second gate electrode 126. Further, the diffusion depths of impurities in the LDD medium concentration region 134 and the LDD low concentration region 135 are set to be substantially the same.

In the LDD medium concentration region 134 located on the opposite side of the first gate electrode 125 from the second gate electrode 126, the LDD medium concentration region 134 is located below and on the side of the outer side wall 110 than the LDD medium concentration region 134. A n-type source region 103 having a shallow junction depth and a high concentration is formed. In addition, the LDD medium concentration region 134 located on the opposite side of the first gate electrode 125 with respect to the second gate electrode 126 has an LDD medium concentration region 134 at the lower end portion of the outer side wall 110 and its side region. An n-type drain region 105 having a shallower junction depth and a high concentration is formed.

A silicide layer 112 made of nickel (Ni) or the like is formed on each of the first gate electrode 125, the second gate electrode 126, the source region 103, and the drain region 105.

Note that in the PMIS transistor (not shown), the conductivity types of the source region 103, the drain region 105, the LDD medium concentration region 134, and the LDD low concentration region 135 of the NMIS transistor shown in FIG.

Next, the configuration of the fine transistor 121 will be described.

The fine transistor 121 is formed on a p-type well 122 different from the p-type well 102 formed on the semiconductor substrate 101 and on the p-type well 122. The p-type well 122 is partitioned by an element isolation 107 made of STI, and a third gate electrode 127 is formed on the p-type well 122 with a thin film gate insulating film 124 made of SiO ₂ interposed therebetween. . Here, the width of the third gate electrode 127 in the gate length direction is set to about 50 nm to 100 nm, for example.

Side walls 110 made of laminated insulating films are formed on both side surfaces of the third gate electrode 127 in the gate length direction. The sidewall 110 includes an offset sidewall 145 formed in order from the inside, a sidewall lower layer film 149 having an L-shaped cross section, and a sidewall upper layer film 150.

An n-type extension region 148 is formed in the upper portion of the p-type well 122 and below and on both sides of the third gate electrode 127. A source region 103 and a drain region 105 having a junction depth deeper than that of the extension region 148 and having a high concentration are formed in the region outside each extension region 148 in the upper part of the p-type well 122.

Further, a silicide layer 112 made of Ni or the like is formed on each of the third gate electrode 127, the source region 103, and the drain region 105, respectively.

In the fine transistor 121 as well, the PMIS transistor (not shown) has the p-type conductivity type of the source region 103, drain region 105, and extension region 148 of the NMIS transistor shown in FIG.

As described above, the high breakdown voltage transistor 120 according to the present embodiment includes the first gate electrode 125 having a relatively large width in the gate length direction and the second gate electrode 126 having a relatively small width in parallel. As will be described later, the amount of impurities implanted into the LDD low concentration region 135 formed between the first gate electrode 125 and the second gate electrode 126 can be reduced in a self-aligned manner without using a resist mask. As a result, since mask alignment is not required, there is no variation in sustain breakdown voltage, and an increase in cost due to an increase in device area and an increase in processes can be suppressed.

Also, since the impurity concentration of the LDD low concentration region 135 between the first gate electrode 125 and the second gate electrode 126 is low, an injection profile with a gentle electric field can be realized at the end of the first gate electrode 125. For this reason, since the impact ionization rate can be reduced, it is possible to improve the decrease in the sustain breakdown voltage due to the increase in the substrate potential due to the increase in the substrate leakage current.

In addition, since the effective channel length between the source region 103 and the LDD low concentration region 135 in the first gate electrode 125 can be increased, the influence of the short channel effect can be reduced. As a result, the transistor region can be reduced and the chip can be reduced.

Further, as will be described later, by applying an appropriate potential to the second gate electrode 126, the width, resistance, and electric field of the depletion layers of the LDD medium concentration region 134 and the drain region 105 can be adjusted from the outside. For this reason, the degree of freedom in circuit design is high, and in addition to the improvement of the sustain breakdown voltage, the direction and position of hot carriers can be changed, so that the deterioration of the hot carrier life can be improved.

Further, there is no change from the diffusion method in a normal MIS transistor, the structure is simple, and it is easy to mix with a low-voltage driven logic core transistor such as the fine transistor 121.

(Production method)
Hereinafter, a method of manufacturing the high breakdown voltage transistor 120 and the fine transistor 121 configured as described above will be described with reference to FIGS.

First, as shown in FIG. 2, an element isolation 107 made of STI having a depth of about 300 nm to 400 nm is formed on a semiconductor substrate 101 made of Si. Subsequently, in the NMIS region of the high breakdown voltage transistor 120 in the semiconductor substrate 101, ion energy (acceleration energy) is 180 keV to 230 keV, and a dose amount is about 1 × 10 ¹³ atoms / cm ² to 5 × 10 ¹³ atoms / cm ^2. P-type well 102 is formed by ion implantation of boron (B). On the other hand, phosphorus (P) having an ion energy of 350 keV to 450 keV and a dose of about 2 × 10 ¹² atoms / cm ² to 8 × 10 ¹² atoms / cm ² is ion-implanted into the PMIS region (not shown) of the semiconductor substrate 101. As a result, an n-type well is formed. Although not shown, ion implantation is performed to determine threshold voltages of the NMIS and PMIS high voltage transistors.

Subsequently, boron (B) having an ion energy of 180 keV to 230 keV and a dose of about 1 × 10 ¹³ atoms / cm ² to 5 × 10 ¹³ atoms / cm ² is ion-implanted into the NMIS region of the fine transistor 121. Thus, the p-type well 122 is formed. On the other hand, in the PMIS region (not shown) of the semiconductor substrate 101, phosphorus (P) having an ion energy of 350 keV to 450 keV and a dose of about 0.5 × 10 ¹³ atoms / cm ² to 2 × 10 ¹³ atoms / cm ² is used. By ion implantation, an n-type well is formed. Although not shown, ion implantation is performed to determine threshold voltages of the NMIS and PMIS fine transistors.

Note that the order of the well injection and the threshold injection of the high voltage transistor 120 and the fine transistor 121 is not particularly limited.

Next, as shown in FIG. 3, as the relatively thick gate insulating film 108 of the high breakdown voltage transistor 120 used in the power supply circuit or the like, the SiO 2 having a film thickness of about 15 nm to 20 nm is formed on the entire surface of the semiconductor substrate 101. _Two films are formed. At this time, the SiO ₂ film is a laminated film of an oxide film by a substrate oxidation (thermal oxidation) method and a LP-CVD (Low Pressure-Chemical Vapor Deposition) film or the like, so that an end portion of the element isolation (STI) 107 is obtained. It is possible to relieve stress caused by. Further, the thin gate insulating film 124 of the fine transistor 121 used in the logic transistor or SRAM (Static Random Access Memory) transistor is formed by removing the thick gate insulating film 108 once formed by an oxide film wet etch, On the p-type well 122 and an n-type well (not shown), it is formed by a thin film substrate oxidation method so that the film thickness becomes about 2 nm to 3 nm.

Next, as shown in FIG. 4, a non-doped polysilicon film 109 having a thickness of about 100 nm to 150 nm is deposited on the entire surface of the semiconductor substrate 101. Thereafter, ion implantation is appropriately performed on the NMIS region and PMIS region of the high breakdown voltage transistor 120 and the NMIS region and PMIS region of the fine transistor 121 in the deposited polysilicon film 109 using a resist mask. This suppresses depletion at the interface between the gate insulating film 108 and the thin gate insulating film 124 and the polysilicon film 109 and adjusts the threshold voltage of the transistor, thereby forming a polysilicon gate necessary for the CMIS structure.

Next, as shown in FIG. 5, a gate pattern is formed using a resist mask (not shown). At this time, in the NMIS region of the high breakdown voltage transistor 120, a predetermined interval is provided on the first gate electrode 125 serving as a transistor gate electrode for controlling the driving capability and the threshold voltage, and on the drain electrode 105 side of the first gate electrode 125. The second gate electrode 126 is formed at the same time, and serves as a gate electrode for controlling the drain electrode 105. The first gate electrode 125 and the second gate electrode 126 are disposed in the p-type well 102 that is one active region. In the p-type well 102, the first gate electrode 125 and the second gate electrode 126 are disposed. Are formed in parallel to each other. Similarly, also in the PMIS region (not shown) of the high breakdown voltage transistor 120, the first gate electrode 125 and the second gate electrode 126 are disposed in an n-type well which is one active region, and the first gate electrode 125 and the second gate electrode 126 are within the n-type well. The first gate electrode 125 and the second gate electrode 126 are formed in parallel to each other.

At the same time, a third gate electrode 127 which is a gate electrode for a fine transistor for forming a logic circuit capable of high-speed operation is formed in the NMIS region of the fine transistor 121 by using the same resist mask as that of the high voltage transistor 120. .

Note that the distance between the first gate electrode 125 and the second gate electrode 126 is a value determined in the LDD implantation step in the high-voltage transistor 120 in a later step, and is about 80 nm to 200 nm.

Thus, by forming the first gate electrode 125 and the second gate electrode 126 parallel to each other in the NMIS region of the high voltage transistor 120, for example, the drain formation region of the first gate electrode 125 is separated into two. The Accordingly, the p-type well 102 is positioned on the opposite side of the first drain formation region 129 with respect to the source formation region 128 and the first drain formation region 129 on both sides of the first gate electrode 125 and the second gate electrode 126. Three diffusion regions of the second drain formation region 130 to be formed are formed. The same applies to the PMIS region (not shown).

Next, as shown in FIG. 6, a resist mask 131 is formed in the NMIS region and the PMIS region of the fine transistor 121 by lithography. Thereafter, a high breakdown voltage LDD implantation 132, which is an LDD implantation for forming a relatively deep junction surface at a medium concentration in the NMIS region and the PMIS region of the high breakdown voltage transistor 120, is performed.

At this time, the LDD implantation tilt angle 133 is set to a high angle (large angle), and the first gate electrode 125 and the second gate electrode 126 are ion-implanted four times, one each from four directions. For example, in the NMIS region, phosphorus (P) having an ion energy of 40 keV to 60 keV and a dose of about 0.7 × 10 ¹² atoms / cm ² to 2 × 10 ¹² atoms / cm ² is tilted by 35 °. Inject 4 times at ~ 65 °. In the PMIS region, boron (B) having an ion energy of 12 keV to 20 keV and a dose of about 0.7 × 10 ¹² atoms / cm ² to 2 × 10 ¹² atoms / cm ² is tilted at a tilt angle of 35 °. Inject 4 times at ~ 65 °.

In this way, by performing ion implantation four times from four directions using the first gate electrode 125 and the second gate electrode 126 arranged close to each other as a mask, the first gate electrode on the upper portion of the p-type well 102 In the source formation region 129 and the second drain formation region 130 located on the outer sides of the 125 and the second gate electrode 126, the LDD implantation for 3 to 4 times is performed to form the LDD medium concentration region 134. On the other hand, in the first drain formation region 129 located between the first gate electrode 125 and the second gate electrode 126 adjacent to each other, the

gate electrodes

125 and 126 serve as shadows (masks) for LDD implantation. As a result of performing the LDD injection for one time, the LDD low concentration region 135 is formed. Since the LDD low-concentration region 135 is implanted twice with ions, for example, in the NMIS region, a total of phosphorus (P) is 1.4 × 10 ¹² atoms / cm ² to 4 × 10 ¹² atoms. Ions are implanted to about / cm ² . In the PMIS region, boron (B) is ion-implanted at about 1.4 × 10 ¹² atoms / cm ² to 4 × 10 ¹² atoms / cm ² .

The LDD low concentration region 135 and the LDD medium concentration region 134 are simultaneously formed by two

parallel gate electrodes

125 and 126, and the region into which impurity ions are implanted is determined by the gate electrode interval 136. Therefore, the LDD medium concentration region 134 and the LDD low concentration region 135 have an effect that they can be formed with high accuracy without depending on the alignment of the resist mask.

The first overlap width 137, which is the overlap width between the LDD medium concentration region 134 formed in the source formation region 128 of the first gate electrode 125 and the first gate electrode 125, is relatively large, about 50 nm to 150 nm. . On the other hand, in the LDD low concentration region 135, since the LDD implantation is limited to the direction parallel to the

gate electrodes

125 and 126, the second over-range which is the overlapping width of the first gate electrode 125 and the LDD low concentration region 135 is obtained. The overlap width 138 is about 20 nm to 50 nm, and the overlap width is small. Accordingly, the effective channel length 139 between the source formation region 128 and the first drain formation region 129 of the first gate electrode 125 can be increased. Thus, the influence of the short channel effect can be reduced, so that the transistor region can be reduced and the device area can be reduced. Therefore, since mask alignment is not required, it is possible to eliminate variations in the sustain breakdown voltage, and it is possible to reduce the device area and to suppress an increase in cost due to an increase in processes.

Also, the first drain formation region 129 forms an implantation profile having a low implantation concentration and a gentle change in electric field, and can reduce the impact ionization rate. For this reason, it is possible to improve the decrease in the sustain withstand voltage accompanying the increase in the substrate potential due to the increase in the substrate leakage current.

Furthermore, a gentle implantation profile can be formed by performing a heat treatment after performing the high breakdown voltage LDD implantation 132. For this reason, the effect of improving the sustain breakdown voltage can be further enhanced. The heat treatment conditions depend on the impurity implantation conditions, but in the case of low temperature and long time heating conditions, for example, heat treatment at a temperature of 500 ° C. to 750 ° C. for about 60 minutes to 120 minutes can be used. On the other hand, in the case of high-temperature and short-time heating conditions, for example, a spike heat treatment at a temperature of 750 ° C. to 1000 ° C. for 60 minutes can be used. Since this heat treatment step is performed before the extension implantation that greatly affects the transistor characteristics in the fine transistor 121 is performed, the characteristic deterioration of the fine transistor 121 can be ignored.

For the first drain formation region 129 and the second drain formation region 130 of the second gate electrode 126, the third overlap width 140, which is the overlap width between the LDD medium concentration region 134 and the second gate electrode 126, is 50 nm to 50 nm. As large as about 150 nm. On the other hand, the fourth overlap width 141, which is the overlap width between the LDD low concentration region 135 and the second gate electrode 126, is about 20 nm to 50 nm. Further, since the LDD implantation is limited to the direction parallel to the

gate electrodes

125 and 126, the overlap width between the LDD medium concentration region 134 and the LDD low concentration region 135 is small, but the high breakdown voltage LDD implantation 132 is performed. Since the second gate electrode width 142 is reduced after the heat treatment is performed, the LDD medium concentration region 134 and the LDD low concentration region 135 can be brought into contact with each other below the second gate electrode 126. FIG. 6 shows a state where heat treatment is applied.

Here, as conditions for forming the predetermined LDD low concentration region 135, the gate electrode interval 136, the gate electrode height 143, the second gate electrode width 142, the tilt angle 133, and the LDD implantation depth 144 shown in FIG. Organize the relationship.

7A and 7B, assuming that the thermal diffusion distance of implanted ions by the heat treatment described above is about 30 nm after performing the high breakdown voltage LDD implantation 132, an allowable tilt angle 133 and Gate electrode spacing 136 is shown.

For example, in FIG. 7A, when the gate electrode height 143 is 120 nm, the LDD implantation depth 144 after heat treatment is 80 nm, and the second gate electrode width 142 is 150 nm, the tilt angle 133 is If the angle is 51 ° or less, impurity ions are implanted into the first drain formation region 129 without penetrating implanted ions by LDD implantation in the lateral direction of the second gate electrode 126. Therefore, FIG. 7B shows that the gate electrode interval 136 under this condition may be set to 88 nm or less. Further, FIG. 7B shows that when the second gate electrode width 142 is 200 nm, the gate electrode interval 136 may be set to 117 nm or less.

FIG. 8A shows a planar configuration of the NMIS region of the high voltage transistor 120. FIG. 8B also shows a transistor obtained by rotating the configuration of FIG. 8A by 90 °. In any transistor arrangement, the tilt angle 133 of LDD implantation is set to a relatively high angle, and ion implantation in four directions is performed on the

gate electrodes

125 and 126. For this reason, the LDD medium concentration region is formed in the source formation region 129 and the second drain formation region 130 outside the first gate electrode 125 and the second gate electrode 126 arranged in proximity by LDD implantation for three to four times. 134 is formed. On the other hand, in the first drain formation region 129 between the first gate electrode 125 and the second gate electrode 126 that are arranged close to each other, the adjacent gate electrodes are shadows of the LDD implantation, so that two LDD implantations are performed. As a result, the LDD low concentration region 135 having the lowest impurity concentration is formed. Thus, according to the present embodiment, there is no restriction on the arrangement direction of the transistors, and the degree of freedom in design is increased.

Next, as shown in FIG. 9, TEOS (Tetra-Etyhl-Ortho--) having a film thickness of about 5 nm to 20 nm is formed on the entire surface of the semiconductor substrate 101 including the

gate electrodes

125, 126 and 127 by LP-CVD. (Silicate) or silicon nitride (SiN) or the like is deposited, and the deposited insulating film is etched back by anisotropic dry etching to form both sides of each

gate electrode

125, 126, and 127. Offset sidewalls 145 are formed respectively. At this time, as shown in FIG. 9, each upper end portion of the offset sidewall 145 is not necessarily formed. Subsequently, a resist mask 146 that covers the high breakdown voltage transistor 120 is formed by lithography, and extension implantation 147 that forms a high-concentration and shallow junction surface is performed on the substrate surface of the NMIS region in the fine transistor 121 to form an n-type extension. Region 148 is formed. As an extension implantation condition for the NMIS region, arsenic (As) having an ion energy of 2 keV to 4 keV and a dose of about 1 × 10 ¹⁵ atoms / cm ² to 3 × 10 ¹⁵ atoms / cm ² is ionized at a tilt angle of about 0 °. inject. Further, as an extension implantation condition in the PMIS region, boron (B) having an ion energy of 0.3 keV to 1 keV and a dose of about 2 × 10 ¹⁴ atoms / cm ² to 8 × 10 ¹⁴ atoms / cm ² is tilt angle 0. Ion implantation at about °.

Next, as shown in FIG. 10, TEOS by LP-CVD or SA-CVD (Sub-layer) is formed on the entire surface of the semiconductor substrate 101 including the

gate electrodes

125, 126 and 127 each having the offset sidewall 145 formed thereon. A sidewall underlayer film 149 made of NSG (Non-doped Silicate Glass) by an Atmospheric-Chemical Vapor Deposition method is deposited, and a thickness of about 10 nm is deposited on the sidewall underlayer film 149. A sidewall upper layer film 150 made of SiN by a Deposition method and having a film thickness of about 35 nm to 60 nm is deposited. Subsequently, the sidewall upper layer film 150 and the sidewall lower layer film 149 are etched back by anisotropic dry etching, and the offset sidewall 145 and the side wall are respectively formed on the side surfaces of the

gate electrodes

125, 126, and 127. A sidewall 110 including the wall lower layer film 149 and the sidewall upper layer film 150 is formed. At this time, when the gate electrode interval 136 between the first gate electrode 125 and the second gate electrode 126 is small, for example, about 88 nm, a sidewall is formed between the first gate electrode 125 and the second gate electrode 126. Since 110 is buried, the sidewalls 110 formed between the first gate electrode 125 and the second gate electrode 126 are connected to each other.

Next, as shown in FIG. 11, source / drain implantation 151 is simultaneously performed in the NMIS region and the PMIS region of the high voltage transistor 120 and the fine transistor 121, respectively. In the NMIS region, for example, arsenic (As) having an ion energy of ¹⁵ keV to 40 keV, a dose of about 2 × 10 ¹⁵ atoms / cm ² to 8 × 10 ¹⁵ atoms / cm ² , and an ion energy of 5 keV to 15 keV. At least one of phosphorus (P) having a dose of about 1 × 10 ¹⁵ atoms / cm ² to 5 × 10 ¹⁵ atoms / cm ² is ion-implanted. Further, boron (B) having an ion energy of 1 keV to 3 keV and a dose of about 2 × 10 ¹⁵ atoms / cm ² to 8 × 10 ¹⁵ atoms / cm ² is ion-implanted into the PMIS region. Thereby, the source region 103 and the drain region 105 of the high breakdown voltage transistor 120 and the fine transistor 121 are formed, respectively. At this time, although not shown, the source / drain implantation 151 is simultaneously implanted into the upper portions of the

gate electrodes

125, 126 and 127. The order of performing the source / drain implantation 151 in the NMIS region and the PMIS region is not particularly limited. Subsequently, in order to activate each impurity introduced by ion implantation, activation heat treatment at a temperature of 1000 ° C. or higher is performed by high-temperature, short-time lamp heating or laser heating.

Next, as shown in FIG. 12, a film thickness of about 5 nm to 20 nm is formed on the entire surface of the semiconductor substrate 101 including the source region 103 and the drain region 105 and the

gate electrodes

125, 126, and 127 by sputtering or the like. A nickel (Ni) film, which is a high melting point metal, is deposited. Thereafter, a heat treatment for siliciding the deposited Ni film is applied. Subsequently, the unreacted Ni film that is not silicided is removed by wet etching using hydrochloric acid or the like. Thereafter, heat treatment is appropriately performed to remove the first drain formation region 129 of the semiconductor substrate 101, the upper portions of the first gate electrode 125, the second gate electrode 126, and the third gate electrode 127, and the source region 103 and the drain region. A silicide layer 112 made of NiSi is formed on each upper portion of 105.

As described above, according to the manufacturing method of the semiconductor device according to the present embodiment, the LDD medium concentration region 134, the LDD low concentration region 135, the source region 103 and the drain region 105, and each silicide layer 112 are all self-aligned. Can be formed. Therefore, since there is no alignment shift without depending on the resist mask, a highly accurate drain expansion type transistor with suppressed variation in sustain breakdown voltage can be realized.

(First Modification of One Embodiment)
A semiconductor device according to a first modification of one embodiment will be described with reference to FIG.

As shown in FIG. 13, a pair transistor that uses two adjacent transistors that share a source region 103 as a differential circuit, and is paired with a pair transistor 152A and a pair transistor that are inverted horizontally around the source region 103. 152B are arranged. Here, in FIG. 13, the same components as those in FIG.

The

pair type transistors

152A and 152B are composed of the high breakdown voltage transistor 120 according to the present embodiment. Therefore, as described above, mask misalignment does not occur, and thus device performance does not deteriorate due to increased variation in operating characteristics. .

(Second Modification of One Embodiment)
Further, as shown in the second modified example of FIG. 14, the mask misalignment does not occur in the same way also in the pair type transistors 150A and 150B using the two adjacent transistors sharing the drain region 105 as the differential circuit. Therefore, the device performance does not deteriorate due to an increase in variation in operating characteristics.

(Description of operation)
Next, with reference to FIGS. 15 to 18, channel formation and depletion layer spreading due to four potentials applied to the first gate electrode 125 and the second gate electrode 126 will be described.

First, as shown in FIG. 15, when a high (Hi) voltage is applied to both the first gate electrode 125 and the second gate electrode 126, the gate insulating film 108 of the first gate electrode 125 in the p-type well 102. A channel 102a made of an inversion layer is formed immediately below the region. At this time, since the high voltage is also applied to the drain region 105, the bias voltage is not substantially applied to the second gate electrode 126 and the drain region 105. For this reason, the high breakdown voltage transistor 120 can be operated like a transistor with a drain resistance added, in which the second gate electrode 126 is not provided.

Next, as shown in FIG. 16, when a high voltage is applied to the first gate electrode 125 and a low voltage is applied to the second gate electrode 126, the first gate electrode 125 in the p-type well 102. In a region immediately below the gate insulating film 108, a channel 102a of an inversion layer is formed. On the other hand, a high voltage bias is applied to the drain region 105. In the case of an NMIS transistor, the impurities in the LDD medium concentration region 134 under the second gate electrode 126 are electrons of n-type carriers. Accordingly, electrons generated on the surface of the gate insulating film 108 of the second gate electrode 126 move toward the drain region 105 by the generated electric field. Therefore, since the depletion layer 157 is formed on the surface of the gate insulating film 108, the current path near the second gate electrode 126 is narrowed, and as a result, the drain resistance can be increased.

Next, as shown in FIG. 17, when a low voltage is applied to the first gate electrode 125 and a high voltage is applied to the second gate electrode 126, the gate insulation of the first gate electrode 125 in the p-type well 102 is performed. In a region immediately below the film 108, the channel 102a is not formed and is in an off state. On the other hand, since a high voltage is also applied to the drain region 105, a bias voltage is not substantially applied to the second gate electrode 126 and the drain region 105. For this reason, the high breakdown voltage transistor 120 can be operated like a transistor with a drain resistance added, in which the second gate electrode is not provided.

Next, as shown in FIG. 18, when a low voltage is applied to both the first gate electrode 125 and the second gate electrode 126, the p-type well 102 is directly under the gate insulating film 108 of the first gate electrode 125. In the region, the channel 102a is not formed and is in an off state. On the other hand, since a high voltage is applied to the drain region 105, a bias voltage is applied to the second gate electrode 126 and the drain region 105. In the case of the NMIS transistor, the impurities in the LDD medium concentration region 134 under the second gate electrode 126 are electrons of n-type carriers. Accordingly, electrons generated on the surface of the gate insulating film 108 of the second gate electrode 126 move toward the drain region 105 by the generated electric field. Therefore, a depletion layer 157 is formed on the surface of the gate insulating film 108, and the current path near the second gate electrode 126 is narrowed. As a result, drain resistance can be increased, and off-leakage current can also be reduced.

Thus, by applying a predetermined potential to the second gate electrode 126, the width, resistance value, and electric field of the depletion layer of the drain region 105 including the LDD medium concentration region 134 and the LDD low concentration region 135 can be adjusted from the outside. Therefore, the degree of freedom in circuit design is increased, and the depletion layer 157 in the LDD medium concentration region 134, the LDD low concentration region 135, and the drain region 105 can be controlled. Thereby, in addition to the improvement of the sustain breakdown voltage, it is possible to adjust the direction and position in which the hot carriers flow, so that it is possible to improve the deterioration of the hot carrier life.

15 to 18, the case of the NMIS transistor has been described, but the same effect can be obtained also in the case of the PMIS transistor. That is, in the case of the PMIS transistor, the n-type impurity of the NMIS transistor is changed to a p-type impurity, and the p-type impurity is changed to an n-type impurity. In the case of the NMIS transistor, the high voltage is 5 V, for example, and the low voltage is 0 V, for example. Therefore, the high voltage in the PMIS transistor may be read as 0 V, for example, and the low voltage as 5 V, for example.

(Third Modification of One Embodiment)
FIG. 19 shows a cross-sectional configuration of a high voltage transistor, which is a semiconductor device according to a third modification of one embodiment.

As shown in FIG. 19, the high breakdown voltage transistor 120 according to the third modification employs a configuration in which the width dimension (gate electrode width 142) of the second gate electrode 126 in the gate length direction is increased. Even in this case, it is possible to obtain the same effects as those obtained by the operations shown in FIGS. That is, when a high voltage is applied to both the first gate electrode 125 and the second gate electrode 126, the first gate electrode 125 and the second gate electrode 126 in the p-type well 102 are directly below the gate insulating films 108. In each region, a channel is formed by an inversion layer.

When the second gate electrode width 142 is relatively small, the depletion layer of the LDD low concentration region 135 and the LDD medium concentration region 134 can be short-circuited.

Further, when a high voltage is applied to the first gate electrode 125 and a low voltage is applied to the second gate electrode 126, the lower portion of the gate insulating film 108 of the second gate electrode 126 in the p-type well 102 is applied. It can be used as a high resistance layer.

Also, when a low voltage is applied to the first gate electrode 125 and a high voltage is applied to the second gate electrode 126, only the normal first gate electrode 125 can be turned off. In addition, when a low voltage is applied to both the first gate electrode 125 and the second gate electrode 126, a normal off state can be obtained.

As described above, various transistor operations can be performed by appropriately adjusting the value of the second gate electrode width 142.

(Fourth modification of one embodiment)
FIG. 20 shows a cross-sectional configuration of one step of a main part of a method for manufacturing a high voltage transistor, which is a semiconductor device according to a fourth modification of one embodiment.

As shown in FIG. 20, when the value of the gate electrode interval 136 between the first gate electrode 125 and the second gate electrode 126 is set large within a range in which the LDD low concentration region 135 can be formed, the sidewall 110 It is difficult to embed in the gap between the gate electrodes.

Therefore, in the step of performing the source / drain implantation 151, the resist mask 154 is formed so as to provide the boundary of the end face in the upper part of the first gate electrode 125 and the second gate electrode 126, respectively. Can be obtained.

(Fifth Modification of One Embodiment)
21 and 22 show a cross-sectional configuration in the order of steps of a main part of a method for manufacturing a high voltage transistor, which is a semiconductor device according to a fifth modification of the embodiment.

When the gate electrode interval 136 is set to a relatively large value, first, as shown in FIG. 21, a silicide block film 155 as an insulating film is formed on the entire surface of the semiconductor substrate 101 between the gate electrodes. It is deposited so as to be embedded in the gap.

Next, as shown in FIG. 22, isotropic wet etching is performed on the deposited silicide block film 155 to leave the silicide block film 155 only in the gap between the gate electrodes. As a result, even if the gap between the gate electrodes cannot be filled with the sidewall 110, the silicide block film 155 is selectively formed in the gap between the gate electrodes, so that each silicide layer 112 is formed by self-alignment. Can be formed.

(Sixth Modification of One Embodiment)
As shown in FIG. 23, the silicide lock film 155 is deposited only in the gap between the gate electrodes by performing anisotropic dry etching instead of isotropic wet etching on the deposited silicide lock film 155. 155 can remain. Therefore, as in the fifth modification, each silicide layer 112 can be formed by self-alignment.

Furthermore, in the sixth modified example, the silicide block film 155 is formed not only on the gap between the gate electrodes but also on the side surface of the lower portion of the sidewall 110 outside the first gate electrode 125 and the second gate electrode 126. Can be left behind. Therefore, in the source region 103 and the drain region 105, the distance between the inner end portion of each silicide layer 112 formed above them and the outer end portion of each

gate electrode

125, 126 can be increased. Therefore, electric field concentration from each silicide layer 112 to each

gate electrode

125, 126 can be reduced.

(Seventh Modification of One Embodiment)
As shown in FIG. 24, the silicide block film 155 cannot be embedded in the gap where the LDD low concentration region 135 can be formed, that is, the upper surface of the LDD low concentration region 135 is exposed. In that case, the resist mask 156 may be formed so that the boundary of the end face is provided on the upper portion of the first gate electrode 125 and the second gate electrode 126 on the silicide block film 155.

Therefore, after the silicide block film 155 is etched using the formed resist mask 156, the respective silicide layers 112 are formed as shown in FIG. Obtainable.

In the above-described embodiment and its modifications, an insulating film such as a TEOS film or a SiN film is used for the offset sidewall 145. In order to suppress oxidation or the like that the

gate electrodes

125 and 126 or the semiconductor substrate 101 suffer from, however, An NSG film formed by SA-CVD, a low-temperature LP-TEOS film, a low-temperature ALD-SiN film, a low-temperature silicon carbide (SiC) film, silicon oxynitride (SiON), or the like that can be formed at a low temperature can be used.

In this embodiment and its modification, Ni silicide is used for the silicide layer 112, but cobalt (Co), titanium (Ti), tungsten (W), platinum (Pt) or molybdenum (Mo), There is no particular problem even if silicides of those metal alloys or laminated metals are used.

In the present embodiment and its modification, the constituent material of the thin-film gate insulating film 124 constituting the fine transistor 121 is not limited to SiO ₂ . For example, a high dielectric constant (high-k) material such as hafnium oxide (HfO ₂ ), hafnium silicate (HfSixOy), or hafnium aluminate (HfAlxOy), or a group of insulating films to which nitrogen is added, such as SiO ₂ It may be a single layer film including any one selected or a laminated film including at least one film selected from these groups. The film thickness of the thin gate insulating film 124 may be determined as appropriate in consideration of the gate length, the EOT (equivalent oxide film thickness) tolerance, the leakage current tolerance, and the like.

The constituent materials of the

gate electrodes

125, 126, and 127 are doped with amorphous Si or non-doped polysilicon with phosphorus (P), arsenic (As), boron (B), indium (In), or the like by ion implantation. An electrode material containing silicon (Si) can be used. Further, an electrode material containing Si such as silicon germanium (SiGe) doped with germanium (Ge) may be used, and may be determined as appropriate from the viewpoint of workability or silicide reaction. As a method for forming the

gate electrodes

125, 126, and 127, a deposition method such as an LP-CVD method, a sputtering method, or an ALD method, or a coating method using a coating silicon material can be used. Furthermore, a silicon material doped with carbon or metal, porous silicon, or the like can be selected.

Further, in the present embodiment and its modification, a semiconductor in which a high voltage transistor 120 connected to a power supply voltage having a voltage of 5V and a fine transistor 121 connected to a power supply voltage having a voltage of 1.2V for high-speed operation are mixedly mounted. Although the apparatus has been described as an example, it is not limited to this configuration. In other words, it can be applied to a battery control circuit with a high-efficiency power control function to support in-vehicle devices that have a power supply voltage of 12V or 24V and a high withstand voltage of 60V that are used as stationary devices. It is. In this case, naturally, the film thickness of the gate insulating film 108, the gate length, the height of the gate electrode, and the like need to be scaled in accordance with the power supply voltage.

The semiconductor device and the manufacturing method thereof according to the present invention improve the sustain withstand voltage without causing an increase in area and an increase in the manufacturing process, suppressing the dispersion of the sustain withstand voltage, and adjusting the drain resistance and the junction profile after forming the transistor. A possible semiconductor device having a high degree of freedom can be realized, and is useful for, for example, a high-performance LSI device for use in the environmental field or in-vehicle field with a high power supply voltage.

101 semiconductor substrate 102 p-type well (semiconductor region)
102a channel 103 source region 105 drain region 107 element isolation 108 gate insulating film 109 polysilicon film 110 sidewall 112 silicide layer 120 high voltage transistor 121 fine transistor 122 p-type well 124 thin film gate insulating film 125 first gate electrode 126 second gate Electrode 127 Third gate electrode 128 Source formation region 129 First drain formation region 130 Second drain formation region 131 Resist mask 132 High breakdown voltage LDD implantation 133 Tilt angle 134 LDD medium concentration region 135 LDD low concentration region 136 Gate electrode interval 137 First Overlap width 138 Second overlap width 139 Effective channel length 140 Third overlap width 141 Fourth overlap width 142 Second gate electrode width 143 Gate Electrode height 144 LDD implantation depth 145 Offset sidewall 146 Resist mask 147 Extension implantation 148 Extension region 149 Side wall lower layer film 150 Side wall upper layer film 151 Source / drain implantation

152A Pair transistor

152B Pair transistor 154 Resist mask 155 Silicide block Film 156 Resist mask 157 Depletion layer

Claims

A first gate electrode formed on the first semiconductor region of the first conductivity type with a first gate insulating film interposed;
The second gate insulating film is interposed on the first semiconductor region, is formed in parallel with the first gate electrode at a distance, and is smaller in width in the gate length direction than the first gate electrode. A gate electrode;
A first source region containing a first impurity of a second conductivity type and a first drain region containing a second impurity of a second conductivity type, which are respectively formed in regions on both sides of the first gate electrode in the first semiconductor region. When,
A second source region containing a second impurity of a second conductivity type and a second drain region containing a fourth impurity of a second conductivity type, which are respectively formed in regions on both sides of the second gate electrode in the first semiconductor region. And
A concentration of the first impurity in the first source region is higher than a concentration of the second impurity in the first drain region;
A concentration of the third impurity in the second source region is lower than a concentration of the fourth impurity in the second drain region;
The semiconductor device in which the second source region is shared with the first drain region.
In claim 1,
A sidewall formed of an insulator is further formed on each side surface of the first gate electrode and the second gate electrode,
The side walls formed on the opposing side surfaces of the first gate electrode and the second gate electrode are in contact with each other.
In claim 1 or 2,
The semiconductor device in which the first source region, the first drain region, the second source region, and the second drain region have joint surfaces having the same junction depth.
In claim 1 or 2,
The first drain region is
A first PN junction comprising the first impurity and formed to overlap the first gate electrode;
A second PN junction formed by a second impurity formed in a region away from the first PN junction toward the second gate electrode and having a higher concentration than the first PN junction;
A semiconductor device formed in a region on the second gate electrode side from the second PN junction and having a third PN junction by the third impurity having a higher concentration than the second PN junction; .
In claim 1,
A region of the first source region to which the first impurity is added and a region of the second drain region to which the fourth impurity is added have a second conductivity type having a higher concentration than the first impurity and the fourth impurity. Of the fifth impurity,
The region to which the fifth impurity is added is formed by being included in the region to which the first impurity is added and the region to which the fourth impurity is added.
In claim 1 or 2,
A metal layer formed on the first source region and the second drain region;
The semiconductor device is a semiconductor device in which the metal layer is not formed on the first drain region and the second source region.
In claim 1,
The first gate insulating film is interposed on the first semiconductor region, and center lines along the gate width direction of the first gate electrode in the first source region are formed symmetrically with respect to each other. A third gate electrode having the same configuration as one gate electrode, and a fourth gate electrode having the same configuration as the second gate electrode;
A third source region including the first impurity and a third drain region including the second impurity, which are respectively formed in regions on both sides of the third gate electrode in the first semiconductor region;
A fourth source region including the third impurity and a fourth drain region including the fourth impurity, each formed in a region on both sides of the fourth gate electrode in the first semiconductor region;
A concentration of the first impurity in the third source region is higher than a concentration of the second impurity in the third drain region;
A concentration of the third impurity in the fourth source region is lower than a concentration of the fourth impurity in the fourth drain region;
The semiconductor device in which the third source region is shared with the first source region, and the fourth source region is shared with the third drain region.
In claim 1,
The first gate insulating film is interposed on the first semiconductor region, and center lines along the gate width direction of the second gate electrode in the second drain region are formed symmetrically with respect to each other. A fourth gate electrode having the same configuration as the two gate electrodes, and a third gate electrode having the same configuration as the first gate electrode;
A third source region including the first impurity and a third drain region including the second impurity, which are respectively formed in regions on both sides of the third gate electrode in the first semiconductor region;
A fourth source region including the third impurity and a fourth drain region including the fourth impurity, each formed in a region on both sides of the fourth gate electrode in the first semiconductor region;
A concentration of the first impurity in the third source region is higher than a concentration of the second impurity in the third drain region;
A concentration of the third impurity in the fourth source region is lower than a concentration of the fourth impurity in the fourth drain region;
The semiconductor device in which the fourth drain region is shared with the second drain region, and the fourth source region is shared with the third drain region.
In claim 1 or 2,
A semiconductor device in which a first overlap amount of an overlap portion between the first source region and the first gate electrode is larger than a second overlap amount of an overlap portion between the first drain region and the second gate electrode.
In claim 1 or 2,
A semiconductor device in which a third overlap amount in an overlapping portion between the second source region and the second gate electrode is smaller than a fourth overlap amount in an overlapping portion between the second drain region and the second gate electrode.
In claim 1 or 2,
The semiconductor device in which the second source region and the second drain region are in contact with each other and short-circuited in a lower portion of the second gate electrode in the first semiconductor region.
In claim 1 or 2,
The conductivity type of the lower part of the central part of the first gate electrode in the first semiconductor region is opposite to the conductivity type of the lower part of the central part of the second gate electrode.
In claim 1 or 2,
An interval between the first gate electrode and the second gate electrode is 70% or less of a height of the first gate electrode and the second gate electrode;
The width of the second gate electrode in the gate length direction is 1.3 times or more the height of the first gate electrode and the second gate electrode.
In claim 1,
A semiconductor device further comprising a third gate electrode formed on a second semiconductor region with a second gate insulating film thinner than the first gate insulating film interposed therebetween.
A method of manufacturing a semiconductor device according to claim 1,
The first source region, the first drain region, the second source region, and the second drain region are:
A method of manufacturing a semiconductor device, wherein the first gate electrode and the second gate electrode are used as masks to form ions by ion implantation from at least three different directions.