JPH1012747A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently suppress variance in transistor characteristics and short channel effect even when self-aligned contact structure is employed for some part on a semiconductor substrate. SOLUTION: While the aspect ratio of the pattern in an MOS-FET formation area is decreased by selectively removing an offset oxide film 4 on a gate electrode 3 in the MOS-FET formation area, oblique ion implantation is carried out to form a p<+> type pocket area 6 and an n<-> type LDD area 7L in a p type Si substrate 1. As the shadowing effect of obliquely implanted ions by the pattern decreases, impurities are implanted sufficiently into right below the edge part of the gate electrode 3. In the self-aligned contact formation area, on the other hand, the offset oxide film 4 is present as usual, therefore insulation between the gate electrode 3 and upper-layer wiring which is formed by postprocessing is held excellent.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device manufactured according to a fine design rule, and more particularly to a method of manufacturing a semiconductor device in which a self-aligned contact structure is employed in a part of a semiconductor substrate. The present invention relates to a method for effectively preventing a channel effect and making transistor characteristics uniform.

[0002]

2. Description of the Related Art As the design rules of semiconductor devices have been highly reduced, it is necessary to reduce the line width of a gate electrode and shorten the channel length in a field effect transistor (FET) to increase the operation speed. It is important in planning. However, on the other hand, the reduction in the channel length causes a so-called short channel effect. A typical example of the short channel effect is a punch-through phenomenon. This phenomenon occurs, for example, in a MOS-FET, when a depletion layer extending from the drain region and a depletion layer extending from the source region come into contact with each other as the channel length is shortened, a leakage current flows inside the Si substrate. In particular, it causes a serious performance degradation in a transfer transistor of a DRAM and a CMOS inverter.

[0003] As a countermeasure against punch-through, several methods have heretofore been proposed. As one of the techniques, there is a technique of suppressing the spread of a depletion layer from a source / drain region by increasing an impurity concentration of a channel region. However, this method increases the dependence of the threshold voltage Vth on the substrate potential, and is not necessarily an advantageous measure especially in a future device having a rule of 0.1 μm in which even the statistical fluctuation of the impurity concentration becomes a problem.

[0004] On the other hand, pocket ion implantation is known as a method of reducing such a concern. This is nM
Taking a process for forming an OS transistor as an example, after a gate electrode is formed on a p-type Si substrate, B (boron) ion implantation for forming a p-type pocket region is performed using the gate electrode as a mask, and an n-type source is formed. / As for forming drain region
This is a technique in which a p ⁺ -type pocket region is additionally formed at the pn junction interface of a normal transistor by successively implanting (arsenic) ions and then annealing. According to this method, the impurity concentration in the channel region increases only at the end portion, that is, in the vicinity of the source / drain region, and the impurity concentration in the portion immediately below the gate electrode does not need to be increased so much. Problems do not arise.

[0005] As the pocket ion implantation method described above,
A so-called oblique ion implantation method in which the incident direction of ions is inclined by a predetermined angle with respect to the normal direction of the Si substrate surface is often used. This is because impurities are introduced at a sufficient concentration into the Si substrate near the edge of the gate electrode. This oblique ion implantation is actually S
This is performed while rotating the substrate while the substrate surface is inclined.

[0006]

By the way, in recent semiconductor processes, since the improvement of the alignment performance of the reduced projection exposure apparatus in photolithography cannot keep up with the reduction of the design rule, the overlay accuracy with the lower layer wiring has to be improved. When the design margin of the connection hole is determined in consideration of the variation in the size, the design dimension of the connection hole (= hole diameter + design margin) becomes too large. If the design size of the connection hole becomes large, the line width of the lower wiring cannot be reduced, which is a major obstacle to miniaturization and high density of the semiconductor device. On the other hand, if an attempt is made to suppress an increase in the design size by reducing the hole diameter, the current exposure apparatus has an insufficient depth of focus and cannot resolve the hole pattern in the resist film.

[0007] From such a background, a self-alignment contact process has been proposed which can make the design margin for the superposition unnecessary on the photomask. Have been. Although there are various types of self-aligned contact processes, the process most often studied because a number of exposure steps is not increased is a process using a silicon nitride (SiN) film as an etching stop film. A conventional general self-aligned contact structure obtained by this process will be described with reference to FIG.

FIG. 1 shows a portion where a substrate contact is formed in a self-aligned manner between two gate electrodes (word lines) as seen in a bit line contact of an SRAM or a storage node contact of a DRAM. Shows the structure. That is, the gate oxide film 22 is formed on the Si substrate 21.
A gate electrode 23 (polySi / WSix) made of a tungsten / polycide film is formed via (SiO ₂ ). The gate electrode 23 has an offset oxide film 24 (SiOx) on its upper surface and an LDD sidewall 25 ( SiOx) and are insulated from the surroundings. In the Si substrate 21, source / drain regions 26 having an LDD structure are formed in a self-alignment manner with the gate electrode 23 and the edge of the LDD sidewall 25, respectively.

The surfaces of the offset SiOx film 24 and the LDD side wall 25 are covered with a SiN etching stop film 26 capable of ensuring an etching selectivity with respect to the SiOx-based material.
It is planarized by an interlayer insulating film 27 made of a PSG (boron / phosphor / silicate / glass) film. A contact hole 29 is opened in the interlayer insulating film 28 through resist patterning and anisotropic dry etching, and an upper wiring 30 made of, for example, a TiN / Al laminated film is formed to cover the contact hole 29.

When the contact hole 29 is opened in the interlayer insulating film 27 having a locally large difference in thickness, the SiN etching stop film 27 prevents the offset oxide film 24 and the LDD sidewall 2 from excessive overetching.
5 plays a role of protection. For this reason, the opening position of the contact hole 29 is slightly shifted with respect to the lower wiring (the source / drain region 26 in this case), or the contact hole 29 which is significantly wider than the space between the electrodes as shown in FIG. Even if such a case occurs, it is possible to minimize the erosion of the offset oxide film 24 and the LDD sidewall 25 when the SiN etching stop film 27 is removed. Also, the presence of the SiN etching stop film 27 enables the interlayer insulating film 28 to be flattened.

As described above, the offset oxide film 24 is an indispensable member for achieving insulation between the gate electrode 23 and the upper wiring 30 in the self-aligned contact structure as shown in FIG. From the viewpoint of ensuring the withstand voltage when the hole 29 overlaps the gate electrode 23, it is necessary to form the hole 29 with a certain thickness. This offset oxide film 24 is usually
3, the pattern height at the end of the patterning is higher than when only the gate electrode 23 is formed.

When the self-aligned contact process and the above-described oblique ion implantation are to be combined, as the distance between the patterns is reduced, the incidence of ions is affected by the shadowing effect of the patterns. The problem arises that it is difficult for impurities to be introduced to below the edge portion. This problem will be described with reference to FIG.

FIG. 9 is a diagram for explaining a difference in ion incidence efficiency during oblique ion implantation depending on the density and height of the pattern. First, when both the pattern height and the pattern interval are large as shown in FIG. 7A, ions which obliquely enter the substrate by grazing the edges of the pattern can also enter the substrate, as shown in FIG. If only the pattern interval is reduced without changing the pattern height, obliquely incident ions, which have sharpened the edges of one pattern, collide with the side wall surface of the adjacent pattern and cannot reach the substrate surface. The actual ion behavior is a little more complicated when the scattering due to the pattern edge is also taken into account, but in any case, the effect of the short channel effect can be obtained even in oblique pocket ion implantation in areas where the pattern is densely formed. Cannot be expected. Also, when the LDD ion implantation is performed obliquely, the penetration length of the LDD region (low-concentration impurity diffusion region) under the gate electrode differs between a sparse pattern region and a dense pattern region, and the transistor characteristics are reduced. It causes variation.

Therefore, the present invention eliminates the dependence of oblique ion implantation on the pattern density even when a self-aligned contact process is employed, thereby suppressing the short channel effect and making the transistor characteristics uniform. It is an object of the present invention to provide a possible method for manufacturing a semiconductor device.

[0015]

According to the present invention, there is provided a method of manufacturing a semiconductor device having a self-aligned contact formation region and a MIS transistor formation region on the same semiconductor substrate, wherein the transistor is formed only in the MIS transistor formation region. The above object is achieved by performing oblique ion implantation in a state where the offset insulating film on the upper surface of the gate electrode is selectively removed. This oblique ion implantation is typically a pocket ion implantation. When an LDD sidewall is formed on the side wall surface of the gate electrode to form the MIS transistor with an LDD structure, low-concentration ion implantation for forming an LDD region can be performed as the oblique ion implantation. .

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An offset insulating film formed by a common pattern with a gate electrode plays an important role in ensuring a withstand voltage between the gate electrode and an upper wiring in a self-aligned contact formation region. In the transistor formation region, this may hinder the introduction of impurities by oblique ion implantation. In the present invention, since the offset insulating film is selectively removed only in the transistor formation region, the efficiency of introducing impurities into the semiconductor substrate can be increased in this region. That is, as is clear from the comparison between FIGS. 9B and 9C, if the pattern interval is constant, the smaller the pattern height is, the more the shadowing effect becomes, as shown in FIG. 9C. Thus, obliquely incident ions can reach the Si substrate 21 sufficiently. As a result, the impurity is sufficiently introduced to just below the edge portion of the gate electrode, and variation in characteristics of the transistor and short channel effect can be suppressed. On the other hand, in the self-aligned contact formation region, since the offset insulating film exists on the gate electrode as in the related art, the withstand voltage between the gate electrode and the upper wiring is sufficiently ensured.

Hereinafter, a specific embodiment of the present invention will be described with reference to FIGS. Here, an n-type MOS-FET is taken as an example of the MIS transistor.

FIG. 1 shows, for example, in each of a self-aligned contact formation region and a MOS-FET formation region on a p-type Si substrate 1, a gate electrode 3 (polySi / WSi
x) and the offset oxide film 4 (SiOx) are formed in a common pattern. To explain the steps so far, first, for example, S
A gate oxide film 2 having a thickness of about 10 nm is formed on the surface of an i-substrate 1, and a tungsten (W) -polycide film is laminated thereon. The W-polycide film is made of polysilicon (pol) having a thickness of about 50 nm and
A ySi) film and a WSix film having a thickness of about 50 nm are stacked, and both can be formed by the LPCVD method. On top of this, for example, a plasma CV
After a SiOx film having a thickness of about 100 nm is formed by the method D, resist patterning is performed on the laminated film according to the pattern of the gate electrode 3, and anisotropic dry etching of the laminated film is performed. Such a pattern is formed.

The width of the gate electrode 3 is about 0.25 μm.
m, the space between the electrodes in the self-aligned contact formation region was about 0.25 μm, and the space between the electrodes in the MOS-FET formation region was about 0.4 μm. MOS-FET
The reason why the space between the electrodes is wide in the formation region is that the contact formation in the region is not self-aligned, so that the insulation between the gate electrode 3 and the upper wiring formed in a later step is made to some extent. This is because it is necessary to secure a space for this. However, even if the pattern interval is wide, the design rules of this level still make it difficult for ions obliquely entering the inter-wiring space to reach the substrate.

Next, as shown in FIG. 2, the pattern in the self-aligned contact formation region is
(PR). Using this resist pattern 5 as a mask, for example, RI using a fluorocarbon-based gas is used.
By performing E (reactive ion etching), M
The offset oxide film 4 constituting the uppermost layer of the pattern in the OS-FET formation region was selectively removed.

Next, as shown in FIG.
The pattern 5 was removed by ashing, and pocket ion implantation of a p-type impurity was performed. The ion implantation conditions at this time are, for example, ion species = B ⁺ , ion acceleration energy 3
0 keV, dose = 4 × 10 ¹² / cm ² , and ion incident angle = 45 °. Subsequently, LDD ion implantation of n-type impurities was performed. The ion implantation conditions at this time were, for example, ion species = As ⁺ , ion acceleration energy 25 keV, dose amount = 2 × 10 ¹³ / cm ² , and ion incident angle = 7 °.

By the above ion implantation, the silicon substrate 1
Has a p ⁺ type pocket region 6 and an n ⁻ type LDD region 7 _L
Are formed. According to the present invention, the offset oxide film 4 which causes the aspect ratio of the pattern to increase is the MOS-type.
Since the region is selectively removed in advance in the FET formation region, a sufficient concentration of impurities is introduced also immediately below the edge of the gate electrode 3 in this region, greatly contributing to suppression of variation in transistor characteristics and suppression of the short channel effect. doing.

Next, a SiOx film for covering the entire surface of the substrate in a conformal manner is formed by a CVD method, and the SiOx film is anisotropically etched back to form a sidewall surface of each pattern as shown in FIG. LDD sidewall 8 on top
s, 8t (the suffixes s and t indicate that the LDD sidewall formation locations are the
Indicates that this is an FET formation region. The same applies hereinafter. ) Formed. In this state, high-concentration ion implantation was performed to form source / drain regions 7 having an LDD structure. The ion implantation conditions at this time are, for example, ion species = As ⁺ , ion acceleration energy 20 keV, dose amount = 3 × 10 ¹⁵ /
cm ² . The activation of impurities is performed, for example, at 105
This was performed by RTA (rapid thermal annealing) at 0 ° C. for 10 seconds.

Next, as shown in FIG. 5, an SiN etching stop film 9 having a thickness of about 20 nm for conformally covering the entire surface of the substrate is formed by, for example, a plasma CVD method. The surface was flattened with an interlayer insulating film 10 having a thickness of about 400 nm. This interlayer insulating film 10 is obtained by, for example, reflowing a BPSG film formed by doping boron and phosphorus at the time of forming an SiOx film by an O ₃ -TEOS normal pressure CVD method. Such planarization of the interlayer insulating film 10 is made possible by providing the SiN etching stop film 9 having an etching selectivity with this film on the lower layer side. On the interlayer insulating film 10, a resist
Pattern 11 (PR) was formed. The resist pattern 11 has an opening 12 according to the contact hole pattern.

Next, the interlayer insulating film 10 exposed in the opening 12 is removed by, for example, dry etching using a mixed gas of CHF ₃ / CH ₂ F _{2 to} form a self-aligned contact as shown in FIG. Contact holes 13s and 13t were partially formed in the region and the MOS-FET formation region, respectively. This etching was performed under the condition that a high selectivity with respect to the underlying SiN etching stop film 9 can be secured by utilizing the deposition of the fluorocarbon polymer.

Subsequently, the SiN etching stop film 9 exposed as a base was dry-etched using, for example, a CHF ₃ / O ₂ mixed gas to complete the contact holes 13s and 13t as shown in FIG. Further, an upper wiring was formed so as to cover these contact holes 13s and 13t. The upper wiring includes a plug 14 buried in the contact holes 13s and 13t, and an upper wiring pattern 15 formed on the planarized interlayer insulating film 10. The plug 14 is, for example, Ti
The upper wiring pattern 15 can be composed of, for example, a TiN barrier metal / A film.
It can be composed of a three-layer film of 1-1% Si film / TiN antireflection film. The self-aligned contact structure as shown in FIG. 7 is employed for a bit line contact of an SRAM or a storage node contact of a DRAM, for example.

Although the specific embodiments of the present invention have been described above, the present invention is not limited to these embodiments. For example, it is optional to reverse the conductivity type of the impurity described above. Further, design rules, details of the device structure, constituent materials of each part, film forming methods, dry etching conditions, and ion implantation conditions can be appropriately changed or selected.

As is apparent from the above description, according to the present invention, even when such a self-aligned contact is formed on a part of the semiconductor substrate, the transistor performance can be made uniform and short-circuit can be achieved. -The channel effect can be suppressed. Therefore, the present invention greatly contributes to miniaturization, high integration, and high performance of a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a state in which an offset oxide film and a gate electrode are patterned in a self-aligned contact formation region and a MOS-FET formation region in a process example to which the present invention is applied.

FIG. 2 is a schematic cross-sectional view showing a state where a self-aligned contact formation region in FIG. 1 is covered with a resist pattern and an offset oxide film is selectively removed in a MOS-FET formation region.

FIG. 3 shows the removal of the resist pattern of FIG. 2 and the oblique ion implantation of a p ⁺ type pocket region and n ^{− in a} Si substrate.
FIG. 4 is a schematic cross-sectional view showing a state in which a mold LDD region is formed.

4 is a schematic cross-sectional view showing a state in which an LDD side wall is formed on a side wall surface of the gate electrode in FIG. 3 and source / drain regions are formed by performing high-concentration ion implantation.

5 is a schematic cross-sectional view showing a state in which a conformal SiN etching stop film and a flat interlayer insulating film are sequentially laminated on the entire surface of the substrate of FIG. 4 and resist patterning has been performed.

6 is a schematic cross-sectional view showing a state in which a contact hole is formed partway by selectively dry-etching the interlayer insulating film of FIG. 5;

FIG. 7 shows Si exposed on the bottom surface of the contact hole in FIG. 7;
FIG. 11 is a schematic cross-sectional view showing a state in which a contact hole is completed by selectively removing an N-etching stop film and an upper-layer wiring covering the contact hole is formed.

FIG. 8 is a schematic cross-sectional view for explaining a conventional general self-aligned contact structure.

9A and 9B are schematic cross-sectional views illustrating differences in ion incidence efficiency during oblique ion implantation depending on the density and height of a pattern. FIG. 9A is a diagram when both the pattern height and the pattern interval are large, and FIG. (C) shows the case where the pattern height is large and the pattern interval is small, and (c) shows the case where both the pattern height and the pattern interval are small.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Si substrate 2 ... Gate oxide film 3 ... Gate electrode 4
... Offset oxide film 6 ... Pocket region 7 ... Source /
Drain region 8s LDD side wall (for self-aligned contact formation region) 8t LDD side wall (for MOS-FET formation region) 9 ... SiN etching stop film 10 ... Interlayer insulating film 13s ... Contact (for self-aligned contact formation region) Hall 13t ... (MO
Contact hole (in the S-FET formation region) 14 plug 15 upper wiring pattern

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device having a self-aligned contact formation region and a MIS transistor formation region on the same semiconductor substrate, comprising: an electrode pattern having an upper surface covered with an offset insulating film on the semiconductor substrate. A second step of covering the electrode pattern in the self-aligned contact formation region with a resist pattern; and an offset insulation of an upper surface of the electrode pattern in the MIS transistor formation region. A third step of selectively removing a film, a fourth step of removing the resist pattern, and a fifth step of implanting ions into the semiconductor substrate from a direction inclined at a predetermined angle with respect to a normal direction of the semiconductor substrate. And a method for manufacturing a semiconductor device. 2. The method according to claim 1, wherein in the fifth step, a pocket region is formed in the semiconductor substrate by ion-implanting an impurity of the same conductivity type as that of the semiconductor substrate. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising, after the fifth step, a sixth step of forming an LDD sidewall on a side wall surface of the electrode pattern. 4. In the fifth step, an impurity of the same conductivity type as that of the semiconductor substrate is ion-implanted to form a pocket region in the semiconductor substrate, and an impurity of a conductivity type opposite to that of the semiconductor substrate is ion-implanted. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the LDD region is formed by performing the method.