JP2000106436A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which causes no short-circuit between a gate electrode and a contact member and can also meet to miniaturization of the device. SOLUTION: A gate insulating film 2, a gate electrode 3a and a protective layer 4a on a gate are formed on an Si substrate 1 and thereafter, lightly doped source and drain regions 6 are formed on the substrate 1. A first sidewall 15a and a second sidewall are respectively formed on the side surfaces of the electrode 3a and after that, heavily doped source and drain regions 9 are formed on the substrate 1 by an ion implantation method using these sidewalls as masks. After the second sidewall is selectively removed, pocket implanted regions Rpo are formed in the substrate 1 and an entire surface protective film 12 is deposited. After that, deposition of an interlayer insulating film 10, formation of a contact hole Hct to reach the drain region 9 and formation of a plug electrode 11 are conducted. As the second sidewall is removed at the time of deposition of the film 12, the part between the electrode 3a and the film 12 is not filled with the film 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a self-aligned contact.

[0002]

2. Description of the Related Art Recently, when forming a contact member to a source / drain region of a MOS transistor, a self-aligned contact structure, a so-called SAC structure, has begun to be used in order to increase the density of elements. This is L
The sidewall used to form the DD structure is also used as an etching stopper when forming a contact in a self-aligned manner.

FIGS. 7A to 7D are cross-sectional views showing a conventional method of manufacturing a MOS transistor having a general self-aligned contact structure. With the recent miniaturization of transistors, a so-called LDD structure is used as a transistor structure. As a method of manufacturing the transistor, a sidewall is formed on a side surface of a gate electrode, and the sidewall is further formed. Generally, a high concentration source / drain region is formed by ion implantation as a mask.

First, in a step shown in FIG.
01, a gate oxide film 102 made of a thermal oxide film, a polysilicon film 103 for a gate electrode, and a silicon nitride film 10
After sequentially forming the resists 4, a resist film 105 for gate patterning is formed.

Next, in the step shown in FIG.
05 as an etching mask, silicon nitride film 1
04 and the polysilicon film 103 are sequentially etched,
After the over-gate protection layer 104a and the gate electrode 103a are formed, impurities (phosphor or arsenic in an n-channel MOS transistor, and boron in a p-channel MOS transistor) are introduced into the semiconductor substrate 101 using the gate electrode 103a and the like as a mask. By performing ion implantation, a low concentration source / drain region 106 is formed. Thereafter, the CVD oxide film 107 and the CVD nitride film 1 are formed on the substrate.
08 is deposited.

Next, in the step shown in FIG. 7C, by performing anisotropic dry etching of the CVD oxide film 107 and the CVD nitride film 108, an oxide film sidewall 107a and a nitride film side surface are formed on the side surfaces of the gate electrode 103a. A wall 108a is formed.

Next, in the step shown in FIG.
03a, the oxide film sidewall 107a and the nitride film sidewall 108a are used as a mask, and impurities (phosphor or arsenic in an n-channel MOS transistor, and boron in a p-channel MOS transistor) are ion-implanted to obtain a high-concentration source. Drain region 109
Is formed, thereby completing the MOS transistor having the LDD structure.

In the self-aligned contact technique, the contact between the gate electrode and the contact member is prevented by using the nitride film sidewall 108a formed in the above process as an etching stopper when forming a contact hole.

FIG. 8 is a sectional view showing an example of a sectional state of a MOS transistor when a contact member is formed. As shown in FIG. 8, after an interlayer insulating film 110 made of a silicon oxide film is deposited on the MOS transistor having the LDD structure formed in FIG. 7D, the interlayer insulating film 110 is flattened. Then, photolithography and etching are performed to form a high concentration source
A contact hole reaching the drain region 109 is formed. At this time, even if a part of the contact hole interferes with the on-gate protective layer 104a and the nitride film sidewall 108a, the interlayer insulating film 110 made of a silicon oxide film and the on-gate protective layer 104a and nitride film made of a silicon nitride film Since the etching selectivity with respect to the sidewall 108a is high, the protection layer 104a on the gate and the nitride
08a is hardly etched. That is, these functions as an etching stopper at the time of forming a contact hole, thereby protecting the gate electrode 103a. Thereafter, the plug electrode 111 is buried in the contact hole, and a wiring layer (not shown) is further formed thereon.

As described above, the nitride film sidewall 108
a is used as a mask for ion implantation for forming the high-concentration source / drain regions 109 in the manufacturing process of the MOS transistor having the SAC structure and the LDD structure, and protects the gate electrode 103a at the time of forming the self-aligned contact. Also used as an etching stopper. However, it is known that direct contact between the nitride film sidewall 108a and the side surface of the gate electrode 103a deteriorates the characteristics of the transistor.
A thin oxide film sidewall 107a is interposed between the gate electrode 8a and the thin oxide film sidewall 107a.

When the contact hole is formed so as to reach above the gate electrode 103a as shown in FIG. 8, the upper end surface of the oxide film sidewall 107a is exposed in the contact hole. When the oxide film sidewall 107a is etched,
On-gate protection layer 104a and nitride film sidewall 108
There is a possibility that the contact hole may reach the gate electrode 103a due to the digging of the gap with the gate electrode 103a. This is because the plug electrode 111 and the gate electrode 103a are contact members.
Means that there is an electrical short circuit.

As a countermeasure, as shown in FIGS. 9A and 9B, after forming a MOS transistor by the steps shown in FIGS.
After covering with a VD nitride film 112 and forming an interlayer insulating film 110 on the entire surface of the substrate, a contact hole is formed in the interlayer insulating film 110. In this case, in the state shown in FIG. 9B, the progress of etching is prevented by the CVD nitride film 112 until the contact hole penetrates the interlayer insulating film 110, so that it is ensured that the contact hole reaches the gate electrode 103a. Can be prevented.

[0013]

However, in the manufacturing process of the above-described conventional semiconductor device having the SAC structure, there are the following problems.

That is, as shown in FIG. 10, by depositing a relatively thick CVD nitride film 112, the gap between the gate electrodes 103a of adjacent MOS transistors may be filled with the CVD nitride film 112. there were. In particular, as recently, when the gate length is 0.15
When the gate pitch is about 0.4 μm, the gap between the gates is about 0.25 μm. Considering the thickness of the oxide film sidewall and the thickness of the nitride film sidewall, the gap between them is Since it is extremely small, the probability of occurrence of this problem tends to increase. Opening a contact hole reaching the source / drain region 109 below the gap between the gates filled with the CVD nitride film 112 as shown in FIG. Was difficult.

An object of the present invention is to provide a semiconductor device which functions as a MIS transistor having a so-called SAC structure, by taking measures for ensuring the formation of a self-aligned contact while maintaining reliability, thereby achieving an SAC suitable for miniaturization. An object of the present invention is to provide a method for manufacturing a semiconductor device having a structure.

[0016]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: (a) forming a gate insulating film, a gate electrode, and a protective layer on a gate on a semiconductor substrate; (B) performing ion implantation for forming a low-concentration impurity diffusion region in the semiconductor substrate using the protective layer as a mask; and forming a first insulating film and a first insulating film on the substrate. A step (c) of depositing a mask film that can be selectively etched, and anisotropically etching the first insulating film and the mask film to form a film on the side surfaces of the gate electrode and the over-gate protection layer. Forming a first sidewall while leaving a part of the first insulating film, and forming a second sidewall while leaving a part of the mask film on a side surface of the first sidewall; (D) and the game A step (e) of performing ion implantation for forming a high-concentration impurity diffusion region in the semiconductor substrate using the upper protective layer, the gate electrode, and each side wall as a mask, and after the step (e), (F) for selectively removing the second sidewall while leaving the side wall of (a), and after the step (f), a second layer covering at least the above-gate protection layer and the first sidewall on the substrate. (G) depositing an insulating film of the above, and after the step (g), depositing an interlayer insulating film made of a material that can be selectively etched with respect to the second insulating film on the substrate (h) ) And by etching,
The method includes a step (i) of forming an opening reaching the high-concentration impurity diffusion region, and a step (j) of embedding a plug electrode made of a conductive material in the opening.

According to this method, in the step (e),
Since the second sidewall exists, the high-concentration impurity diffusion region can be formed at a position offset from the low-concentration impurity diffusion region, and a MIS transistor having a so-called LDD structure can be obtained. On the other hand, in the step (g), the gap between the gate electrodes of the adjacent transistors is sufficiently large because the second sidewall is not present, and the gap is filled with the second insulating film. Can be suppressed. Therefore, even when the semiconductor device is miniaturized, a highly reliable semiconductor device having a so-called SAC structure and the presence of the second insulating film can be formed.

In the method of manufacturing a semiconductor device, in the step (c), an NSG film is formed as the first insulating film.
By forming a PSG film or a BPSG film as the mask film, respectively, the etching selection of the first sidewall and the second sidewall can be performed without adverse effects such as generation of stress in the operation region of the semiconductor device. The ratio can be secured.

In this case, by performing the step (f) by HF vapor phase etching, only the second sidewall can be reliably removed with a high etching selectivity.

In the method of manufacturing a semiconductor device, after the step (f) and before the step (g), the semiconductor substrate is formed in the semiconductor substrate by using the over-gate protective layer, the gate electrode and the first sidewall as a mask. By further providing a step of performing ion implantation for forming a pocket implantation region, a semiconductor device having a high punch-through prevention function can be formed.

In the method of manufacturing a semiconductor device, after the step (e) and before the step (f), a step of forming a protective film on the substrate as a mask for the non-silicided region; Forming a low-concentration impurity diffusion region for preventing leakage below the high-concentration impurity diffusion region using the film as a mask; and covering the silicidation region except for a portion of the protective film covering the non-silicidation region. And a step of forming a silicide layer on the surface of the high-concentration impurity diffusion region.
Using the protective film serving as a mask when performing the silicide process, a low-concentration impurity diffusion region for preventing leakage can be formed. The leak preventing low-concentration impurity diffusion region not only reduces the leak current, but also
Since the junction capacitance is also reduced, a semiconductor device having a high operation speed can be obtained in combination with the reduction of the sheet resistance by the silicide layer.

According to a second method of manufacturing a semiconductor device of the present invention,
Step (a) of forming a gate insulating film, a gate electrode and a protective layer on a gate on a semiconductor substrate, and a first insulating film and a mask capable of selectively etching the first insulating film on the substrate (B) depositing a first insulating film and an anisotropic etching of the first insulating film and the mask film to form a first insulating film on the side surfaces of the gate electrode and the over-gate protective layer. (C) forming a first sidewall while leaving a part thereof, and forming a second sidewall while leaving a part of the mask film on a side surface of the first sidewall; A step (d) of performing ion implantation for forming a high-concentration impurity diffusion region in the semiconductor substrate using the over-gate protective layer, the gate electrode, and the respective sidewalls as a mask; and, after the step (d), Leaving one side wall (E) selectively removing the second sidewall, and forming a low-concentration impurity diffusion region in the semiconductor substrate using the gate electrode, the protective layer on the gate and the first sidewall as a mask. After the step (f) of performing the ion implantation of the above and the above step (f),
Depositing a second insulating film covering at least the above-mentioned protective layer on the gate and the first sidewall on the substrate (g).
Depositing an interlayer insulating film made of a material that can be selectively etched with respect to the second insulating film on the substrate after the step (g); and etching the interlayer insulating film by etching. (I) forming an opening reaching the high-concentration impurity diffusion region; and (j) embedding a plug electrode made of a conductive material into the opening.

According to this method, the same operation and effect as those of the first method for manufacturing a semiconductor device can be obtained. in addition,
In this method, the high-concentration impurity diffusion region is formed first, and then the low-concentration impurity diffusion region is formed. It is possible to suppress the short channel effect by performing a heat treatment for activating the impurity in the low concentration diffusion region in a short time even at a low temperature condition or a high temperature while reducing the junction capacitance by sufficiently deepening the region. It becomes possible.

In the second method for manufacturing a semiconductor device,
Additional items similar to those of the first method for manufacturing a semiconductor device can be provided.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1A to 1D are cross-sectional views showing steps of manufacturing an N-channel MIS transistor which is a semiconductor device according to a first embodiment of the present invention. Note that the P-channel MIS transistor also differs only in the conductivity type of the impurity doped into each part of the MIS transistor.
Are performed in the same manner as the process shown in FIG.

First, in the step shown in FIG. 1A, after forming an element isolation region (not shown) on the Si substrate 1, an MIS transistor is formed in an active region surrounded by the element isolation region by the following steps. For the process. First, a silicon oxide film having a thickness of about 3 nm is formed on the main surface of the Si substrate 1 by performing a thermal oxidation process, and then a gate insulating film 2 made of silicon oxynitride is formed by performing a nitriding process. Then, a gate electrode 3a made of polysilicon and an over-gate protection layer 4a made of silicon nitride are formed on the gate insulating film 2. At this time, although not shown, the same steps as those shown in FIG. That is, after depositing the polysilicon film and the silicon nitride film, photolithography and dry etching are performed to pattern the polysilicon film and the silicon nitride film to form the gate electrode 3a and the over-gate protection layer 4a.

The gate electrode 3a is doped with an N-type impurity (a P-type impurity for a P-channel MIS transistor).

Then, using the gate electrode 3a and the over-gate protective layer 4a as a mask, phosphorus ions (P ⁺ ) are implanted under the conditions of an inclination angle of 7 to 40 °, an implantation energy of 20 to 30 keV, and a dose of about 5 × 10 ¹³ / cm ² . To form low-concentration source / drain regions 6. In addition, low concentration source
An extension region may be formed instead of the drain region 6, in which case, arsenic ions (As) are implanted with an implantation energy of 10 to 20 keV and a dose of 5 × 10 ¹⁴ / c.
Inject under the condition of m ² .

Next, in the step shown in FIG. 1B, a thin non-doped oxide film 15 having a thickness of 10 to 20 nm is formed on the entire surface of the substrate.
(For example, NSG film) and a doped oxide film 16 (BPSG film, PSG film, BSG film, etc.) having a thickness of 40 to 60 nm.
Are sequentially deposited.

Next, in the step shown in FIG. 1C, anisotropic etching is performed to form a first sidewall 15a and a second sidewall 16a on the side surface of the gate electrode 3a. Then, using the gate electrode 3a, the over-gate protective layer 4a and the side walls 15a and 16a as masks, arsenic ions are implanted at an inclination angle of 7 ° and an implantation energy of 30 to 50 ke.
V is implanted under the conditions of a dose of 3 to 5 × 10 ¹⁵ / cm ² to form a high concentration source / drain region 9.

Note that a thin nitride film may be interposed between the first sidewall 15a and the second sidewall 16a. In addition, the material of the first sidewall 15a and the second sidewall 16a is not limited to the material of the present embodiment, and the second sidewall 16a is formed in the next step.
What is necessary is just to be able to remove a selectively.

Next, in the step shown in FIG. 1D, only the second sidewall 16a is selectively removed while leaving the first sidewall 15a. At this time, selective etching can be easily performed by performing HF vapor phase etching. That is, in the gas phase etching of HF, the etching rate for a doped oxide film such as a BPSG film is about two orders of magnitude higher than the etching rate for a non-doped oxide film such as an NSG film. Becomes possible. At this time, the portion of the gate insulating film 2 that is exposed on the substrate is often removed, although it depends on the amount of over-etching.

Thereafter, using the gate electrode 3a, the over-gate protection layer 4a and the first side wall 15a as a mask, boron ions (or boron fluoride ions) are tilted at an angle of 20 degrees.
The implantation is performed under conditions of about 40 °, implantation energy of 10 to 50 keV, and dose of 1 to 5 × 10 ¹³ / cm ² to form a pocket implantation region Rpo for a punch-through stopper. The pocket injection region Rpo is not always necessary.

Thereafter, in order to activate the impurities doped in each of the regions 6, 9 and Rpo, at 900-1000.degree.
The RTA process is performed under the condition of 0 to 30 sec.

Thereafter, a self-align contact step is performed according to the procedure shown in FIGS. 2A to 2C. Note that “self-aligned contact” here means that a margin is not provided in consideration of a positional shift between a mask for forming a gate electrode and a mask for forming a contact hole.

First, in the step shown in FIG. 2A, a thickness of 30 to 30
A 50 nm overall protective film 12 is deposited. At this time, as the material of the entire surface protective film 12, instead of silicon nitride, another insulating material having a high etching selectivity with respect to an interlayer insulating film to be formed later can be used.

Next, in a step shown in FIG. 2B, an interlayer insulating film 10 is deposited on the entire surface of the substrate, and the interlayer insulating film 10 is planarized. Then, the interlayer insulating film 10 is formed by photolithography and dry etching. Then, a contact hole Hct which penetrates the entire surface protective film 12 and reaches the high concentration source / drain region 9 is formed. At this time, contact hole Hct
Reaches a part of the entire surface protective film 12 and the part is exposed, the entire surface protective film 12 having a high etching selectivity with respect to the interlayer insulating film 10 functions as an etching stopper. When the removal of the interlayer insulating film 10 is completed, the entire surface protective film 12 is removed by switching the etching gas. Thereby, a self-aligned contact hole Hct can be formed for gate electrode 3a. Note that FIG. 2B shows a state where the contact hole Hct is in contact with the on-gate protection layer 4a when the displacement of the mask is large. The first
On the side surface of the portion of the sidewall 15a exposed to the inside of the contact hole Hct, a part of the entire protective film 12 remains to form the sidewall 12a.

Thereafter, in a step shown in FIG. 2C, a metal such as W or Al is buried in the contact hole Hct to form the plug electrode 11.

Although illustration of the subsequent steps is omitted, a metal wiring layer is formed on the interlayer insulating film 10 and the plug electrode 11 and, if necessary, a second interlayer insulating film,
It is general to form a wiring layer,..., And provide a multilayer wiring layer.

According to the manufacturing method of the present embodiment, in the step shown in FIG.
When the contact hole Hct reaching the drain region is formed, the first passivation film 12 completely covers the upper part of the gate electrode 3a and the first sidewall 15a.
The side wall 15a is removed and the contact hole H is removed.
ct does not reach the gate electrode 3a. That is, when the contact hole Hct reaches a part of the entire surface protective film 12 through the interlayer insulating film 10, the entire surface protective film 12 having a high etching selectivity with respect to the interlayer insulating film 10 functions as an etching stopper. Therefore, by the time the removal of the interlayer insulating film 10 is completed, the already exposed portion of the entire surface protective film 12 is slightly etched. However, since the etching amount is small, the contact hole Hct is not completely removed. 12 does not reach the over-gate protection layer 4a or the first sidewall 15a. After the contact hole Hct has penetrated the entire surface protective film 12, the over-gate protective layer 4a and the first sidewall 15a are partially removed by the amount of the overetching, but the removal amount is small.

The above effects are almost the same as those of the conventional method for manufacturing a semiconductor device shown in FIGS. 9A and 9B. However, in the present embodiment, unlike the conventional method of manufacturing a semiconductor device, it is possible to effectively prevent the entire surface of the protective film from filling the gap between the adjacent gate electrodes.

FIG. 3 is a sectional view showing a state where the gap between the gate electrodes 3a of two MIS transistors is extremely small. In the present embodiment, since the second sidewall 16a corresponding to the nitride film sidewall 108a shown in FIG. 10 is removed, the gap between the gate electrodes 3a is widened accordingly. Therefore, this gap is not filled with the entire surface protective film 12. For example, when the gate length is 0.15 μm and the pitch between the gate electrodes is 0.4 μm, the gap between adjacent gate electrodes 3a is 0.25 μm. Under this condition, if the thickness of the first sidewall 15a is at most 20 nm, the gap is 0.21 μm. Therefore, even if the entire surface protective film 12 having the thickness of at most 50 nm is deposited, the adjacent gate electrode 3a The gap between them is not filled with the entire surface protective film 12.

That is, the common source / drain region 9 existing between the gate electrodes 3a of the adjacent MIS transistors is the same as the contact hole to the source / drain region 9 existing in other portions. To
A contact hole can be reliably formed.

The pocket injection region Rpo is not always necessary. However, punch-through can be effectively suppressed by providing the pocket injection region Rpo.
Generally, a pocket injection region is often provided in an MIS transistor having an LDD structure. In this case, in the conventional manufacturing process, ion implantation for forming a pocket implantation region is performed in the process shown in FIG. 7B or FIG. 7D. It is necessary to distinguish between the drain region and the high concentration source / drain region. In contrast, in the present embodiment,
By using only the first sidewall 15a as a mask,
There is an advantage that it can be easily distinguished from the low-concentration source / drain region 6 (or the extension region) and the high-concentration source / drain region 9.

In the present invention, the entire surface protective film 12 is formed.
Must be made of a material having a high etching selectivity to the interlayer insulating film 10. Generally, a silicon oxide film doped with an impurity, for example, a BPSG film is used for the interlayer insulating film. Therefore, it is preferable to use a silicon nitride film having a high etching selectivity with respect to the BPSG film as the entire surface protective film 12 in the present invention. However, other insulating films such as an NSG film and a silicon oxynitride film can be used as long as the etching selectivity with the interlayer insulating film 10 can be ensured. The same applies to the second and third embodiments described later.

The first sidewall 15a must be made of a material that does not generate stress on the gate electrode 3a or the Si substrate 1, and the second sidewall 16a is formed of the first sidewall 15a or the first sidewall 15a. , The gate insulating film 2 or the Si substrate 1 must be made of a material having a high etching selectivity.

Therefore, in addition to the combination in this embodiment, the first side wall 15a is formed from a silicon oxide film (either a non-doped oxide film or a doped oxide film), and the second side wall 15a is formed from a silicon nitride film and a poly-silicon film. A combination formed from a silicon film, a metal film, an organic film, a carbon film, or the like can also be employed. Even when both the first and second sidewalls 15a and 16a are formed of a silicon oxide film, a high etching selectivity can be ensured if one of the impurity concentrations is high and the other is low. However, the first sidewall 1
Considering that the gate electrode 5a contacts the gate insulating film 2, the first
It is preferable that the side wall 15a is formed of a silicon oxide film having a lower impurity concentration. The same applies to the second and third embodiments described later.

The protective layer 4a on the gate may be made of an insulating material, and it is not always necessary that the etching selectivity with the interlayer insulating film 10 is high. However, the entire protective film 1
2 and the interlayer insulating film 10 have a high etching selectivity,
Considering that the portion directly above the on-gate protection layer 4a of the entire surface protection film 12 may be removed before the penetration of the thick interlayer insulation film 10 is completed, the on-gate protection layer 4a is formed of the interlayer insulation film 10a. It is preferable to be made of a material having a high etching selectivity with respect to. Therefore, silicon nitride is preferable as the material of the protective layer on the gate. The same applies to the second and third embodiments described later.

(Second Embodiment) FIGS. 4A to 4D are cross-sectional views showing steps of manufacturing an N-channel MIS transistor as a semiconductor device according to a second embodiment of the present invention. The P-channel MIS transistor also differs only in the conductivity type of the impurity doped into each part of the MIS transistor.
Are performed in the same manner as the process shown in FIG.

First, in a step shown in FIG. 4A, after forming an element isolation region (not shown) on the Si substrate 1, an MIS transistor is formed in an active region surrounded by the element isolation region by the following steps. For the process. First, a silicon oxide film having a thickness of about 3 nm is formed on the main surface of the Si substrate 1 by performing a thermal oxidation process, and then a gate insulating film 2 made of silicon oxynitride is formed by performing a nitriding process. Then, a gate electrode 3a made of polysilicon and an over-gate protection layer 4a made of silicon nitride are formed on the gate insulating film 2. At this time, although not shown, the same steps as those shown in FIG. That is, after depositing the polysilicon film and the silicon nitride film, photolithography and dry etching are performed to pattern the polysilicon film and the silicon nitride film to form the gate electrode 3a and the over-gate protection layer 4a. The gate electrode 3a
Is doped with an N-type impurity (a P-type impurity for a P-channel MIS transistor).

Next, in a step shown in FIG. 4B, a thin non-doped oxide film 15 having a thickness of 10 to 20 nm is formed on the entire surface of the substrate.
(For example, NSG film) and a doped oxide film 16 (BPSG film, PSG film, BSG film, etc.) having a thickness of 40 to 60 nm.
Are sequentially deposited.

Next, in the step shown in FIG. 4C, anisotropic etching is performed to form a first sidewall 15a and a second sidewall 16a on the side surface of the gate electrode 3a. Then, using the gate electrode 3a, the over-gate protective layer 4a and the side walls 15a and 16a as masks, arsenic ions are implanted at an inclination angle of 7 ° and an implantation energy of 30 to 50 ke.
V is implanted under the conditions of a dose of 3 to 5 × 10 ¹⁵ / cm ² to form a high concentration source / drain region 9. Thereafter, in order to activate the impurities doped in the high concentration source / drain regions 9, 900 to 1000 ° C., 10 to 3
The first RTA is performed under the condition of 0 sec.

Note that a thin nitride film may be interposed between the first side wall 15a and the second side wall 16a.

Next, in the step shown in FIG. 4D, only the second sidewall 16a is selectively removed while leaving the first sidewall 15a. At this time, selective etching can be easily performed by performing HF vapor phase etching. That is, in the gas phase etching of HF, the etching rate for a doped oxide film such as a BPSG film is about two orders of magnitude higher than the etching rate for a non-doped oxide film such as an NSG film. Becomes possible. At this time, the portion of the gate insulating film 2 that is exposed on the substrate is often removed, although it depends on the amount of over-etching.

Then, using the gate electrode 3a, the over-gate protective layer 4a and the first sidewall 15a as a mask, phosphorus ions (P ⁺ ) are implanted at an inclination angle of 7 to 40 °, an implantation energy of 20 to 30 keV, and a dose of about 5 × 10 5. ^The low-concentration source / drain region 6 is formed by implanting under the condition of ¹³ / cm ² . Note that an extension region may be formed instead of the low-concentration source / drain region 6, in which case,
Arsenic ions (As) are implanted at an energy of 10 to 20 ke.
V is implanted under the conditions of a dose of 5 × 10 ¹⁴ / cm ² .

Further, the gate electrode 3 and the protective layer 4 on the gate 4
a and the first sidewall 15a as masks, boron ions (or boron fluoride ions)
40 °, implantation energy 10 to 50 keV, dose 1
Implantation is performed under a condition of about 5 × 10 ¹³ / cm ² to form a pocket injection region Rpo for a punch-through stopper. In addition,
This pocket injection region Rpo is not always necessary.

Then, in order to activate the impurities doped in the low concentration source / drain region 6 and the pocket injection region Rpo, a second RTA is performed at 850 to 900 ° C. for 10 to 30 seconds.

Thereafter, also in the present embodiment, the self-aligned contact forming step shown in FIGS. 2A to 2C is performed as in the first embodiment.

Also in this embodiment, since the entire surface protective film 12 is deposited after removing the second side wall 16a, the same effect as in the first embodiment can be exhibited. That is, a semiconductor device having a SAC structure can be formed without filling the gap between the adjacent gate electrodes 3a with the entire surface protective film 12.

In addition, in this embodiment, the high-density source
The first RTA is performed after the drain region 9 is formed, and the second RTA is performed after the low concentration source / drain region 6 is formed.
Since the second RTA is performed at a lower temperature than the first RTA, the diffusion range of the low-concentration source / drain region 6 is narrowed as compared with the first embodiment, and an MIS transistor having high resistance to the short channel effect is formed. be able to.
That is, in order to suppress the leakage when the surface portion of the high-concentration source / drain region 9 is silicided as in the MIS transistor having a salicide structure and to reduce the junction capacitance, the high-concentration source / drain region 9 is required. Is preferably increased to some extent. However, if the heat treatment for activation is performed at a high temperature, the low-concentration source / drain region 6 (or the extension region) becomes too wide, and the short channel effect is promoted. On the other hand, as in the present embodiment, by performing heat treatment for activating the high-concentration source / drain regions 9 first, the low-concentration source / drain regions 6 (or extension regions), the pocket injection regions Rpo and the high It becomes easy to control the impurity concentration profile of the concentration source / drain region 9 to a desired state, and short channel effects such as punch-through can be reliably suppressed.

(Third Embodiment) FIGS. 5A to 6B are cross-sectional views showing steps of manufacturing an N-channel MIS transistor as a semiconductor device according to a third embodiment of the present invention. The P-channel MIS transistor also differs from the P-channel MIS transistor only in the conductivity type of the impurity doped into each part of the MIS transistor.
Are performed in the same manner as the process shown in FIG. In the present embodiment, the high concentration source
A case where a step of silicidation of the surface of the drain region is added will be described. Then, there is a silicon layer (non-silicided region) which is exposed on the substrate in the silicidation process and is not silicided on the substrate (for example, a source / drain region of a memory cell transistor).
And a manufacturing process when the present invention is applied to the silicidation region in such a case.

First, in the step shown in FIG. 5A, after forming an element isolation region (not shown) on the Si substrate 1, an MIS transistor is formed in an active region surrounded by the element isolation region by the following steps. For the process. First, a silicon oxide film having a thickness of about 3 nm is formed on the main surface of the Si substrate 1 by performing a thermal oxidation process, and then a gate insulating film 2 made of silicon oxynitride is formed by performing a nitriding process. Then, a gate electrode 3a made of polysilicon and an over-gate protection layer 4a made of silicon nitride are formed on the gate insulating film 2. At this time, although not shown, the same steps as those shown in FIG. That is, after depositing the polysilicon film and the silicon nitride film, photolithography and dry etching are performed to pattern the polysilicon film and the silicon nitride film to form the gate electrode 3a and the over-gate protection layer 4a. The gate electrode 3a
Is doped with an N-type impurity (a P-type impurity for a P-channel MIS transistor).

Next, in the step shown in FIG. 5B, a thin non-doped oxide film 15 having a thickness of 10 to 20 nm is formed on the entire surface of the substrate.
(For example, NSG film) and a doped oxide film 16 (BPSG film, PSG film, BSG film, etc.) having a thickness of 40 to 60 nm.
Are sequentially deposited.

Next, in the step shown in FIG. 5C, anisotropic etching is performed to form a first sidewall 15a and a second sidewall 16a on the side surface of the gate electrode 3a. Then, using the gate electrode 3a, the over-gate protective layer 4a and the side walls 15a and 16a as masks, arsenic ions are implanted at an inclination angle of 7 ° and an implantation energy of 30 to 50 ke.
V is implanted under the conditions of a dose of 3 to 5 × 10 ¹⁵ / cm ² to form a high concentration source / drain region 9. Thereafter, in order to activate the impurities doped in the high concentration source / drain regions 9, 900 to 1000 ° C., 10 to 3
The first RTA is performed under the condition of 0 sec.

Note that a thin nitride film may be interposed between the first sidewall 15a and the second sidewall 16a.

Next, in the step shown in FIG.
In a later silicidation step, a non-silicided region
(Not shown, for example, a memory cell array region)
Silicon oxide film with a thickness of about 100 nm for masking
17 is deposited. Then, the silicon oxide film 17 is
Before performing polishing, phosphorus ions were implanted at an inclination angle of 7 ° and implanted.
Energy is 150-200 keV, dose is 1.0 ×
10¹⁴~ 1.0 × 10 ^Fifteen/ Cm^TwoUnder the condition of
Inject into Thereby, the silicidation region shown in FIG.
In the region, the gate electrode 3a, the protective layer 4a on the gate,
And silicon in addition to the sidewalls 15a and 16a.
Since the oxide film 17 functions as a mask, the high concentration source
・ Below the drain region 9 and away from the gate electrode 3a
N in area ^-A region 18 is formed.

By providing this N ^- region 18,
Source / drain junction capacitance and leakage current can be reduced.

Next, in the step shown in FIG. 6A, the silicon oxide film 17 is patterned by etching using the photoresist film as a mask. At this time, although not shown, the silicon oxide film 17 remains in the non-silicided region, but in the silicided region shown in FIG.
Silicon oxide film 17 is removed.

Then, after forming a refractory metal film of Ti, W, etc. on the substrate, the refractory metal is reacted with silicon on the surface portion of the high-concentration source / drain region 9 by heat treatment, and the unreacted refractory metal is reacted. After the portions are removed, heat treatment is performed to change the silicide structure to a stable structure, and the high-concentration source / drain regions 9 are formed.
A silicide film 19 is formed thereon.

Next, in the step shown in FIG. 6B, only the second sidewall 16a is selectively removed while leaving the first sidewall 15a. At this time, selective etching can be easily performed by performing HF vapor phase etching. That is, in the gas phase etching of HF, the etching rate for a doped oxide film such as a BPSG film is about two orders of magnitude higher than the etching rate for a non-doped oxide film such as an NSG film. Becomes possible.

After that, using the gate electrode 3a, the over-gate protective layer 4a and the first sidewall 15a as a mask, phosphorus ions (P ⁺ ) are implanted at an inclination angle of 7 to 40 °, an implantation energy of 20 to 30 keV, and a dose of about 5 × 10 5 ^The low-concentration source / drain region 6 is formed by implanting under the condition of ¹³ / cm ² . Note that an extension region may be formed instead of the low-concentration source / drain region 6, in which case,
Arsenic ions (As) are implanted at an energy of 10 to 20 ke.
V is implanted under the conditions of a dose of 5 × 10 ¹⁴ / cm ² .

Further, the gate electrode 3 and the protective layer 4 on the gate
a and the first sidewall 15a as masks, boron ions (or boron fluoride ions)
40 °, implantation energy 10 to 50 keV, dose 1
Implantation is performed under a condition of about 5 × 10 ¹³ / cm ² to form a pocket injection region Rpo for a punch-through stopper. In addition,
This pocket injection region Rpo is not always necessary.

Then, in order to activate the impurities doped in the low concentration source / drain region 6 and the pocket injection region Rpo, a second RTA is performed at 850 to 900 ° C. for 10 to 30 seconds.

Thereafter, also in the present embodiment, the self-aligned contact forming step shown in FIGS. 2A to 2C is performed as in the first embodiment.

In the above description, the case where the silicidation process is added to the manufacturing process of the second embodiment has been described. However, the silicidation process can be added to the manufacturing process of the first embodiment. . In that case, FIG.
After the step (c), after depositing the silicon oxide film 17 and forming the N ⁻ region 18 by ion implantation, the silicon oxide film 17 is patterned. Then, FIG.
After performing the silicidation process as shown in FIG.
The process shown in FIG.

The step shown in FIG. 5D may be performed after the formation of the photoresist film covering the non-silicided region or before the formation of the photoresist film.

According to the present embodiment, the following effects can be exhibited in addition to the effects of the first and second embodiments.

That is, the non-silicided region is masked.
Immediately before patterning the silicon oxide film 17 for
Utilizing the state, below the high concentration source / drain region 9
N ^-Since the region 18 is provided, the high concentration source / drain
The surface of the region 9 is silicided to form a lead.
It is possible to suppress the problem that the current increases. Also high
Reducing the junction capacitance of the source / drain region 9
In this way, the operation speed of the MIS transistor can be increased.
Can be.

[0080]

According to the method of manufacturing a semiconductor device of the present invention, the first and second sidewalls made of materials having a high etching selectivity are laminated on the side surface of the gate electrode, and both are provided. A high-concentration impurity diffusion region is provided at a stage, and the entire protective film for forming the SAC is formed in a state where the second sidewall is removed. Therefore, a transistor having an LDD structure can be formed, and even if the distance between gate electrodes is reduced. A semiconductor device with sufficient source / drain contact can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a process of forming a low-concentration source / drain region and the like in a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a step of forming a self-aligned contact in the manufacturing steps of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a formation state of a whole surface protection film when gate electrodes are close to each other in the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a process of forming a low-concentration source / drain region and the like in a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a process of forming a semiconductor device according to a third embodiment of the present invention up to formation of an N ⁻ region for preventing leakage;

FIG. 6 is a cross-sectional view showing a silicidation process in a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device having a general self-aligned contact structure.

FIG. 8 is a cross-sectional view showing a defect of a semiconductor device formed by a conventional manufacturing process of a semiconductor device having a general self-aligned contact structure.

FIG. 9 is a cross-sectional view showing a part of a manufacturing process of a semiconductor device when a conventional entire surface nitride film is provided.

FIG. 10 is a cross-sectional view showing a state of formation of a nitride film covering the entire surface when gate electrodes are close to each other in a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Si substrate 2 Gate oxide film 3a Gate electrode 4a Protective layer on a gate 6 Low-concentration source / drain region 9 High-concentration source / drain region 10 Interlayer insulating film 11 Plug electrode 12 Full-surface protective film 15 Non-doped oxide film 15a First sidewall 16 Doped oxide film 16a Second sidewall 17 Silicon oxide film 18 N ^- region 19 Silicide film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takehiko Ueda 1-1, Sachimachi, Takatsuki-shi, Osaka Prefecture Matsushita Electronics Corporation Inside (72) Taimi Shimizu 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics Industry Co., Ltd. (72) Inventor Yoshiaki Kato 1-1, Yukicho, Takatsuki-shi, Osaka Prefecture Matsushita Electronics Co., Ltd. Inside (72) Inventor Tatsuya 1-1, Yukicho, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. (72) Inventor Toyoyuki Shimazaki 1-1, Sachimachi, Takatsuki City, Osaka Prefecture Matsushita Electronics Corporation

Claims (10)

[Claims] A step of forming a gate insulating film, a gate electrode, and a protective layer on a gate on a semiconductor substrate; and a step of forming a low concentration impurity in the semiconductor substrate using the gate electrode and the protective layer on the gate as a mask. A step (b) of performing ion implantation for forming a diffusion region; and a step of depositing, on a substrate, a first insulating film and a mask film that can be selectively etched with respect to the first insulating film. (C) performing anisotropic etching of the first insulating film and the mask film to leave a portion of the first insulating film on the side surfaces of the gate electrode and the over-gate protective layer; (D) forming a second sidewall while leaving a portion of the mask film on the side surface of the first sidewall, and forming the second sidewall, And each sidewall As a mask, the step of performing the ion implantation for forming the high concentration impurity diffusion region in the semiconductor substrate (e)
And (f) after the step (e), selectively removing the second sidewall while leaving the first sidewall.
(G) depositing a second insulating film covering at least the protective layer on the gate and the first sidewall on the substrate after the step (f); (H) depositing an interlayer insulating film made of a material that can be selectively etched with respect to the second insulating film, and an opening reaching the high-concentration impurity diffusion region in the interlayer insulating film by etching. And a step (j) of embedding a plug electrode made of a conductive material in the opening. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (c), an NSG film is formed as the first insulating film, and a PSG film or a BPSG film is formed as the mask film. A method for manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 2, wherein the step (f) is performed by HF vapor phase etching. 4. The method of manufacturing a semiconductor device according to claim 1, wherein after the step (f) and before the step (g), the protective layer on the gate, the gate electrode, and A method of manufacturing a semiconductor device, further comprising a step of performing ion implantation for forming a pocket implantation region in the semiconductor substrate using the first sidewall as a mask. 5. The method of manufacturing a semiconductor device according to claim 1, wherein after the step (e) and before the step (f), a non-silicide is formed on the substrate. Forming a protective film serving as a mask for the region; forming a low-concentration impurity diffusion region for preventing leakage below the high-concentration impurity diffusion region using the protective film as a mask; A step of selectively removing a portion covering the silicidation region while leaving a portion covering the silicidation region; and a step of forming a silicide layer on the surface of the high concentration impurity diffusion region. Manufacturing method. 6. A step (a) of forming a gate insulating film, a gate electrode, and a protective layer on a gate on a semiconductor substrate, and selecting a first insulating film and the first insulating film on the substrate. Step (b) of depositing an etchable mask film
Performing anisotropic etching of the first insulating film and the masking film to leave a part of the first insulating film on the side surfaces of the gate electrode and the over-gate protective layer; (C) forming a second sidewall while leaving a part of the mask film on the side surface of the first sidewall; and forming the above-mentioned protective layer on the gate, a gate electrode and each side. Performing ion implantation for forming a high-concentration impurity diffusion region in the semiconductor substrate using the wall as a mask (d).
And (e) after the step (d), selectively removing the second sidewall while leaving the first sidewall.
(F) performing ion implantation for forming a low-concentration impurity diffusion region in the semiconductor substrate using the gate electrode, the over-gate protection layer, and the first sidewall as a mask; A) depositing a second insulating film covering at least the protective layer on the gate and the first sidewall on the substrate; and g) depositing the second insulating film on the substrate after the step (g). (H) depositing an interlayer insulating film made of a material that can be selectively etched with respect to the insulating film, and forming an opening in the interlayer insulating film by etching to reach the high concentration impurity diffusion region (i). ) And a step (j) of embedding a plug electrode made of a conductive material in the opening. 7. The method of manufacturing a semiconductor device according to claim 6, wherein in the step (b), an NSG film is formed as the first insulating film, and a PSG film or a BPSG film is formed as the mask film. A method for manufacturing a semiconductor device, comprising: 8. The method for manufacturing a semiconductor device according to claim 7, wherein the step (e) is performed by HF vapor phase etching. 9. The method of manufacturing a semiconductor device according to claim 6, wherein after the step (e) and before the step (g), the protective layer on the gate, the gate electrode, and A method of manufacturing a semiconductor device, further comprising a step of performing ion implantation for forming a pocket implantation region in the semiconductor substrate using the first sidewall as a mask. 10. The method of manufacturing a semiconductor device according to claim 6, wherein after the step (d) and before the step (f), a non-silicide is formed on the substrate. Forming a protective film serving as a mask for the region; forming a low-concentration impurity diffusion region for preventing leakage below the high-concentration impurity diffusion region using the protective film as a mask; A step of selectively removing a portion covering the silicidation region while leaving a portion covering the silicidation region; and a step of forming a silicide layer on the surface of the high concentration impurity diffusion region. Manufacturing method.