JP3363802B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art With the progress of microfabrication technology for MOSLSI, the capacity has been increased and the chip size has been reduced.

A conventional method of manufacturing a MOS transistor will be described with reference to FIGS. 7 to 12 show M
FIG. 6 is a process sectional view of an OS transistor element.

First, in a step shown in FIG. 7A, a gate oxide film (200) is formed on a p-type region of a silicon substrate (100) by thermal oxidation.

Subsequently, in a step shown in FIG. 7B, a polysilicon Poly-Si (301) film having a thickness of about 1000 Å is formed on the gate oxide film (200) by low pressure CVD, and thermal diffusion of POCl 3 is performed. To perform phosphorus dope. Furthermore, on the Poly-Si (301), low voltage CV
D is used to form a tungsten silicide WSi2 (302) in a thickness of about 1000Å.

Next, in the step shown in FIG.
A silicon oxide film (400) formed by low pressure decomposition of TEOS (tetraethoxysilane) on Si2 (302)
It is formed to a thickness of 00 to 2000Å. This silicon oxide film (400) will later become a hard mask.

Then, in the step shown in FIG.
On the silicon oxide film (400), BARC (bottom anti
A reflective coat) film (500) is formed. this is,
An organic film having a flattening action, which flattens surface irregularities (not shown) due to a field oxide film or the like.

In the step shown in FIG. 8 (e), the BARC
A resist (R1) for forming a gate electrode is formed on the film (500). Here, BARC film (500)
Since the surface is flattened by providing the film, the line width accuracy of the resist (R1) is improved.

In the step shown in FIG. 9F, the hard mask (401) is formed by etching the BARC film (500) and the silicon oxide film (400) using this resist (R1) as a mask. Hard mask (40
1) The BARC film (500) that remained in the same shape on the
It is removed together when the resist (R1) is peeled off.

In the step shown in FIG. 9G, the hard mask (401) is used as a mask and WSi 2 (302) / Po is used.
By etching ly-Si (301), W
A gate electrode (300) made of Si2 / Poly-Si, that is, a polycide layer is formed. A halogen-based gas is used as the etching gas.

Here, the etching of the gate electrode (300) using the hard mask (401) is one of the elemental techniques of the ultrafine processing technique. In the anisotropic dry etching, the mask material reacts with the etching gas to generate a deposit on the side wall of the film to be etched, which functions as an etching stop film to suppress the side etch to a small extent. In this case, WSi2 (30) is better when the hard mask (401) whose material is selected is used as the mask than when the resist which is the photosensitive resin is used.
2) The side wall deposited material of the gate electrode (300) composed of / Poly-Si (301) has a large effect of preventing etching, and the processing accuracy is high. Similarly, etching the hard mask (401) is more effective than etching the gate electrode (300) using a resist of photosensitive resin.
High accuracy.

In the step shown in FIG. 10H, ion implantation is performed using the hard mask (401) and the gate electrode (300) as a mask. Ion implantation is performed, for example, by ion-implanting phosphorus showing an n-type with a low dose amount of 10 <13>. As a result, a low concentration region (10) is formed in a region of the silicon substrate (100) other than directly under the gate electrode (300).
1) is formed. The region directly under the gate electrode (300) is
It becomes a p-type channel region.

In the ultra-miniaturized structure, the gate electrode (3
00) is WSi2 (302) / Poly-Si (30)
The thickness of 1) is as thin as 1000Å / 1000Å. this is,
This is because the thicker the film, the larger the side-etching amount and the lower the accuracy, and the smaller the unevenness and the higher the flatness and flatness. As described above, when the gate electrode (300) is thin, ions may penetrate through the mask during ion implantation. However, by using a hard mask (401) stacked on the gate electrode (300) as a mask, , Ions penetrate the mask, and the silicon substrate (1
00) can be prevented.

In the step shown in FIG. 10I, a silicon oxide film is formed on the entire surface and the entire surface is etched back, so that the gate electrode (300) and the hard mask (40) are formed.
A spacer (600) is formed on the side wall of 1). This time,
The gate oxide film (200) other than the gate electrode (300) and the sidewall spacers (600) is also removed to expose the surface of the silicon substrate (100).

In the step shown in FIG. 11 (j), a protective film (700) made of a silicon oxide film is formed on the entire surface by 200
After forming to a thickness of Å, this time, the side wall spacer (60
0) is added to the mask, and phosphorus is ion-implanted at a high dose of about 10 15 to form a high concentration region (102) in a region other than the sidewall spacers (600). The low-concentration region (101) remains in the region immediately below the sidewall spacer (600). As a result, source and drain regions (102) composed of high concentration regions are formed on both sides of the channel region (103) with the low concentration region (101) interposed therebetween. Such a structure has an LDD (lightly doped dra
in) is called. The protective film (700) prevents the surface of the silicon substrate (100) from being contaminated by impurities other than phosphorus.

In the step shown in FIG. 11K, a silicon nitride film (801) having a thickness of 300Å and a silicon oxide film (802) having a thickness of 2000Å are formed on the entire surface to form an interlayer insulating film.

In the step shown in FIG. 12 (l), a resist (R2) for forming a contact hole (CT) is formed on the interlayer insulating film (802).

In the step shown in FIG. 12 (m), the resist (R2) is used as a mask to form the interlayer insulating films (801, 80).
By forming the contact hole (CT) by performing the etching of 2), a film of Al or the like is formed by sputtering, and by etching this, a wiring electrode (900) connected to the source / drain region (102). To form. The contact hole (CT) is formed larger. The contact hole (CT) is formed by utilizing the etching selection ratio of the interlayer insulating film (802) made of a silicon oxide film, the interlayer insulating film (801) made of a silicon nitride film, and the protective film (700) made of a silicon oxide film. Done. That is, during etching, the sidewall spacer (600) and the hard mask (401) covering the gate electrode (300) are exposed until the valley bottom of the protective film (700) is exposed.
It remains while being protected by the protective film (700).
Then, the protective film (700) is removed by etching to expose the source and drain regions (102).

The structures given here are SAC (self align
contact) and is used in an ultrafine structure with a channel length of about 0.35 μm. Contact hole (C
T) is slightly opened, and even if the position of the resist (R2) is displaced and the position of the contact hole (CT) is displaced in the step shown in FIG. The wiring electrode (900) and the source / drain regions (10) are not completely separated from (102).
The contact with 2) is made possible.

[0020]

In the etching process shown in FIG. 9 (g), in the etching using the hard mask (401), the gate electrode (3) which is the film to be etched is formed.
00) can be patterned with high precision, but the hard mask (401) reacts with the etching gas and shrinks, causing film loss. That is, compared to the resist, the hard mask (401) and the film to be etched, WSi2
The etching selectivity of (302) / Poly-Si (301) is small. The hard mask (401) is shown in FIG.
(H) and also as a mask in the ion implantation step shown in FIG. 11 (j), when the film thickness of the hard mask (401) is reduced, phosphorus ions penetrate the mask and are counter-doped into the channel region (103), Change in threshold,
The element characteristics are changed, such as reduction of the on / off ratio.

Further, in the SAC structure, FIG.
As shown in (m), the hard mask (401) also serves as an interlayer insulating layer between the gate electrode (300) and the wiring electrode (900), and when the film thickness of the hard mask (401) is reduced, This causes a short circuit between the sources and between the gate and drain.

Further, in order to solve these problems, if the hard mask (401) is thickened, this time,
The side etch amount of the hard mask (401) increases,
The accuracy of forming the hard mask (401) decreases.

Further, the resist (R1) shown in FIG.
Since the BARC film (500) is formed in the forming step, the line width accuracy is good. However, although the BARC film (500) is etched using oxygen,
Since the side etch occurs, the BARC film (501) is formed smaller than the mask pattern. Therefore, although the target line width is obtained by forming the mask pattern in advance in a large size, there is often no room for forming the mask pattern in such a large size in the ultrafine structure. When the BARC film (501) is not used, since the lower silicon oxide film (400) is transparent, light scattering occurs in the lower layer of the resist (R1) during exposure, and the edge of the resist (R1) is blurred. , Hinders ultra-fine processing.

[0024]

SUMMARY OF THE INVENTION The present invention has been made to solve this problem and is a semiconductor having a semiconductor layer on a substrate and a gate electrode formed facing the semiconductor layer with a gate insulating film interposed therebetween. In the method of manufacturing a device, a step of forming a first mask layer and a second mask layer on the conductive film layer to be the gate electrode, and using the first mask layer and the second mask layer as a mask, A step of forming the gate electrode by etching the conductive film layer, and ion implantation of impurities using the first mask layer and the gate electrode as a mask to form an impurity implantation region in the semiconductor layer. And a step of performing.

As a result, since the first mask layer is protected by the second mask layer, the first mask layer does not shrink due to the etching gas during the etching of the gate electrode, and therefore, By etching the gate electrode using the first mask layer, highly precise patterning becomes possible.

In particular, the second mask layer is removed when the conductive film layer is etched.

As a result, after the completion of the device, the unnecessary second
No mask layer remains.

In particular, the conductive film layer is made of a polycide layer, and the second mask layer is made of a polysilicon layer.

As a result, since the second mask layer reflects light, a resist for forming the second mask layer is formed with a clear edge.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION MO according to an embodiment of the present invention
A method of manufacturing the S transistor element will be described with reference to process sectional views of FIGS.

First, in the step shown in FIG. 1A, a gate oxide film (20) is formed on a p-type region of a silicon substrate (10) by thermal oxidation.

Then, in the step shown in FIG. 1B, a polysilicon Poly-Si (31) film is formed on the gate oxide film (20) by low pressure CVD to a thickness of about 1000 Å, and POCl 3 is thermally diffused. To perform phosphorus dope. Furthermore, a tungsten silicide WSi2 (32) of 1000 Å is formed on the Poly-Si (31) by low pressure CVD.
The film is formed to a thickness of about.

Next, in the step shown in FIG.
A silicon oxide film (40) of 100 is formed on the Si2 (32) by low pressure decomposition of TEOS (tetraethoxysilane).
It is formed to a thickness of 0 to 2000Å. This silicon oxide film (40) will later become a hard mask.

Then, in the step shown in FIG. 2D, on the silicon oxide film (40), Poly-Si (50) which is the compensation film (51) of the present invention is 2000 Å or less, for example, 1000 Å in thickness. To form. This Poly-Si
(50) is Poly-Si (31) which is a gate electrode
It can be formed by the same low-pressure CVD method as described above, but phosphorus doping is unnecessary.

In the step shown in FIG. 2 (e), Poly
A resist (R1) for forming a gate electrode is formed on -Si (50). Since the Poly-Si (50) reflects light, the light interference in the lower layer of the resist (R1) is suppressed during the exposure of the resist (R1), so that the edge of the obtained resist (R1) becomes clear and the pattern of High accuracy.

In the step shown in FIG. 3F, the Poly-Si (50) and the silicon oxide film (40) are etched by using the resist (R1) as a mask to thereby form the hard mask (41) and its compensation film (41). 51) is formed. A halogen-based gas is used as the etching gas for the Poly-Si (50), and a fluorine-based gas is used as the etching gas for the silicon oxide film (40), and there is no side etching. Therefore, these compensation film (51) / hard mask (41) are formed with high accuracy. In particular, the hard mask (41) directly affects the processing accuracy of the gate electrode (30), but since the film thickness is not large, it is patterned with high accuracy.

In the step shown in FIG. 3G, WSi 2 is used with the hard mask (41) and the compensation film (51) as masks.
A gate electrode (30) of polycide is formed by etching (32) / Poly-Si (31). A halogen gas is used as an etching gas, and there is no side etching, and the gate electrode (30) is formed with high precision.

In this step, the compensation film (51) is etched by the etching gas and the gate electrode (3
Since it is formed thinner than the (0) film, the gate electrode (3
WSi2 (32) / Poly-Si (31) other than 0)
Is completely removed together with. During most of this etching, the hard mask (41) is protected by the compensation film (51) and is not exposed to the etching gas,
Film loss is prevented.

In the step shown in FIG. 4H, ion implantation is performed using the hard mask (41) and the gate electrode (30) as masks. Ion implantation is performed, for example, by ion-implanting phosphorus showing an n-type with a low dose amount of 10 <13>. As a result, the n − -type low concentration region (11) is formed in the region of the silicon substrate (10) other than directly under the gate electrode (30).
To form. The region directly under the gate electrode (30) becomes a p-type channel region.

In the ultra-miniaturized structure, the gate electrode (3
In 0), the thickness of WSi2 (32) / Poly-Si (31) is as thin as 1000Å / 1000Å and ions may pass through the mask during ion implantation. By using the layered mask (41), it is possible to prevent ions from penetrating the mask and being implanted into the silicon substrate (10). Particularly, in the present invention, the hard mask (4
In 1), the film loss is prevented and the thickness is sufficient in the process of FIG. 3 (g) described above, so that the effect of preventing punch-through becomes remarkable.

In the step shown in FIG. 4 (i), a silicon oxide film is formed on the entire surface and the entire surface is etched back to form spacers (60) on the side walls of the gate electrode (30) and the hard mask (41). To do. At this time, the gate oxide film (20) other than the gate electrode (30) and the sidewall spacers (60) is also removed, and the surface of the silicon substrate (10) is exposed.

In the step shown in FIG. 5 (j), the entire surface is
After forming a protective film (70) made of a silicon oxide film to a thickness of 200Å, this time add a sidewall spacer (50) to the mask and perform phosphorus ion implantation at a high dose amount of about 10 15th power. The gate electrode (30),
An n + type high concentration region (12) is formed in a region other than the sidewall spacers (50). The low-concentration region (11) remains in the region immediately below the sidewall spacer (50). As a result, the source and drain regions composed of the high-concentration regions (12) are formed on both sides of the channel region (13) with the low-concentration regions (11) interposed therebetween.

In the step shown in FIG. 5K, the entire surface is
300 Å thick silicon nitride film (81) and thickness 20
A 00Å silicon oxide film (82) is formed to form an interlayer insulating film.

In the step shown in FIG. 6L, a resist (R2) for forming a contact hole (CT) is formed on the interlayer insulating film (82).

In the step shown in FIG. 6 (m), the contact hole (CT) is formed by etching the interlayer insulating film (81, 82) using the resist (R2) as a mask.
After forming, a film of Al or the like is formed by sputtering,
By etching this, a wiring electrode (90) connected to the source / drain region (12) is formed.

The contact hole (CT) is formed by etching between the interlayer insulating film (82) made of a silicon oxide film, the interlayer insulating film (81) made of a silicon nitride film, and the protective film (70) made of a silicon oxide film. It is performed by utilizing the selection ratio. That is, during etching, the sidewall spacer (60) and the hard mask (41) covering the gate electrode (30) are protected by the protective film (70) until the bottom of the protective film (70) is exposed. And remains. afterwards,
The protective film (70) is removed by etching.

[0047]

As is apparent from the above description, according to the present invention, in the method of manufacturing a semiconductor device of ultrafine processing using the hard mask for etching the gate electrode, the mask for ion implantation is used for etching the gate electrode. Since the film thickness of the hard mask, which also serves as a mask, is not reduced, counter-doping of the channel region due to ion penetration is prevented, and the electrical characteristics of the obtained semiconductor element are improved.

Even in the structure in which the contact with the wiring electrode is formed by self-alignment, the film thickness of the hard mask that also serves as an interlayer insulating layer between the wiring electrode and the gate electrode is not reduced, so that the wiring electrode and the gate electrode are not reduced. Short circuit with was prevented.

Further, since these effects are realized without increasing the thickness of the hard mask, further miniaturization is possible.

Further, the compensation film is made of Poly having a reflectance.
By forming with —Si, the edge of the resist for etching the compensation film becomes clear and the accuracy is further improved.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a process cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 4 is a process sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a process sectional view showing the method of manufacturing a semiconductor device according to the embodiment of the invention.

FIG. 6 is a process cross-sectional view showing the method of manufacturing a semiconductor device according to the embodiment of the present invention.

7A to 7D are process cross-sectional views showing a conventional method for manufacturing a semiconductor device.

FIG. 8 is a process cross-sectional view showing a conventional method of manufacturing a semiconductor device.

FIG. 9 is a process cross-sectional view showing the method of manufacturing a conventional semiconductor element.

10A to 10D are process cross-sectional views showing a conventional method for manufacturing a semiconductor device.

FIG. 11 is a process sectional view showing the method of manufacturing a conventional semiconductor device.

FIG. 12 is a process sectional view showing the method of manufacturing a conventional semiconductor element.

[Explanation of symbols]

10 Silicon substrate 20 Gate oxide film 30 gate electrode 40 hard mask 50 compensation film 60 spacers 70 Protective film 81,82 Interlayer insulation film 90 wiring electrodes

Continuation of the front page (56) Reference JP-A-7-78987 (JP, A) JP-A-59-217328 (JP, A) JP-A-4-30428 (JP, A) JP-A-6-275574 (JP , A) JP-A-9-246206 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/085-21/092 H01L 21/8234-21/8238 H01L 29/78 H01L 21/336 H01L 21/3065 H01L 21/28-21/288

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor device, comprising: a semiconductor layer on a substrate; and a gate electrode formed to face the semiconductor layer with a gate insulating film interposed therebetween. Forming a first mask layer and a second mask layer, and forming a resist having a predetermined pattern on the second mask layer
And a step of forming the first and second mask layers using the resist as a mask.
Form the hard mask and compensation film by etching
And a step of forming the conductive film layer on which the hard mask is formed.
A step of forming the gate electrode by etching together with a compensation film, and a step of forming an impurity implantation region in the semiconductor layer by performing ion implantation of impurities using the hard mask and the gate electrode as masks. A method of manufacturing a semiconductor device, comprising: 2. The conductive film layer comprises a polycide layer,
The method of manufacturing a semiconductor device according to claim 1, wherein the second mask layer is made of a polysilicon layer.