JP2000100965A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a superfine MOS transistor. SOLUTION: A compensating film 51 is formed on a hard mask 41 used for etching a gate electrode 30. The compensating film 51 is formed of poly-Si the same as the gate electrode 30 is formed of Poly-Si, and the compensating film 51 is completely removed off while etching is carried out. The hard mask 41 is not exposed to the etching gas and prevented from being lessened in thickness while etching is carried out. Therefore, the mask 41 is enhanced in masking effect to prevent ions from penetrating through it when ions are injected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art With the development of MOS LSI microfabrication technology, large capacity and small chip size have been developed.

A conventional method for manufacturing a MOS transistor will be described with reference to FIGS. FIG. 7 to FIG.
It is a process sectional view of an OS transistor element.

First, in a step shown in FIG. 7A, a gate oxide film (200) is formed on a p-type region of a silicon substrate (100) by thermal oxidation.

Subsequently, in a step shown in FIG. 7B, a polysilicon Poly-Si (301) is formed on the gate oxide film (200) to a thickness of about 1000 ° by low pressure CVD, and thermal diffusion of POCl 3 is performed. To do phosphorus doping. Furthermore, a low pressure CV is placed on the Poly-Si (301).
D is used to deposit tungsten silicide WSi2 (302) to a thickness of about 1000 °.

Next, in the step shown in FIG.
A silicon oxide film (400) formed by low pressure decomposition of TEOS (tetraethoxysilane) is
It is formed to a thickness of 00 to 2000 mm. This silicon oxide film (400) will later become a hard mask.

Then, in the step shown in FIG.
BARC (bottom anti) on the silicon oxide film (400)
reflective coat) to form a film (500). this is,
An organic film having a flattening action, which flattens irregularities on the surface due to a field oxide film or the like (not shown).

In the step shown in FIG.
A resist (R1) for forming a gate electrode is formed on the film (500). Here, the BARC film (500)
Since the surface is flattened by providing the film, the line width accuracy of the resist (R1) is improved.

In the step shown in FIG. 9F, a hard mask (401) is formed by etching the BARC film (500) and the silicon oxide film (400) using the resist (R1) as a mask. Hard mask (40
1) The BARC film (500) remaining in the same shape on the
When the resist (R1) is peeled off, it is removed together.

In the step shown in FIG. 9 (g), using the hard mask (401) as a mask, WSi2 (302) / Po
By etching ly-Si (301), W
A gate electrode (300) made of Si2 / Poly-Si, that is, a polycide layer is formed. As an etching gas, a halogen-based gas is used.

Here, the etching of the gate electrode (300) using the hard mask (401) is one of the elemental technologies of the ultrafine processing technology. In the anisotropic dry etching, a reaction between the mask material and the etching gas generates a deposit on the side wall of the film to be etched, which functions as an etching stopper film, thereby suppressing side etching to a small value. In this case, it is better to use a hard mask (401) of a selected material than to use a resist which is a photosensitive resin as a mask.
2) The gate electrode (300) made of / Poly-Si (301) has a large effect of preventing the deposit on the side wall and has a high processing accuracy. Similarly, etching the hard mask (401) is more effective than etching the gate electrode (300) using a photosensitive resin resist.
High accuracy.

In the step shown in FIG. 10H, ion implantation is performed using the hard mask (401) and the gate electrode (300) as masks. The ion implantation is performed, for example, by implanting n-type phosphorus ions at a low dose of 10 13. As a result, the low-concentration regions (10
Form 1). The region immediately below the gate electrode (300)
It becomes a p-type channel region.

In the ultra-miniaturized structure, the gate electrode (3
00) is WSi2 (302) / Poly-Si (30
The thickness of 1) is as thin as 1000 ° / 1000 °. this is,
If the film is thicker, the amount of side etching becomes larger and the accuracy is reduced, and the unevenness is reduced to improve the flatness. As described above, when the gate electrode (300) is thin, ions may pass through the mask at the time of ion implantation. However, by using a mask in which a hard mask (401) is stacked on the gate electrode (300), the mask is used. , Ions penetrate through the mask and form a silicon substrate (1
00) can be prevented.

In the step shown in FIG. 10I, a silicon oxide film is formed on the entire surface, and the entire surface is etched back to thereby form the gate electrode (300) and the hard mask (40).
A spacer (600) is formed on the side wall of 1). At this time,
The gate oxide film (200) other than the gate electrode (300) and the side wall spacer (600) is also removed, exposing the surface of the silicon substrate (100).

In the step shown in FIG. 11 (j), a protective film (700) made of a silicon oxide film
厚 み, and then the side wall spacer (60
0) is added to the mask, and phosphorus ion implantation is performed at a high dose of about 10 15 to form a high-concentration region (102) in a region other than the sidewall spacer (600). The low concentration region (101) remains in the region directly below the sidewall spacer (600). As a result, source and drain regions (102) composed of high concentration regions are formed on both sides of the channel region (103) with the low concentration region (101) interposed therebetween. Such a structure is called LDD (lightly doped dra
in). The protective film (700) prevents the surface of the silicon substrate (100) from being contaminated by impurities other than phosphorus.

In the step shown in FIG. 11 (k), a 300 nm thick silicon nitride film (801) and a 2000 mm thick silicon oxide film (802) are formed on the entire surface to form an interlayer insulating film.

In the step shown in FIG. 12 (l), a resist (R2) for forming a contact hole (CT) is formed on the interlayer insulating film (802).

In the step shown in FIG. 12 (m), the interlayer insulating films (801, 80) are formed using the resist (R2) as a mask.
After the contact hole (CT) is formed by performing the etching of 2), a film of Al or the like is formed by sputtering, and this is etched to form the wiring electrode (900) connected to the source / drain region (102). To form The contact hole (CT) is formed relatively large. The formation of the contact hole (CT) utilizes the etching selectivity of an interlayer insulating film (802) made of a silicon oxide film, an interlayer insulating film (801) made of a silicon nitride film, and a protective film (700) made of a silicon oxide film. It is done. That is, during the etching, until the valley bottom of the protective film (700) is exposed, the side wall spacer (600) and the hard mask (401) covering the gate electrode (300) are removed.
It remains in a state protected by the protective film (700).
After that, the protective film (700) is removed by etching to expose the source and drain regions (102).

The structure described here is based on SAC (self align).
This is used in an ultrafine structure having a channel length of about 0.35 μm. Contact hole (C
T) is opened large, and in the step shown in FIG. 12 (l), even if the position of the resist (R2) is shifted and the position of the contact hole (CT) is shifted as shown in the figure, the source / drain region Without completely deviating from (102), the wiring electrode (900) and the source / drain region (10
2) can be obtained.

[0020]

In the etching step shown in FIG. 9 (g), in the etching using the hard mask (401), the gate electrode (3) which is a film to be etched is formed.
00) can be patterned with high precision, but the hard mask (401) reacts with the etching gas and shrinks, resulting in film thinning. That is, as compared with the resist, the hard mask (401) and the WSi2
The etching selectivity of (302) / Poly-Si (301) is small. The hard mask (401) is shown in FIG.
(H) and also serves as a mask in the ion implantation step shown in FIG. 11 (j). When the film thickness of the hard mask (401) is reduced, phosphorus ions penetrate the mask and are counter-doped into the channel region (103). Fluctuation of the threshold,
Device characteristics such as a reduction in on / off ratio are changed.

In the SAC structure, FIG.
As shown in (m), the hard mask (401) also serves as an interlayer insulating layer between the gate electrode (300) and the wiring electrode (900). This causes a short circuit between the source and the gate / drain.

Further, in order to solve these problems, when the hard mask (401) is made thicker, this time,
The side etch amount of the hard mask (401) increases,
The precision of forming the hard mask (401) is reduced.

The resist (R1) shown in FIG.
In the forming process, the line width accuracy is good because the film is formed on the BARC film (500). However, the BARC film (500) is etched using oxygen,
Since side etching occurs, the BARC film (501) is formed smaller than the mask pattern. Therefore, a target line width is obtained by forming a large mask pattern in advance, but there is often no room for forming a large mask pattern in an ultrafine structure. When the BARC film (501) is not used, since the underlying silicon oxide film (400) is transparent, light scattering occurs at the lower layer of the resist (R1) during exposure, and the edge of the resist (R1) is blurred. Hamper ultra-fine processing.

[0024]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has been made in order to solve the above-mentioned problem, and has a semiconductor having a semiconductor layer on a substrate and a gate electrode formed opposite to the semiconductor layer with a gate insulating film interposed therebetween. In the method for manufacturing a device, a step of forming a first mask layer and a second mask layer on a conductive film layer serving as the gate electrode; and using the first mask layer and the second mask layer as masks, Forming the gate electrode by etching the conductive film layer and forming an impurity-implanted region in the semiconductor layer by performing impurity ion implantation using the first mask layer and the gate electrode as a mask; And a step of performing

Thus, since the first mask layer is protected by the second mask layer, the first mask layer is not reduced by the etching gas during the etching of the gate electrode. By etching the gate electrode using the first mask layer, highly accurate patterning becomes possible.

In particular, the second mask layer is removed when the conductive film layer is etched.

Thus, after completion of the apparatus, unnecessary second
No mask layer remains.

In particular, the conductive film layer is composed of a polycide layer, and the second mask layer is composed of a polysilicon layer.

As a result, since the second mask layer reflects light, a resist for forming the second mask layer is formed with a clear edge.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS MO according to an embodiment of the present invention
A method for manufacturing the S transistor element will be described with reference to the process sectional views of FIGS.

First, in the step shown in FIG. 1A, a gate oxide film (20) is formed on a p-type region of a silicon substrate (10) by thermal oxidation.

Subsequently, in the step shown in FIG. 1B, a polysilicon Poly-Si (31) is formed on the gate oxide film (20) to a thickness of about 1000 ° by low pressure CVD, and thermal diffusion of POCl 3 is performed. To do phosphorus doping. Further, tungsten silicide WSi2 (32) is deposited on the poly-Si (31) by low pressure CVD at 1000Å.
The film is formed to a thickness of about the same.

Next, in the step shown in FIG.
A silicon oxide film (40) is formed on Si2 (32) by low pressure decomposition of TEOS (tetraethoxysilane).
It is formed to a thickness of 0 to 2000 mm. This silicon oxide film (40) will later become a hard mask.

Then, in the step shown in FIG. 2D, a poly-Si (50) serving as a compensating film (51) of the present invention is formed on the silicon oxide film (40) to a thickness of 2000 ° or less, for example, 1000 °. Formed. This Poly-Si
(50) Poly-Si (31) as a gate electrode
Can be formed by the same low-pressure CVD as described above, but phosphorus doping is not required.

In the step shown in FIG.
-A resist (R1) for forming a gate electrode is formed on the Si (50). Since the Poly-Si (50) reflects light, the light interference in the lower layer of the resist (R1) is suppressed when exposing the resist (R1), so that the edge of the obtained resist (R1) becomes clear, and High accuracy.

In the step shown in FIG. 3F, the poly-Si (50) and the silicon oxide film (40) are etched using the resist (R1) as a mask, thereby forming a hard mask (41) and its compensation film ( 51) is formed. The etching gas for the Poly-Si (50) uses a halogen-based gas, and the etching gas for the silicon oxide film (40) uses a fluorine-based gas, and there is no side etching. Therefore, the compensation film (51) and the hard mask (41) are formed with high precision. In particular, the hard mask (41) directly affects the processing accuracy of the gate electrode (30), but is patterned with high precision because the thickness is not increased.

In the step shown in FIG. 3 (g), the hard mask (41) and the compensation film (51) are used as masks to form WSi2
(32) / Poly-Si (31) is etched to form a polycide gate electrode (30). As the etching gas, a halogen gas is used, there is no side etching, and the gate electrode (30) is formed with high precision.

In this step, the compensation film (51) is etched by the etching gas and the gate electrode (3) is etched.
0) Since it is formed thinner than the film, the gate electrode (3
WSi2 (32) other than 0) / Poly-Si (31)
It is completely removed with. During most of this etching, the hard mask (41) is protected by the compensation film (51) and is not exposed to the etching gas,
Film loss is prevented.

In the step shown in FIG. 4H, ion implantation is performed using the hard mask (41) and the gate electrode (30) as masks. The ion implantation is performed, for example, by implanting n-type phosphorus ions at a low dose of 10 13. Thereby, the n − -type low-concentration region (11) is formed in the region of the silicon substrate (10) other than immediately below the gate electrode (30).
To form The region immediately below the gate electrode (30) becomes a p-type channel region.

In the ultra-miniaturized structure, the gate electrode (3
In (0), the thickness of WSi2 (32) / Poly-Si (31) is as thin as 1000/1000, and ions may pass through the mask during ion implantation. The use of a stacked mask (41) can prevent ions from penetrating through the mask and being implanted into the silicon substrate (10). In particular, in the present invention, the hard mask (4
In the case of 1), since the film is prevented from being reduced in the step of FIG. 3G and has a sufficient thickness, the effect of preventing penetration is remarkable.

In the step shown in FIG. 4I, a spacer (60) is formed on the side walls of the gate electrode (30) and the hard mask (41) by forming a silicon oxide film on the entire surface and performing etch back on the entire surface. I do. At this time, the gate oxide film (20) other than the gate electrode (30) and the side wall spacer (60) is also removed, exposing the surface of the silicon substrate (10).

In the step shown in FIG.
After a protective film (70) made of a silicon oxide film is formed to a thickness of 200 °, a sidewall spacer (50) is added to a mask, and phosphorus ion implantation is performed at a high dose of about 10 15. Thereby, the gate electrode (30),
An n + type high concentration region (12) is formed in a region other than the side wall spacer (50). The low concentration region (11) remains in the region directly below the side wall spacer (50). As a result, source and drain regions composed of the high concentration region (12) are formed on both sides of the channel region (13) with the low concentration region (11) interposed therebetween.

In the step shown in FIG.
Silicon nitride film (81) having a thickness of 300 ° and a thickness of 20
A silicon oxide film (82) of 00 ° is formed, and an interlayer insulating film is formed.

In the step shown in FIG. 6 (l), a resist (R2) for forming a contact hole (CT) is formed on the interlayer insulating film (82).

In the step shown in FIG. 6 (m), the interlayer insulating films (81, 82) are etched using the resist (R2) as a mask to form contact holes (CT).
After forming, a film of Al or the like is formed by sputtering,
By etching this, a wiring electrode (90) connected to the source / drain region (12) is formed.

The contact hole (CT) is formed by etching between an interlayer insulating film (82) made of a silicon oxide film, an interlayer insulating film (81) made of a silicon nitride film, and a protective film (70) made of a silicon oxide film. This is performed using the selection ratio. That is, the sidewall spacer (60) and the hard mask (41) covering the gate electrode (30) are protected by the protective film (70) until the bottom of the protective film (70) is exposed during the etching. And survive. afterwards,
The protective film (70) is removed by etching.

[0047]

As is apparent from the above description, according to the present invention, in a method of manufacturing a semiconductor device of ultra-fine processing using a hard mask for etching a gate electrode, a mask for ion implantation is used for etching a gate electrode. Since the thickness of the hard mask also serving as a mask is not reduced, the channel region is prevented from being counter-doped due to the penetration of ions, and the electrical characteristics of the obtained semiconductor device are improved.

Also in the structure in which the contact with the wiring electrode is formed by self-alignment, the thickness of the hard mask serving also as the interlayer insulating layer between the wiring electrode and the gate electrode is not reduced, so that the wiring electrode and the gate electrode are not reduced. Short circuit was prevented.

Furthermore, since these effects were realized without increasing the thickness of the hard mask, further miniaturization became possible.

Further, the compensation film is made of Poly having a reflectance.
By forming with -Si, the edge of the resist for etching the compensation film becomes clear, and the accuracy is further improved.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a process sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 8 is a process sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 9 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 10 is a process sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 11 is a process sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 12 is a process sectional view illustrating a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 20 gate oxide film 30 gate electrode 40 hard mask 50 compensation film 60 spacer 70 protective film 81, 82 interlayer insulating film 90 wiring electrode

Continued on the front page F term (reference) 5F004 AA04 DA00 DB02 DB03 DB17 EA03 EA06 EA33 EB02 FA02 5F040 DA18 DA28 DB03 DC01 EC01 EC09 EC11 EF02 EF03 EH07 FA05 FA12 FA17 FA19 FB02 FB04 FC11 FC21 FC22 5F048 AA01 BB03 BB02 BF16 DA18 DA20 DA25

Claims (3)

[Claims] In a method for manufacturing a semiconductor device having a semiconductor layer on a substrate and a gate electrode formed to face the semiconductor layer with a gate insulating film interposed therebetween, a method for manufacturing a semiconductor device, comprising the steps of: Forming a first mask layer and a second mask layer; and using the first mask layer and the second mask layer as masks,
Forming the gate electrode by etching the conductive film layer; and performing ion implantation of impurities using the first mask layer and the gate electrode as a mask to form an impurity implantation region in the semiconductor layer. And a method of manufacturing a semiconductor device. 2. The method according to claim 1, wherein said second mask layer is removed when said conductive film layer is etched. 3. The conductive film layer comprises a polycide layer,
3. The method according to claim 1, wherein the second mask layer is made of a polysilicon layer.