JP2010034224A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, along with its manufacturing method, which can be reduced in size and off breakdown voltage is maintained, while lowering the on-resistance. <P>SOLUTION: In the region of semiconductor substrate 1, a source electrode 7 and an LDD region 5b are formed on one side, while a drain electrode 6 and an LDD layer 5a are formed on the other side, with a gate electrode 4 therebetween. In the LDD layer 5a, formed from the surface of the semiconductor substrate 1 down to a predetermined depth D1, a p-type diffusion layer 10 is so formed as to be surrounded by the LDD layer 5a, excluding the surface of the LDD layer 5a, while being extended from the surface of the LDD layer 5a to a depth D3. In the LDD layer 5a, a protruding part 55 is formed, in a region which is directly underneath the p-type diffusion layer 10 so as to protrude from the bottom of the LDD layer 5a, toward a deeper region down to a depth D2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a power MOS and a manufacturing method thereof.

  In semiconductor devices having MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) used in various electronic devices and the like, miniaturization is attempted year by year for cost reduction and performance improvement by high integration. In particular, in a semiconductor device such as a CPU (Central Processing Unit) or a memory, which has a great merit due to scale-down, the miniaturization and the operation voltage are actively reduced.

  On the other hand, there is a problem that miniaturization is difficult in a semiconductor device including a MOSFET that needs to control a high voltage of several tens to several hundreds of volts, such as an automobile control part or an optical disk drive. Here, such a MOSFET is referred to as a power MOS with respect to a MOSFET applied to a CPU or a memory. Usually, the miniaturization of the MOSFET is performed simultaneously with the decrease of the power supply voltage, but the power MOS handles almost the same voltage. This is the cause of hindering miniaturization. This is due to the following reason.

  In a power MOS that is a switching element, by changing a bias voltage applied to the gate electrode, an on operation in which a current flows between the source and the drain and an off operation in which no current flows are switched. In the off state, it is necessary to prevent a punch-through current from flowing from the drain electrode to which a high voltage is normally applied to the semiconductor substrate and the source electrode. That is, it is necessary to design the device so that the punch-through current does not flow by setting the power MOS off breakdown voltage higher than the operating voltage region of the device. The off breakdown voltage is a critical voltage at which the voltage applied to the drain electrode is gradually increased and a punch-through current starts to flow from the drain electrode to the source electrode when the power MOS is off.

  As one of such semiconductor devices, a semiconductor device including a lateral power MOS in which a source region and a drain region are formed asymmetrically with respect to a gate electrode has been proposed. In this semiconductor device, the source region is formed adjacent to the sidewall spacer of the gate electrode, whereas the drain region to which a higher voltage is applied is formed at a distance from the sidewall spacer. By doing so, the region where the depletion layer extends is ensured as the drain region is formed at a distance from the sidewall spacer, and the breakdown voltage can be improved.

  On the other hand, if the impurity concentration of the LDD region on the drain side is kept low while trying to extend the depletion layer, the resistance value of the LDD region becomes high and the electric resistance (on-resistance) during power MOS operation increases. There is. As a semiconductor device for solving this problem, Patent Document 1 proposes a method of forming a pn junction in the LDD region. In this semiconductor device, a p-type diffusion layer is formed in the n-type LDD region between the gate electrode and the drain region, and the depletion layer is expanded by applying a reverse bias voltage to the p-type diffusion layer. Off-voltage is raised.

As described above, in the semiconductor device proposed in this document, punch-through is cut off by the depletion layer that is expanded by the reverse bias voltage applied to the p-type diffusion layer in the LDD region. The concentration can be increased, and the off-breakdown voltage can be kept high while the on-resistance is lowered.
JP-A-4-107877

  However, the conventional semiconductor device has the following problems. In order to apply a reverse bias voltage to the p-type diffusion layer formed in the LDD region, it is necessary to add a dedicated electrode, and it is also necessary to separately form a circuit for controlling the voltage. Therefore, even though the power MOS itself can be reduced in size, it is necessary to secure a region for forming such electrodes and circuits, and the size of the entire chip may rather be increased. was there. Further, in addition to the original operation of the semiconductor device, a voltage must be applied to such an electrode, and the control of the semiconductor device becomes complicated, resulting in an increase in design burden.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of reducing the size and keeping the off breakdown voltage high while reducing the on resistance. Another object is to provide a method of manufacturing such a semiconductor device.

  A semiconductor device according to the present invention includes a first conductivity type region, a second conductivity type first impurity region, a second conductivity type second impurity region, a gate electrode, a drain electrode, and a source electrode. The first conductivity type region is formed from the main surface of the semiconductor substrate to a predetermined depth. The first impurity region of the second conductivity type is formed from the surface of the first conductivity type region to a predetermined depth in the first conductivity type region. The second impurity region of the second conductivity type is separated from the first impurity region by a predetermined distance on the main surface and is formed from the main surface of the semiconductor substrate to a predetermined depth. The gate electrode is formed on a region serving as a channel sandwiched between the first impurity region and the second impurity region with a gate insulating film interposed therebetween. The drain electrode is formed in the first impurity region. The source electrode is formed in the third impurity region. The portion of the first impurity region located between the gate electrode and the drain electrode is surrounded by the first impurity region except for the surface of the first impurity region, and has a predetermined depth from the surface of the first impurity region. A third impurity region of the first conductivity type formed over the entire area. In addition, the first impurity region includes a second conductivity type protrusion that protrudes from the bottom of the first impurity region toward a deeper region in the region immediately below the third impurity region.

  A manufacturing method of a semiconductor device according to the present invention includes the following steps. A first conductivity type region is formed from the main surface of the semiconductor substrate to a predetermined depth. A gate electrode is formed on the surface of the first conductivity type region with a gate insulating film interposed. By implanting a second conductivity type impurity into the first conductivity type region using the gate electrode as a mask, a portion of one first conductivity type region located across the gate electrode is introduced from the surface of the first conductivity type region. A second conductivity type first impurity region is formed over a predetermined depth, and a second conductivity type first impurity region is formed in a portion of the other first conductivity type region from the surface of the first conductivity type region over a predetermined depth. Two impurity regions are formed. A drain electrode is formed in the first impurity region. A source electrode is formed in the second impurity region. A resist pattern exposing the surface of the first impurity region located between the gate electrode and the drain electrode is formed. By using the resist pattern as a mask, a second conductivity type impurity is implanted into the first impurity region, thereby forming a second conductivity type protrusion protruding from the bottom of the first impurity region toward a deeper region. By implanting a first conductivity type impurity using the resist pattern as a mask, the first impurity region is surrounded by the first impurity region and a third impurity region of the first conductivity type is formed from the surface of the first impurity region to a predetermined depth. To do.

  According to the semiconductor device of the present invention, the protrusion is formed in the depth direction in the first impurity region, and the second impurity region is formed in the depth direction immediately above the first impurity region. An effective length in which the carrier flows is ensured in the depth direction. Thereby, the area occupied by the semiconductor device can be reduced. In addition, since the effective length of carrier flow is ensured, in the off state, the voltage drop in the first impurity region in the vicinity of the region where the channel is formed is larger than the potential of the drain electrode. Thus, the breakdown voltage can be improved.

  According to the method of manufacturing a semiconductor device of the present invention, the second impurity type is formed in the first impurity region using the resist pattern that exposes the surface of the portion of the first impurity region located between the gate electrode and the drain electrode as a mask. By implanting this impurity, a protrusion is formed in the depth direction in the first impurity region, and by implanting the first conductivity type impurity, a third impurity region is formed. Thus, an effective length in which carriers flow is ensured in the depth direction, and the area occupied by the semiconductor device can be reduced and the breakdown voltage can be improved.

Embodiment 1
A semiconductor device including a power MOS and a method for manufacturing the same according to the first embodiment of the present invention will be described. As shown in FIGS. 1 and 2, an element formation region surrounded by an element isolation region 11 is formed on the surface of the semiconductor substrate 1. A gate electrode 4 is formed on the surface of the element formation region with a gate insulating film 3 interposed. Sidewall insulating films 8 are formed on both side surfaces of the gate electrode 4.

  In a region of the semiconductor substrate 1 on one side of the gate electrode 4, an n-type source electrode (region) 7 and an LDD region 5b are formed. An n-type drain electrode (region) 6 and an LDD layer 5a are formed in the region of the semiconductor substrate 1 on the other side of the gate electrode 4. The LDD layer 5a is formed from the surface of the semiconductor substrate 1 to a predetermined depth D1. The LDD layer 5a is surrounded by the LDD layer 5a except for the surface of the LDD layer 5a, and a p-type diffusion layer 10 is formed from the surface of the LDD layer 5a to the depth D3. In the LDD layer 5a, a protrusion 55 is formed over a depth D2 so as to protrude from the bottom of the LDD layer 5a toward a deeper region in a region immediately below the p-type diffusion layer 10.

  Next, the operation of the power MOS described above will be described. As shown in FIG. 3, first, 3 to 10 V is applied to the gate electrode 4 (G), 0 V is applied to the source electrode 7 (S), and 10 to 20 V is applied to the drain electrode 6 (D). A channel (inversion layer) is formed in the p-well layer 2 immediately below and is turned on. In the on state, electrons flow from the source electrode 7 to the drain electrode 6 through the channel region. Further, a depletion layer (not shown) extends mainly from the junction of the p-type diffusion layer 10 and the n-type LDD layer 5a to the LDD layer 5a side. At this time, as shown in the path C, the electrons flow while moving up and down (in the depth direction) in the LDD layer 5a or the protrusion 55 so as to avoid the depletion layer. On the other hand, as shown in FIG. 4, by applying 0 V to the gate electrode 4 (G), 0 V to the source electrode 7 (S), and 10 to 20 V to the drain electrode 6 (D), the channel disappears and is turned off. It becomes a state.

  In the semiconductor device described above, the area occupied by the power MOS can be reduced while ensuring a breakdown voltage at the time of off. This will be described in relation to a semiconductor device according to a comparative example.

  First, as a first comparative example, a power MOS having a source / drain formed symmetrically with respect to a gate electrode will be described. As shown in FIG. 5, a P well layer 102 is formed on a semiconductor substrate 101, and a gate insulating film 103 and a gate electrode 104 are formed on the P well layer 02. LDD (Lightly Doped Drain) layers 105a and 111 are formed by implanting N-type impurities into the P well layer 102 by ion implantation using the gate electrode 104 as a mask. Further, by using the gate electrode 104 and the sidewall spacer 108 as a mask, N-type impurities are implanted into the LDD layers 105a and 111 by ion implantation, whereby the drain region 106 is formed in the LDD layer 105a. A source region 107 is formed.

  When the power MOS is turned off, if a positive bias is applied to the drain region 106, the depletion layer 109a extends to the P well layer 102 side and the depletion layer 109b also extends to the LDD layer 105 side. When the end of the depletion layer 109b reaches the drain region 106, the width of the depletion layer 109b cannot be further increased. At this time, when a higher voltage is applied to the drain region 106, the depletion layer 109 a extending to the P well layer 102 side further extends in order to relax the electric field, but the depletion layer 109 a faces the source region 107. Even grows. Therefore, such elongation of the depletion layer causes the breakdown voltage between the source and the drain to deteriorate, and there is a problem that punch-through is likely to occur.

  Therefore, as a second comparative example, an example of a lateral power MOS having an asymmetric source / drain structure that avoids such problems will be described. As shown in FIG. 6, in this power MOS, the source region 107 is formed up to the region immediately below the sidewall spacer 108 of the gate electrode 104, whereas the drain region 106 to which a high voltage is applied has a side It is formed at a distance from the wall spacer 108 (offset).

  In the off state of the power MOS, the drain region 106 is formed at a distance from the sidewall spacer 108, so that a depletion layer generated from the interface between the LDD layer 105 a and the P well layer 102 is formed on the side of the LDD layer 105 a. It is said that the electric field can be relaxed. As described above, in the power MOS according to the second comparative example, the drain region 106 is separated from the sidewall spacer 108 (gate electrode 104) by securing the withstand voltage, so that the voltage applied to the drain region 106 is increased. Is not reduced, it is difficult to reduce the distance between the gate electrode 104 and the drain region 106, and there is a limit in reducing the size of the power MOS.

  On the other hand, in the semiconductor device according to the present embodiment described above, in the ON state, the electrons are not exposed to the LDD layer 5a or protruding so as to avoid the depletion layer extending from the interface between the p-type diffusion layer 10 and the LDD layer 5a. It flows while moving up and down (depth direction) in the portion 55. Therefore, the effective length that the carrier flows becomes long. Also, since the effective length of carrier flow is increased, in the off state, as shown in FIG. 4, between the drain electrode 6 and the portion A of the LDD layer 5a in the vicinity of the region where the channel is formed. And the voltage drop at the portion A becomes lower. Thereby, the withstand voltage at the time of OFF can be improved.

  In addition, by providing the protruding portion 55, it is possible to sufficiently secure a region where carriers flow, and to reduce on-resistance. Moreover, the area occupied by the power MOS can be reduced by ensuring the effective length in the depth direction of the semiconductor substrate 1 rather than in the planar direction of the semiconductor substrate 1.

  Next, an example of a method for manufacturing the power MOS described above will be described. First, as shown in FIG. 7, an element formation region is formed by forming an element isolation region 11 in a predetermined region on the main surface of the semiconductor substrate 1. Next, a P-type well layer 2 is formed by introducing a p-type impurity such as boron into the element formation region. Next, as shown in FIG. 2, gate electrode 4 is formed on the surface of P well layer 2 with gate insulating film 3 interposed. The thickness of the gate insulating film 3 is determined by the voltage value handled by the MOSFET, but as an example, a silicon oxide film of about 10 to 50 nm is formed.

As the gate electrode 4, a tungsten silicide layer is deposited on a polysilicon film to which N-type impurities such as phosphorus are added at a high concentration (about 1 × 10 ²² cm ⁻³ ) or a polysilicon film to which N-type impurities are added. The stack structure is applied. For example, the height of the gate electrode is about 100 to 300 nm.

Next, LDD layers 5a and 5b are formed by introducing N-type impurities into the P well layer 2 by ion implantation using the gate electrode 4 as a mask. In the conventional power MOS, the implantation for forming the LDD layer has to be performed at a relatively low impurity concentration in order to ensure the off breakdown voltage. On the other hand, in the above-described power MOS, the p-type diffusion layer 10 (see FIG. 11) formed in the LDD layer 5a secures a breakdown voltage at the time of off, so that it can be performed at a relatively high concentration. . Therefore, the on-resistance can be lowered. Here, the LDD layers 5a and 5b are formed, for example, by ion implantation of phosphorus at an energy of about 50 to 200 keV and a dose of about 5 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² .

Next, as shown in FIG. 9, a predetermined resist pattern 12 for forming the protrusion 55 (see FIG. 2) is formed on the LDD layer 5a. In the resist pattern 12, an opening 12 a that exposes a region for forming a protruding portion is formed. Next, as shown in FIG. 10, by using the resist pattern 12 as a mask and introducing an N-type impurity by an ion implantation method, a protruding portion 55 protruding toward a deeper region from the bottom of the LDD layer 5a is formed. It is formed. This ion implantation is performed with energy such that the projection range Rp (Projection Range) in the depth direction of the semiconductor substrate 1 is about 1.5 to 2 times the depth of the LDD layer 5a. Here, the protrusion 55 is formed, for example, by implanting phosphorus with an energy of about 80 to 400 keV and a dose of about 5 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² .

Next, as shown in FIG. 11, a P-type diffusion layer 10 is formed by introducing P-type impurities by the ion implantation method using the same resist pattern 12 as a mask. In this ion implantation, the projecting range Rp is performed with energy such that the depth is half the depth of the LDD layer 5a and the same depth as the LDD layer 5a. The concentration of the P-type impurity is set to such a high concentration that the P-type diffusion layer 10 is formed by offsetting the impurity concentration of the N-type impurity of the LDD layer 5a introduced earlier. Here, the P-type diffusion layer 10 is formed, for example, by ion implantation of boron with an energy of about 10 to 80 kev and a dose of about 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² . Thereafter, the resist pattern 12 is removed.

  Next, as shown in FIG. 12, sidewall spacers 8 are formed on both side surfaces of the gate electrode 4. Next, a resist pattern 13 is formed from the gate electrode 4 to a predetermined position between the P-type diffusion layer 10 and the element isolation region 11 so as to cover the LDD layer 5a. Using the resist pattern 13, the gate electrode 4 and the side wall spacer 8 as a mask, an N-type impurity is introduced into the exposed LDD layers 5a and 5b by ion implantation, whereby a drain electrode (region) is formed in the LDD layer 5a. 6 is formed, and a source electrode (region) 7 is formed in the LDD layer 5b. Thereafter, the resist pattern 13 is removed. Thereafter, an annealing process for activating the introduced impurities, formation of an interlayer insulating film, and formation of metal wiring are performed to form the main part of the power MOS.

  In the above-described power MOS, the case where two pairs (structures) of the protruding portion 55 and the P-type diffusion layer 10 are formed in the LDD layer 5a has been described as an example. The set is not limited to one, and may be one or more than three. Note that as the number of pairs increases, it is more effective for maintaining the off breakdown voltage. However, since it is necessary to secure an area for that purpose, it is desirable to select an appropriate number of pairs according to the layout.

Embodiment 2
A semiconductor device including a power MOS and a method for manufacturing the same according to the second embodiment of the present invention will be described. As shown in FIG. 13, the LDD layer 5a is formed from the surface of the semiconductor substrate 1 to a predetermined depth D1, and the LDD layer 5a protrudes to a depth D2 deeper than the depth D1. A portion 55 is formed. A p-type diffusion layer 10 is formed immediately above the protrusion 55 in the LDD layer 5a over a predetermined depth D3 deeper than the depth D1 from the surface. In addition, since it is the same as that of the structure shown in FIG. 2 about another structure, the same code | symbol is attached | subjected to the same member and the description is abbreviate | omitted.

  Next, the operation of the power MOS described above will be described. As shown in FIG. 14, first, 3 to 10 V is applied to the gate electrode 4 (G), 0 V is applied to the source electrode 7 (S), and 10 to 20 V is applied to the drain electrode 6 (D). A channel (inversion layer) is formed in the p-well layer 2 immediately below and is turned on. In the on state, electrons flow from the source electrode 7 to the drain electrode 6 through the channel region. Further, a depletion layer (not shown) extends mainly from the junction of the p-type diffusion layer 10 and the n-type LDD layer 5a to the LDD layer 5a side. At this time, as shown in the path C, the electrons flow while moving up and down in the LDD layer 5a or the protruding portion 55 so as to avoid the depletion layer.

  On the other hand, as shown in FIG. 15, by applying 0 V to the gate electrode 4 (G), 0 V to the source electrode 7 (S), and 10 to 20 V to the drain electrode 6 (D), the channel disappears and is turned off. It becomes a state.

  In the semiconductor device described above, the p-type diffusion layer 10 is formed from the surface of the LDD layer 5a to a region (depth D3) in the depth direction of the protrusion 55 that is deeper than the bottom (depth D1). Yes. This further increases the effective length of carrier flow as compared with the power MOS described above. As a result, as shown in FIG. 15, in the off state, the voltage drop between the drain electrode 6 and the portion A of the LDD layer 5a in the vicinity of the region where the channel is formed is further increased. Can be further reduced, and the breakdown voltage at the time of OFF can be further improved. In addition, since the effective length (path) through which carriers flow is ensured in the depth direction, the occupation area of the power MOS can be reduced.

Next, an example of a method for manufacturing the power MOS described above will be described. After the resist pattern 12 shown in FIG. 10 is formed through the steps shown in FIGS. 7 to 9, the P-type impurity is introduced by ion implantation as shown in FIG. A diffusion layer 10 is formed. This ion implantation is performed with energy such that the projection range Rp is about 1.5 times the depth of the LDD layer 5a. Here, the P-type diffusion layer 10 is formed, for example, by implanting boron with an energy of about 30 to 120 keV. Note that the dose amount (1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² ) of the P-type impurity is almost the same as that described above. Thereafter, the resist pattern 12 is removed.

  By the way, the P-type diffusion layer 10 needs to be formed in the region of the LDD layer 5 a including the protruding portion 55. This is because, when the P-type diffusion layer 10 is formed so as to protrude outside the region of the LDD layer 5a, the carrier flow path in the N-type diffusion layer 5a connecting the drain and the gate is interrupted in the middle. This is because the ON resistance value is increased.

  Since the implantation profile of phosphorus forming the LDD layer 5a has a broader distribution than the implantation profile of boron forming the P-type diffusion layer 10, even if ion implantation is performed using the same resist pattern 12 as a mask, FIG. It is possible to form the protrusion 55 and the P-type diffusion layer 10 shown. However, depending on the heat treatment conditions applied in the wafer process after implantation, it is assumed that boron is thermally diffused outside the region of the protrusion 55.

  Therefore, in consideration of thermal diffusion of boron, the protruding portion may be formed by oblique implantation. That is, as shown in FIG. 17, the semiconductor substrate 1 has a component injected toward the region immediately below the gate electrode 4 and a component injected toward the region immediately below the drain electrode (region). By performing ion implantation in at least two steps or more with a predetermined implantation angle (incident angle) with respect to the surface of the surface, a substantially trapezoidal protruding portion 55 in which a portion located in a deeper region expands in the lateral direction is formed. It is formed. Next, as shown in FIG. 18, P-type diffusion layer 10 is formed by ion implantation substantially perpendicular to the surface of semiconductor substrate 1. Thus, by diffusing and expanding the portion located in the deeper region of the protrusion 55 in the lateral direction, it is possible to prevent the impurities in the P-type diffusion layer 10 from diffusing out of the LDD layer 5a.

Embodiment 3
A semiconductor device including a power MOS and a manufacturing method thereof according to Embodiment 3 of the present invention will be described. As shown in FIGS. 19 and 20, in this power MOS, the p-type diffusion layer 10 is electrically short-circuited to the gate electrode 4 through the metal wiring 20a and the contact plug 19a. In addition, since it is the same as that of the structure shown in FIG. 2 about another structure, the same code | symbol is attached | subjected to the same member and the description is abbreviate | omitted.

  Next, the operation of the power MOS described above will be described. As shown in FIG. 21, first, 3 to 10 V is applied to the gate electrode 4 (G), 0 V is applied to the source electrode 7 (S), and 10 to 20 V is applied to the drain electrode 6 (D). A channel (inversion layer) is formed in the p-well layer 2 immediately below and is turned on. In the on state, electrons flow from the source electrode 7 to the drain electrode 6 through the channel region. In addition, a depletion layer (dotted line) extends mainly from the junction of the p-type diffusion layer 10 and the n-type LDD layer 5a to the LDD layer 5a side. At this time, electrons flow while moving up and down (in the depth direction) in the LDD layer 5a or the protruding portion 55 so as to avoid the depletion layer (path C).

  On the other hand, as shown in FIG. 22, by applying 0 V to the gate electrode 4 (G), 0 V to the source electrode 7 (S), and 10 to 20 V to the drain electrode 6 (D), the channel disappears and is turned off. It becomes a state.

  In the power MOS described above, the following effects are obtained in addition to the effects described in the first embodiment. That is, the p-type diffusion layer 10 is electrically short-circuited with the gate electrode 4 so that the p-type diffusion layer 10 is in a zero bias state (negative bias state) when turned off and in a positive bias state when turned on. . Thereby, at the time of OFF, as shown in FIG. 22, the depletion layer generated from the interface between the p-type diffusion layer 10 and the LDD layer 5a is further expanded (width L2), and the OFF breakdown voltage can be improved. On the other hand, at the time of ON, as shown in FIG. 21, the depletion layer generated from the interface between the p-type diffusion layer 10 and the LDD layer 5a is further contracted (width L1 <L2), and the region through which carriers flow increases and the on resistance is increased. Can be further reduced. Further, since only the p-type diffusion layer 10 is electrically short-circuited to the gate electrode 4, no additional control circuit or the like as in the case of applying a predetermined voltage to the p-type diffusion layer 10 is required, and the occupied area There is no increase.

  Next, a method for manufacturing the above-described power MOS will be described. After the process shown in FIG. 12, the interlayer insulating film 14 is formed on the semiconductor substrate 1 so as to cover the gate electrode 4 and the like, as shown in FIG. Openings 14 a exposing the respective surfaces of p-type diffusion layer 10, drain electrode (region) 6 and source electrode (region) 7 are formed in interlayer insulating film 14. Next, as shown in FIG. 24, a predetermined conductive film 19 is formed on the interlayer insulating film 14 so as to fill the opening 14a.

  Next, as shown in FIG. 25, the conductive film 19 is subjected to a chemical mechanical polishing process or the like to remove a portion of the conductive film 19 located on the upper surface of the interlayer insulating film 14, thereby opening the opening 14 a. Contact plugs 19a to 19c are formed. Next, as shown in FIG. 26, a conductive film 20 is further formed on the interlayer insulating film 14. Next, as shown in FIG. 27, the conductive film 20 is subjected to predetermined processing to form a wiring 20a that electrically connects the contact plug 19a that contacts the p-type diffusion layer 10 and the gate electrode 4. The Thus, the main part of the power MOS is formed.

Embodiment 4
In the power MOS described in the third embodiment, since the same voltage as the voltage applied to the gate electrode is applied to the p-type diffusion layer 10 when turned on, a large pn junction is formed between the p-type diffusion layer 10 and the LDD layer 5a. A positive bias voltage is applied. For this reason, in addition to the reduction of the width of the depletion layer, it is assumed that the pn junction diode is biased in the forward direction, and an unintended leakage current flows to increase power consumption.

  Therefore, in the fourth embodiment, a semiconductor device including a power MOS that can reduce the assumed leakage current and a manufacturing method thereof will be described. As shown in FIGS. 28 and 29, in this power MOS, the gate electrode 4 and the p-type diffusion layer 10 are electrically short-circuited through the metal wiring 20a and the contact plug 19a. Further, the metal wiring 20a is provided with a resistor 20b. In addition, since it is the same as that of the structure shown in FIG. 2 about another structure, the same code | symbol is attached | subjected to the same member and the description is abbreviate | omitted.

  Next, the operation of the power MOS described above will be described. As shown in FIG. 30, first, 3 to 10 V is applied to the gate electrode 4 (G), 0 V is applied to the source electrode 7 (S), and 10 to 20 V is applied to the drain electrode 6 (D). A channel (inversion layer) is formed in the p-well layer 2 immediately below and is turned on. In the on state, electrons flow from the source electrode 7 to the drain electrode 6 through the channel region. In addition, a depletion layer (dotted line) extends mainly from the junction of the p-type diffusion layer 10 and the n-type LDD layer 5a to the LDD layer 5a side. At this time, electrons flow while moving up and down (in the depth direction) in the LDD layer 5a or the protruding portion 55 so as to avoid the depletion layer (path C).

  On the other hand, as shown in FIG. 31, by applying 0 V to the gate electrode 4 (G), 0 V to the source electrode 7 (S), and 10 to 20 V to the drain electrode 6 (D), the channel disappears and is turned off. It becomes a state.

  In the power MOS described above, the following effects are obtained in addition to the effects described in the first embodiment. That is, by providing the resistor 20b between the gate electrode 4 and the p-type diffusion layer 10, in the ON state, the voltage applied to the p-type diffusion layer 10 can be lowered by the voltage drop due to the resistance, and the depletion layer The width L3 (see FIG. 30) can be larger than the width L1 (see FIG. 21). Thereby, it is possible to prevent a leakage current from being generated in the ON state. Further, by suppressing unnecessary leakage current, the on-resistance can be reduced without increasing power consumption. Note that the width L4 (see FIG. 31) of the depletion layer in the off state is substantially the same as the width L2 (see FIG. 22).

Embodiment 5
A semiconductor device including a power MOS and a manufacturing method thereof according to the fifth embodiment of the present invention will be described. As shown in FIGS. 32 and 33, in this power MOS, an insulating film 15 is formed so as to cover the p-type diffusion layer 10. A contact plug 19a is formed so as to come into contact with the surface of the portion of the insulating film 15 located immediately above the p-type diffusion layer 10. The contact plug 19a is electrically short-circuited with the gate electrode 4 through the metal wiring 20a and the contact plug 19d. In addition, since it is the same as that of the structure shown in FIG. 2 about another structure, the same code | symbol is attached | subjected to the same member and the description is abbreviate | omitted.

  Next, the operation of the power MOS described above will be described. As shown in FIG. 34, first, 3 to 10 V is applied to the gate electrode 4 (G), 0 V is applied to the source electrode 7 (S), and 10 to 20 V is applied to the drain electrode 6 (D). A channel (channel A) is formed in the p-well layer 2 immediately below and is turned on. A channel (channel B) is also formed in the p-type diffusion layer 10 immediately below the contact plug 19a electrically short-circuited with the gate electrode 4. For this reason, in the ON state, electrons flow while moving up and down (in the depth direction) in the LDD layer 5a or the protrusion 55 so as to avoid the depletion layer through the channel A from the source electrode 7 (path C1). Then, it flows through channel A through channel B (path C2) and flows to drain electrode (region) 6.

  On the other hand, as shown in FIG. 35, by applying 0 V to the gate electrode 4 (G), 0 V to the source electrode 7 (S), and 10 to 20 V to the drain electrode 6 (D), channel A and channel B are Disappears and turns off.

  In the power MOS described above, the following effects are obtained in addition to the effects described in the first embodiment. That is, the contact plug 19a is electrically insulated from the semiconductor substrate 1. For this reason, the pn diodes of the p-type diffusion layer 10 and the n-type LDD layer 5a are not biased in the forward direction by the contact plug 19a that is electrically short-circuited with the gate electrode 4 at the time of ON. The depletion layer elongation (width L5) generated from the interface between the p-type diffusion layer 10 and the n-type LDD layer 5a is suppressed. Note that the width L6 of the depletion layer in the off state is substantially the same as the width L2 (FIG. 22) and the width L4 (FIG. 31), but is narrower than that.

  In addition to this, in this power MOS, a channel (channel B) is also formed on the p-type diffusion layer 10 immediately below the contact plug 19 a, and a path (path) through which carriers flow along the vicinity of the surface of the semiconductor substrate 1. ), Two paths (routes C1 and C2) are formed. As a result, the on-resistance can be further reduced.

  Next, a method for manufacturing the above-described power MOS will be described. After the process shown in FIG. 12, the insulating film 15 such as a silicon nitride film is formed on the semiconductor substrate 1 so as to cover the gate electrode 4 and the like, as shown in FIG. An interlayer insulating film 14 is further formed so as to cover the insulating film 15. Openings 14 a exposing the respective surfaces of p-type diffusion layer 10, drain electrode (region) 6 and source electrode (region) 7 are formed in interlayer insulating film 14.

  Next, as shown in FIG. 37, a resist pattern 16 is formed, and the insulating film 15 is etched using the resist pattern 16 as a mask, whereby the surface of the source electrode (region) 7 and the drain electrode (region) 6 are etched. To expose the surface. The resist pattern 16 is removed. Next, through the same steps as those shown in FIGS. 24 to 27, as shown in FIG. 38, the main part of the power MOS including contact plugs 19a to 19c is formed.

  In the power MOS described above, in order to easily form a channel, it is preferable that the thickness of the insulating film immediately below the contact plug 19a is thin, and it is preferable that the number of contact plugs 19a is large. As shown in FIG. 32, in the present power MOS, the case where a plurality of contact plugs 19a are formed in the channel width direction has been described as an example. In addition, as shown in FIG. 39, a slit-shaped contact plug 19 a may be formed so as to correspond to the planar shape of the p-type diffusion layer 10. In this case, the channel is more easily formed, and the on-resistance can be reliably lowered.

  In each of the above-described embodiments, an n-channel type power MOS has been described as an example of the power MOS. However, a p-channel type power MOS may be used by reversing the conductivity type.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along a cross-sectional line II-II shown in FIG. 1 in the same embodiment. FIG. 6 is a cross-sectional view showing an on state for explaining the operation of the semiconductor device in the embodiment. 4 is a cross-sectional view showing an off state for explaining the operation of the semiconductor device in the embodiment. FIG. It is sectional drawing of the semiconductor device which concerns on a comparative example. It is sectional drawing of the semiconductor device which concerns on another comparative example. FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the embodiment. FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the same embodiment. FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the same embodiment. FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the same embodiment. FIG. 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the same embodiment. FIG. 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the same embodiment. It is sectional drawing of the semiconductor device which concerns on Embodiment 2 of this invention. FIG. 6 is a cross-sectional view showing an on state for explaining the operation of the semiconductor device in the embodiment. 4 is a cross-sectional view showing an off state for explaining the operation of the semiconductor device in the embodiment. FIG. FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the embodiment. FIG. 16 is a cross-sectional view showing a step according to a modification of the method for manufacturing a semiconductor device in the embodiment. FIG. 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the same embodiment. It is sectional drawing of the semiconductor device which concerns on Embodiment 3 of this invention. FIG. 20 is a cross-sectional view taken along a cross-sectional line XX-XX shown in FIG. 19 in the same embodiment. FIG. 6 is a cross-sectional view showing an on state for explaining the operation of the semiconductor device in the embodiment. 4 is a cross-sectional view showing an off state for explaining the operation of the semiconductor device in the embodiment. FIG. FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the embodiment. FIG. 24 is a cross-sectional view showing a step performed after the step shown in FIG. 23 in the same embodiment. FIG. 25 is a cross-sectional view showing a step performed after the step shown in FIG. 24 in the same embodiment. FIG. 26 is a cross-sectional view showing a step performed after the step shown in FIG. 25 in the same embodiment. FIG. 27 is a cross-sectional view showing a step performed after the step shown in FIG. 26 in the same embodiment. It is sectional drawing of the semiconductor device which concerns on Embodiment 4 of this invention. FIG. 29 is a cross sectional view taken along a cross sectional line XXIX-XXIX shown in FIG. 28 in the embodiment. FIG. 6 is a cross-sectional view showing an on state for explaining the operation of the semiconductor device in the embodiment. 4 is a cross-sectional view showing an off state for explaining the operation of the semiconductor device in the embodiment. FIG. It is sectional drawing of the semiconductor device which concerns on Embodiment 5 of this invention. FIG. 33 is a cross sectional view taken along a cross sectional line XXIII-XXIII shown in FIG. 32 in the same embodiment. FIG. 6 is a cross-sectional view showing an on state for explaining the operation of the semiconductor device in the embodiment. 4 is a cross-sectional view showing an off state for explaining the operation of the semiconductor device in the embodiment. FIG. FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the embodiment. FIG. 37 is a cross-sectional view showing a step performed after the step shown in FIG. 36 in the same embodiment. FIG. 38 is a cross-sectional view showing a step performed after the step shown in FIG. 37 in the same embodiment. In the same embodiment, it is a top view of the semiconductor device concerning a modification.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 P well layer, 3 Gate insulating film, 4 Gate electrode, 5a LDD layer, 55 Protrusion part, 5b LDD layer, 6 Drain electrode, 7 Source electrode, 8 Side wall spacer, 10 p-type diffusion layer, 11 Element isolation region, 12 photoresist, 12a opening, 13 photoresist, 14 interlayer insulating film, 14a opening, 15 insulating film, 16 photoresist, 19 conductive film, 19a, 19b, 19c, 19d contact plug, 20 conductive film, 20a wiring, 20b resistance, 20c wiring.

Claims (12)

A first conductivity type region formed from the main surface of the semiconductor substrate to a predetermined depth;
A first impurity region of a second conductivity type formed from the surface of the first conductivity type region to a predetermined depth in the first conductivity type region;
A second impurity region of a second conductivity type spaced from the first impurity region on the main surface by a predetermined distance and formed to a predetermined depth from the main surface of the semiconductor substrate;
A gate electrode formed on a region to be a channel sandwiched between the first impurity region and the second impurity region with a gate insulating film interposed therebetween;
A drain electrode formed in the first impurity region;
A source electrode formed in the third impurity region,
The portion of the first impurity region located between the gate electrode and the drain electrode is surrounded by the first impurity region except for the surface of the first impurity region, and from the surface of the first impurity region. A third impurity region of a first conductivity type formed over a predetermined depth;
The semiconductor device, wherein the first impurity region includes a second conductivity type projecting portion projecting from a bottom of the first impurity region toward a deeper region in a region immediately below the third impurity region. The third impurity region is formed over a region deeper than the bottom of the first impurity region;
The semiconductor device according to claim 1, wherein the protruding portion is formed so as to surround a portion of the third impurity region protruding from the bottom of the first impurity region.   The semiconductor device according to claim 1, wherein the protrusion includes a portion extending in a lateral direction as the protrusion becomes deeper.   The semiconductor device according to claim 1, wherein the gate electrode and the third impurity region are electrically short-circuited.   The semiconductor device according to claim 4, wherein a resistor is interposed between the gate electrode and the third impurity region. An insulating film formed on the semiconductor substrate so as to cover a surface of the third impurity region;
4. The device according to claim 1, further comprising a contact plug formed so as to contact a surface of the portion of the insulating film located immediately above the third impurity region and electrically connected to the gate electrode. A semiconductor device according to 1. Forming a first conductivity type region from the main surface of the semiconductor substrate to a predetermined depth;
Forming a gate electrode on the surface of the first conductivity type region with a gate insulating film interposed therebetween;
By implanting a second conductivity type impurity into the first conductivity type region using the gate electrode as a mask, the first conductivity type is formed in a portion of the first conductivity type region located across the gate electrode. A first impurity region of the second conductivity type is formed from the surface of the mold region over a predetermined depth, and the other portion of the first conductivity type region is formed over the predetermined depth from the surface of the first conductivity type region. Forming a second impurity region of a second conductivity type;
Forming a drain electrode in the first impurity region;
Forming a source electrode in the second impurity region,
Forming a resist pattern exposing a surface of a portion of the first impurity region located between the gate electrode and the drain electrode;
By using the resist pattern as a mask, a second conductivity type impurity is implanted into the first impurity region, thereby forming a second conductivity type protrusion protruding from the bottom of the first impurity region toward a deeper region. And a process of
By implanting a first conductivity type impurity using the resist pattern as a mask, the first conductivity type third impurity is surrounded by the first impurity region and a predetermined depth from the surface of the first impurity region. A method for manufacturing a semiconductor device, comprising: forming a region. In the step of forming the third impurity region, the third impurity region is formed over a region deeper than the bottom of the first impurity region,
8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the protruding portion, the protruding portion is formed so as to surround a portion of the third impurity region protruding from a bottom of the first impurity region.   9. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the protruding portion, the second conductivity type impurity is implanted obliquely with a predetermined inclination with respect to the main surface of the semiconductor substrate.   The method for manufacturing a semiconductor device according to claim 7, further comprising a step of forming a wiring that electrically connects the gate electrode and the third impurity region.   The method of manufacturing a semiconductor device according to claim 10, wherein in the step of forming the wiring, a resistance is formed between the gate electrode and the third impurity region. Forming an insulating film having a predetermined thickness on the semiconductor substrate so as to cover a surface of the third impurity region;
Forming an interlayer insulating film on the semiconductor substrate so as to cover the insulating film;
Forming an opening in the interlayer insulating film to expose a surface of a portion of the insulating film located immediately above the third impurity region;
Forming a contact plug in the opening;
Forming a wiring for electrically connecting the gate electrode and the contact plug;
The manufacturing method of the semiconductor device in any one of Claims 7-9 provided with these.

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