JP2004079748A - Insulated gate field effect transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an insulated gate field effect transistor, which is capable of easily improving it in characteristics and reliability and ensuring the degree of freedom of design for it, and to provide an insulated gate field effect transistor which has a source/drain structure and is suitable for ensuring superior characteristics and reliability. <P>SOLUTION: The method of manufacturing the insulated gate field effect transistor comprises a first process of forming a sacrificial layer 7 on a semiconductor 4, second process of forming first source/drain regions 8 in the semiconductor 4 by implantation of ions as the sacrificial layer 7 is used as a mask, third process of covering the sacrificial layer 7 and its vicinity with a thick insulating film 9, fourth process of exposing the top surface of the sacrificial layer 7 and removing the sacrificial layer 7, fifth process of forming a gate insulating film 10 on the surface of the semiconductor 4 where the sacrificial layer 7 has been removed, and sixth process of forming a level difference by the use of the gate insulating film 10 and the thick insulating film 9, seventh process of forming a gate electrode on each side face of the level difference, and eight process of forming a second source/drain region 12 (shown in Figure 4). <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an insulated gate field effect transistor in which two source / drain regions are formed asymmetrically, and a method of manufacturing the same.
[0002]
[Prior art]
With the miniaturization of semiconductor elements, the degree of integration of semiconductor integrated circuits has been improving at a rate of twice in two to three years according to the scaling rule. As a result, higher speed and lower power consumption of semiconductor integrated circuits have been developed.
The miniaturization of a semiconductor element, especially a MOSFET (Metal-Oxide-Semiconductor \ Effect \ Transistor) is mainly achieved by reducing the size of a gate electrode, thinning a gate oxide film, and optimizing an impurity profile. In the optimization of the impurity profile, in addition to the optimization of the channel concentration of the transistor, the impurity profile of the source / drain region in the vicinity of the boundary with the channel formation region is accurately controlled to form, for example, a shallow junction. Is important. As a result, the driving capability of the transistor is improved, the parasitic capacitance is reduced, and the like, and the deterioration in characteristics due to miniaturization is compensated for, or the characteristics are further improved.
[0003]
An accurate and shallow junction forming technique in the vicinity of the channel forming region and the source or drain region is important and indispensable for miniaturization and high performance of the device. Overcoming various problems caused by miniaturization of elements by, for example, maintaining or improving Vth roll-off characteristics, or suppressing or reducing increase in parasitic resistance, by precisely controlling an impurity profile for forming a shallow junction. Becomes possible.
[0004]
In particular, as miniaturization progresses as in recent years, the impurity profile control of an impurity region called an S / D extension (hereinafter, referred to as an S / D extension portion or simply an extension portion) is required to reduce the element size. It will almost determine the progress of high performance and high performance.
In the S / D extension part on the drain side, as the junction becomes deeper, the depletion layer expands in a deeper part immediately below the gate according to the drain voltage (DIBL; Drain Induced Barrier Lowering), and the leakage current due to punch-through increases. I will. Therefore, in the S / D extension part on the drain side, a shallower and steeper junction is required for miniaturization of the element.
At the same time, in order to maintain the reliability of the gate oxide film, it is necessary to reduce the electric field in the channel direction at the drain end to suppress the generation of hot carriers.
Focusing on these, it is necessary to optimize the impurity profile of the S / D extension part in the drain region.
[0005]
On the other hand, it is important to optimize the impurity profile of the S / D extension portion in the source region, particularly from the viewpoint of reducing the source resistance.
For example, in a self-aligned silicide (salicide) forming technique employed in many of small MOSFETs, a side wall spacer (side) is formed in order to prevent a short circuit between a gate and a source or between a gate and a drain. After forming (Wall @ Spacer), a self-aligned silicide is formed. There is an S / D extension part immediately below the sidewall spacer, and this part is not silicided. Therefore, it is necessary to sufficiently lower the resistance of the source-side S / D extension unit so that the characteristics do not deteriorate.
[0006]
As described above, the source region and the drain region have different requirements for the respective impurity regions, and are required to have mutually contradictory characteristics.
However, since the S / D extension part is usually formed collectively on the source side and the drain side, there is a trade-off (trade off) in the design of the impurity profile. That is, it is difficult to simultaneously realize the impurity profile required for the source-side S / D extension portion and the impurity profile required for the drain-side S / D extension portion, and the required characteristics cannot be sufficiently satisfied. There is a problem.
[0007]
In order to overcome this problem, there is known a report on characteristics of a transistor in which a source and a drain are formed asymmetrically by obliquely implanting high-concentration impurity ions into a gate electrode (for example, Non-Patent Document 1). reference).
[0008]
FIG. 6 shows a cross-sectional view of the MOSFET at the time of oblique ion implantation.
The MOSFET illustrated in FIG. 6 has an SOI type substrate isolation structure. A buried insulating film 101 is formed on a substrate 100, and an SOI layer 102 made of single crystal silicon is formed on the buried insulating film 101. A part of the SOI layer 102 is insulated, and an element isolation insulating layer 103 is formed. On the surface of the non-insulated SIO layer 102, a gate insulating film 104 made of silicon oxide is formed. A gate electrode 105 is formed on the gate insulating film.
[0009]
In the state formed up to the stage illustrated in FIG. 6, ion implantation is performed to form source / drain regions including the S / D extension part. Specifically, in the case of NMOS, N-type impurity ions are implanted while changing the implantation angle between, for example, a direction perpendicular to the substrate and a direction obliquely inclined from the vertical position.
As a result, N-type impurity regions are formed in the portions of the SOI layer 102 on one side and the other side of the gate electrode 105, respectively. However, since ions are not implanted into the shadowed portion of the gate electrode 105, the impurity profile on one side is different from the impurity profile on the other side. The side closer to the gate electrode has a higher concentration as a source region, and the side having a relatively lower concentration as a drain region. As a result, a difference can be provided between the impurity profile of the source and the drain, particularly, the concentration difference near the gate.
[0010]
[Non-patent document 1]
T. Ghani and 6 others, "Asymmetric Metric / Drain Extension" Transistor Structure for High High Performance Sub-50nm CMOS Devices, 2001
Symposium \ on \ VLSI \ Technology \ Digest \ of \ Technical \ Paper,
Figure1, Figure2
[0011]
[Problems to be solved by the invention]
However, in the method of forming an asymmetric transistor by oblique ion implantation, there are some problems to be solved as follows.
[0012]
First, the side on which impurity ions are likely to be implanted must be the source, and the side on which impurity ions are less likely to be implanted due to the shadow of the gate electrode and whose concentration is low must be the drain. That is, the arrangement of the transistors is restricted by the positional relationship between the source and the drain with respect to the gate electrode, and the degree of freedom in layout is small. If the gate pattern of the transistor is not basically oriented in the same direction as the ion implantation direction, the characteristics will fluctuate.
[0013]
Second, the asymmetry of the source region and the drain region is affected by the height of the gate electrode in addition to the oblique ion implantation conditions. In this respect, the degree of freedom in designing the device structure is small.
[0014]
Third, the same heat treatment is necessarily applied to the source region and the drain region. Therefore, it is impossible to change the effective thermal process between them. At this point, it is not easy to precisely control and optimize the concentration profile.
For example, in an SOI transistor in which a body potential is in an electrically floating state, there is a demand to suppress FBE (Floating Body Effect) without increasing off current (junction leakage current). In this case, it is most effective to control the carrier lifetime (Life @ Time) separately for the source and the drain. In order to change the lifetime between the source and the drain, the most effective means is to change the thermal process at the time of forming each of the two impurity regions of the source and the drain. However, since the control of the lifetime cannot be controlled separately from the thermal process at the time of forming the impurity region, it is impossible to control such that the lifetime is changed between the source and the drain.
[0015]
A first object of the present invention is to provide a method of manufacturing an insulated gate field effect transistor in which characteristics and reliability can be improved and design flexibility can be easily ensured.
A second object of the present invention is to provide an insulated gate field effect transistor having a source / drain structure suitable for securing excellent characteristics and reliability.
[0016]
[Means for Solving the Problems]
A method of manufacturing an insulated gate field effect transistor according to the present invention achieves the first object described above, and includes a step of forming a sacrificial layer on a semiconductor on which a channel is formed, and Forming a first source / drain region in the semiconductor by ion implantation using a mask, covering the periphery of the sacrificial layer with a thick insulating film, exposing an upper surface of the sacrificial layer, and removing the sacrificial layer Forming a gate insulating film on the surface of the semiconductor where the sacrificial layer has been removed, forming a step with the gate insulating film and the thick insulating film, and forming a gate electrode on a side surface of the step. Forming and forming a second source / drain region in the semiconductor by ion implantation using the gate electrode and the thick insulating film as a mask.
[0017]
In this manufacturing method, a sacrificial layer is formed, and first source / drain regions are formed using the sacrificial layer as a mask. The sacrificial layer is also used as a means necessary for forming the gate electrode in a self-aligned manner. That is, a thick insulating layer is formed so as to fill the periphery of the sacrificial layer, and a gate electrode is formed on a step formed by the thick insulating layer and the gate insulating film formed earlier. At this stage, a gate electrode, a thick insulating film, and a gate insulating film are formed on the semiconductor surface. Next, ion implantation for forming a second source / drain region is performed. At this time, the gate electrode and the thick insulating film function as a mask for blocking implanted ions. Therefore, the first source / drain region is formed, and the second source / drain region is formed in a portion of the semiconductor adjacent to the gate electrode, unlike a portion where a thick insulating film is formed thereon.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of an insulated gate field effect transistor (MISFET) and a method of manufacturing the same according to the present invention will be described with reference to the drawings, using a SOI MOS transistor having an N-type channel conductivity as an example. In the case where the MOS transistor is a P-type, the following description can be applied by analogy by setting the conductivity type of the impurity added to each part to the opposite polarity.
[0019]
FIG. 1 is a cross-sectional view of a semiconductor device including two adjacent MOS transistors.
In the semiconductor device 1 illustrated in FIG. 1, a buried insulating film 3 made of, for example, silicon oxide or the like is formed on a substrate 2 such as a semiconductor or glass. On the buried insulating film 3, a semiconductor (hereinafter, referred to as an SOI layer) 4 made of P-type single crystal silicon or the like and having an SOI-type substrate isolation structure is formed. The thickness of the SOI layer 4 differs depending on whether the transistor is of a partially depleted type or a fully depleted type. For example, the thickness of the SOI layer 4 for making it completely depleted is set to 50 nm or less.
As a method for forming such a thin SOI layer 4, a so-called substrate bonding method or a SIMOX (Separation by Implanted Oxygen) method can be employed.
[0020]
The SOI layer 4 is partially insulated, whereby an element isolation insulating layer 5 is formed. By being surrounded by the element isolation insulating layer 5, the SOI layer 4 which is a formation region of the MOS transistors TR1 and TR2 is formed in an island shape. On the SOI layer 4 and the element isolation insulating layer 5, a thick insulating film 9 made of, for example, silicon oxide is formed. The thick insulating film 9 has an opening substantially at the center of the SOI layer 4.
A gate insulating film 10 made of, for example, silicon oxide is formed on the surface of the SOI layer 4 exposed at the bottom of the opening of the thick insulating film 9. A sufficient step is formed by the difference in film thickness between the thin gate insulating film 10 and the thick insulating film 9. For example, a gate electrode 11 made of polysilicon whose conductivity is increased by adding an N-type impurity is formed on each of two side surfaces of the thick insulating film 9 opposed to each other. The cross section of the gate electrode 11 is formed in a substantially 1/4 elliptical shape. Hereinafter, this shape is referred to as a sidewall shape. The gate electrode 11 is formed on the gate insulating film 10. An insulating spacer (hereinafter, referred to as a sidewall spacer) 13 is formed on each of the curved surfaces of the two gate electrodes 11 facing each other.
[0021]
In the SOI layer 4, an N-type first source / drain region 8 is formed in a region below the thick insulating film 9. An N-type second source / drain region 12 is formed in a portion of the SOI layer 4 defined by a distance between two sidewall spacers 13. The second source / drain region 12 is shared by the two MOS transistors TR1 and TR2. Extension portions 12E extend from one end and the other end of the second source / drain region 12 toward the first source / drain region 8, respectively. The extension portion 12E has N-type, but is formed to have a shallower junction depth than the second source / drain region 12, and extends to a region below the sidewall spacer 13. The impurity concentration of the extension portion 12E desirably differs from the impurity concentration of the second source / drain region 12. For example, the impurity concentration of the extension portion 12E is set lower than the impurity concentration of the second source / drain region 12.
[0022]
The MOS transistors TR1 and TR2 thus formed are covered with the interlayer insulating film 14.
Three contact holes 15 and 16 penetrating the interlayer insulating film 14 in the thickness direction are formed. The center contact hole 16 reaches the second source / drain region 12 through the interlayer insulating film 14 and the gate insulating film 10. The other two contact holes 15 reach the first source / drain regions 8 through the interlayer insulating film 14 and the thick insulating film 9. A conductive material, for example, metal such as tungsten or polysilicon is buried in the contact hole.
Wiring layers 17 and 18 are formed on interlayer insulating film 14. The central wiring layer 18 is connected to the contact hole 16, and the remaining two wiring layers 17 are connected to the contact hole 15.
[0023]
In the MOS transistors TR1 and TR2 having such a structure, the first source / drain region 8 and the second source / drain region 12 (and 12E) have the impurity type, impurity concentration, and impurity implantation depth. At least one is different. Thereby, the impurity profile on the drain side necessary for suppressing or preventing the roll-off effect, the punch-through breakdown voltage due to DIBL, and the short channel effect, and the source necessary for reducing the source resistance for maintaining the driving capability and the like. With the impurity profile on the side. Therefore, it is necessary to perform impurity implantation on the source side and the drain side in separate steps. In the above-described structure, the thick insulating film 9 is formed on one side of the source or the drain, and the sidewall-shaped gate electrode 11 is formed on the side surface. Can be executed.
[0024]
Hereinafter, a method for manufacturing the semiconductor device illustrated in FIG. 1 will be described with reference to the drawings.
2A to 4B are cross-sectional views of the semiconductor device according to the embodiment of the present invention, which are being manufactured.
[0025]
For example, an SOI substrate, that is, a substrate in which the buried insulating film 3 is formed on the substrate 2 and the SOI layer 4 is formed on the buried insulating film 3 is formed by a substrate bonding method or a SIMOX method. The SOI layer 4 is made of single-crystal silicon to which a P-type impurity is added during or after the formation, and has a maximum thickness of 50 nm.
As shown in FIG. 2A, a part of the SOI layer 4 is insulated by a method such as a partial thermal oxidation method performed by masking a transistor formation region or an STI (Shallow Trench Isolation) method. An element isolation insulating layer 5 having a predetermined pattern is formed on the SOI layer 4.
[0026]
In FIG. 2B, a gate insulating film 6 is formed on the surface of the SOI layer 4 where the element isolation insulating layer 5 is not formed. The gate insulating film 6 is made of, for example, silicon oxide formed by a thermal oxidation method.
Next, the sacrificial layer 7 is formed. The sacrificial layer is a layer used for defining a groove shape in the groove gate process, and is a layer that is finally removed. More specifically, for example, polysilicon is deposited to a thickness of about 150 nm by a CVD (Chemical Vapor Deposition) method, and the formed polysilicon film is patterned into a pattern substantially similar to the gate electrode.
[0027]
In FIG. 2C, N-type impurity ions are implanted to form a first source / drain region 8, for example, a source region. For example, arsenic ions As as ion species⁺With an acceleration energy of 2.5 keV and a dose of 1.8 × 10^Fifteenions / cm²Then, ions are implanted into the SOI layer 4 at an implantation angle of 0 °. At this time, the sacrifice layer 7 and the element isolation insulating layer 5 function as a self-aligned mask, and the gate insulating film 6 serves as a protective film for preventing contamination of the SOI layer surface or a through film for reducing defects introduced during implantation. Function. Thus, N-type first source / drain regions 8 are formed in the SOI layer portions on both sides of the sacrificial layer 7.
If necessary, a step of forming a sidewall spacer on the side surface of the sacrificial layer 7 and implanting an N-type impurity under conditions different from the above may be added before the formation. Thus, the source region (the first source / drain region 8) has an extension structure, and the impurity profile can be precisely controlled. The source-side extension portion may have a higher concentration than the first source / drain region 8 in order to further reduce the source resistance.
[0028]
A thick insulating film 9 such as silicon oxide is deposited by a CVD method so as to completely cover the sacrificial layer 7.
Thereafter, as shown in FIG. 3A, the surface of the thick insulating film 9 is polished by a technique such as CMP (Chemical Mechanical Polishing). Polishing is performed until the upper surface of the sacrificial layer 7 is exposed. As a result, the thickness of the thick insulating film 9 is substantially equal to the thickness of the sacrificial layer 7, and the surfaces thereof are flattened.
[0029]
As shown in FIG. 3B, the exposed sacrificial layer 7 is removed by, for example, a wet process. When the sacrificial layer 7 is made of polysilicon, for example, 0.5% ethylenediamine (NH₂(CH₂) 2NH₂A) The treatment using the aqueous solution is performed at room temperature (20 ° C) for about 2 minutes. This 2-minute processing time corresponds to a case where an overetch of about 100% is performed at an etch rate of 160 nm / min.
Subsequently, the gate insulating film 6 is etched using an HF-based solution and removed. Then, the gate insulating film 10 is formed again on the surface of the SOI layer 4 by, for example, a thermal oxidation method.
Note that the gate insulating film 6 may be left as it is without being removed and used as a gate insulating film of a transistor. In that case, the step of removing the gate insulating film 6 and the step of forming the gate insulating film 10 can be omitted. However, here, the gate insulating film is formed again from the viewpoint of ensuring film quality and reliability.
[0030]
Polysilicon as a gate electrode material is deposited to a thickness of about 100 nm using, for example, a vertical CVD apparatus. Silane SiH as a source gas for CVD₄, Hydrogen H₂, Nitrogen N₂Are mixed at a flow rate of 30 sccm, 100 sccm, and 500 sccm, respectively. The substrate temperature is 610 ° C., and the furnace pressure is 40 Pa.
The deposited polysilicon film is entirely etched (etched back) using, for example, an ECR (Electron Cyclotron Resonance) type plasma etcher. Hydrogen bromide HBr, chlorine Cl as etching gas₂Are mixed at a flow rate of 95 sccm and 15 sccm, respectively. The temperature in the chamber is set to 20 ° C., the pressure is set to 0.5 Pa, and micropower 400 W and RF power 25 W are applied. When etch-back is performed for a predetermined time under these conditions, a so-called sidewall-shaped gate electrode 11 is formed on the side surface (groove side surface) of the thick insulating film 9 as shown in FIG.
Note that, since the gate electrode 11 is formed around the groove, a step of electrically separating the two transistors is required in this case.
[0031]
In the step shown in FIG. 4A, N-type impurity ions are implanted to form extension portions of the second source / drain regions. For example, boron fluoride ion BF as an ion species₂ ⁺With an acceleration energy of 2.5 keV and a dose of 2.0 × 10¹⁴ions / cm²Then, ions are implanted into the SOI layer 4 at an implantation angle of 0 °. At this time, the gate electrode 11 and the thick insulating film 9 function as a self-aligned mask, and the gate insulating film 10 functions as a protective film for preventing contamination of the surface of the SOI layer or a through film for reducing defects introduced at the time of implantation. I do. As a result, an N-type extension 12E is formed in the SOI layer defined by the distance between the two gate electrodes 11.
Next, for example, a silicon oxide film is CVD-processed and etched back. Thereby, the sidewall spacers 13 are formed on the curved surfaces of the two gate electrodes 11 facing each other.
[0032]
As shown in FIG. 4B, N-type impurity ions are implanted to form a second source / drain region. For example, boron ion B as an ion species⁺With an acceleration energy of 1.0 keV and a dose of 3.0 × 10^Fifteenions / cm²Then, ions are implanted into the SOI layer 4 at an implantation angle of 0 °. At this time, the sidewall spacer 13, the gate electrode 11, and the thick insulating film 9 function as a self-alignment mask, and the gate insulating film 10 is used as a protective film for preventing contamination of the SOI layer surface or a defect introduced at the time of implantation. It functions as a through film to reduce. Thereby, the second source / drain region 12 is formed in the SOI layer portion defined by the distance between the two sidewall spacers 13.
After that, heat treatment (annealing) for activating the implanted impurities is performed. RTA (Rapid Thermal Annealing) can be used for annealing. At this time, RTA is changed to, for example, nitrogen N₂This is performed for about 10 seconds on a substrate held at 950 ° C. in an atmosphere.
[0033]
Thereafter, although not particularly shown, an interlayer insulating film 14 is deposited, and the interlayer insulating film 14 is planarized as necessary. Further, formation of a contact hole, embedding of a metal, and formation of a wiring are sequentially performed to complete the semiconductor device 1.
[0034]
The case where the present invention is applied to the SOI type NMOS transistor has been described above, but this is merely an example. Embodiments of the present invention are not limited to the above-described device structure, its forming conditions, and the like.
For example, the transistor may be formed on a bulk silicon substrate. Even in the case of an SOI transistor, the design of the type of the SOI substrate, the thickness of the SOI layer, and the like can be changed as appropriate.
Although the method for manufacturing an NMOS transistor has been described, the present invention can be applied to a PMOS transistor by changing the conductivity type of an impurity.
In the example illustrated in FIG. 1, the second source / drain region 12 is shared by two transistors, but can be provided separately. For example, a portion of the SOI layer 4 where the second source / drain region 12 is formed is widened in advance, an element isolation insulating layer 5 is provided in the middle, and a contact hole 16 and a wiring 18 are further formed in the source / drain region. It is provided for every 12.
A transistor having a CMOS structure can be manufactured by using a mask to separate impurities.
[0035]
The sacrificial layer 7 is made of silicon nitride Si besides polysilicon.₃N₄, Or a metal film such as tungsten W. The gate electrode 11 formed on the side surface of the groove formed after removing the sacrificial layer 7 may be made of a metal having a high melting point other than polysilicon.
[0036]
Contrary to the above description, the first source / drain region 8 formed first may be used as a drain, and the second source / drain region 12 formed later may be used as a source. In this case, the extension portion may be provided in the first source / drain region 8, and the formation of the extension portion 12E on the second source / drain region side may be omitted.
[0037]
In addition to the heat treatment (RTA) performed after the formation of the second source / drain region 12, a heat treatment step may be added after the formation of the first source / drain region and before the formation of the second source / drain region 12. . When the total amount of heating for the two source / drain regions 8 and 12 needs to be adjusted, in this embodiment, since the two source / drain regions 8 and 12 are formed in different steps, such control of the heat treatment is easy. It becomes.
[0038]
In the present embodiment, since the two source / drain regions 8 and 12 are formed in different steps, the carrier lifetime can be independently controlled on the source side and the drain side. Specifically, for example, in order to suppress the FBE of the SOI transistor, a method of intentionally introducing a crystal defect into the source region can be adopted.
[0039]
FIG. 5 shows a cross-sectional view when a crystal defect is introduced.
In this example, prior to the step of FIG. 5, the drain region (first source / drain region 8) is formed first in the step of FIG. 2C, and then the source region is formed in the step of FIG. (The second source / drain region 12) is preferably formed.
A source region 12 is formed, heat treatment for activation is performed, and then, as shown in FIG.⁺Etc. are injected. As a result, argon ions are implanted only in the source region 12, so that the recombination center density of carriers is increased only on the source side, and the carrier lifetime is reduced. Subsequent deposition of an interlayer insulating film, formation of a contact hole, and formation of a wiring are performed at a temperature as low as possible.
Through the above steps, it is possible to make a large difference in the value of the lifetime between the source and the drain of the formed MOS transistor. In addition to the argon ion implantation, the carrier lifetime can be locally reduced by doping with gold Au.
[0040]
In the present embodiment, the following effects can be obtained.
First, it is possible to independently design a process and a device for a source region and a drain region. For example, the optimum impurity type, concentration, profile, thermal process, and the like can be set for the source region and the drain region, respectively.
This makes it possible to suppress the short-channel effect and increase the driving capability while making the structure and characteristics of the MOS asymmetric. That is, the aforementioned trade-off can be overcome.
[0041]
Secondly, although the drain breakdown voltage has been compromised to some extent in the past, the above trade-off can be resolved and the drain breakdown voltage is relatively improved, so that the off current (junction leakage current) can be reduced. In addition, generation of hot holes can be suppressed by relaxing the electric field at the drain end of the channel, whereby deterioration of the film quality of the gate insulating film 10 can be prevented.
In particular, in the above embodiment applied to an SOI transistor, when this transistor is used as an element of a signal processing circuit, the history dependence of the signal delay time can be eliminated or reduced without increasing the off current (junction leakage current). . One phenomenon of FBE occurs in that holes generated by impact ionization on the drain side are accumulated in the body region (SOI layer 4) and the body potential fluctuates. The history dependence of the signal delay time is caused by the fact that the amount of accumulated holes changes with time.
In order to reduce the history dependence of the signal delay time, it is desirable that holes be quickly released from the source.
In the present embodiment, since the drain region and the source region can be formed independently, the withstand voltage (leak current amount) of the drain is maintained or reduced, and the barrier height for the source-side hole is reduced, or the source resistance is reduced. This makes it possible to simultaneously withdraw the hole from the body region.
The coexistence of the reduction of the leak and the suppression of the FBE can be more easily achieved by introducing the defect into the source region described above. In other words, if a defect is introduced on the drain side, the leakage current increases. Therefore, in order to suppress the accumulation of holes, a defect is introduced only on the source side to increase the recombination center density of the carrier, and the carrier is limited in the region limited to the source side. Reduce lifetime. As a result, the history dependency of the signal delay time can be further reduced while suppressing an increase in the leak current.
[0042]
Third, the source region and the drain region, that is, the first and second source / drain regions 8, 12 and the extension portion 12E are all formed by a self-alignment process. Specifically, the first source / drain region 8 is formed in a self-alignment manner with respect to the sacrificial layer 7 formed first, and the thick insulating film 9 is formed in a self-alignment manner with respect to the sacrificial layer 7. Is done. A gate electrode 11 is formed on the thick insulating film 9 in a self-aligned manner, and a second source / drain region 12 and an extension 12E are formed on the gate electrode 11 in a self-aligned manner. These self-aligned processes do not require additional masks and do not add significant cost.
[0043]
Fourth, the degree of freedom in designing the gate electrode 11 (height, density, and the like) or layout is greater in the impurity region forming method of the present embodiment than in the oblique ion implantation method.
[0044]
【The invention's effect】
According to the method of forming an insulated gate field effect transistor according to the present invention, the impurity profile of the source / drain region can be independently determined on the source side and the drain side by changing the impurity type, concentration, ion implantation energy, thermal process (lifetime). ) Can be controlled. As a result, it has become easy to improve the characteristics and reliability and to secure the degree of freedom in design.
According to the insulated gate field effect transistor of the present invention, excellent characteristics and high reliability are realized.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a portion including two adjacent MOS transistors in a semiconductor device according to an embodiment of the present invention.
FIGS. 2A to 2C are cross-sectional views showing up to an ion implantation step for forming a first source / drain region in the manufacture of the semiconductor device according to the embodiment of the present invention;
FIGS. 3A to 3C are cross-sectional views subsequent to FIG. 2C and show steps up to the formation of a gate electrode.
FIGS. 4A and 4B are cross-sectional views subsequent to FIG. 3C, showing up to an ion implantation step for forming a second source / drain region.
FIG. 5 is a cross-sectional view at the time of introducing a crystal defect, which can be adopted as an additional step in the embodiment of the present invention.
FIG. 6 is a cross-sectional view of a MOSFET during oblique ion implantation in a conventional method for forming source / drain regions.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 semiconductor device, 2 substrate, 3 buried insulating film, 4 semiconductor SOI layer on which channel is formed, 5 element isolation insulating layer, 6 gate insulating film, 7 sacrifice layer, 8 first source A drain region, 9 a thick insulating film, 10 a gate insulating film, 11 a gate electrode, 12 a second source / drain region, 12E an extension portion, 13 a sidewall spacer, 14 an interlayer insulating film, 15 , 16 ... contact hole, 17, 18 ... wiring layer

Claims (8)

Forming a sacrificial layer on the semiconductor on which the channel is formed;
Forming a first source / drain region in the semiconductor by ion implantation using the sacrificial layer as a mask;
Covering the periphery of the sacrificial layer with a thick insulating film;
Exposing the upper surface of the sacrificial layer and removing the sacrificial layer;
Forming a gate insulating film on the surface of the semiconductor where the sacrificial layer has been removed, and forming a step with the gate insulating film and the thick insulating film;
Forming a gate electrode on the side surface of the step;
Forming a second source / drain region in the semiconductor by ion implantation using the gate electrode and the thick insulating film as a mask;
A method for manufacturing an insulated gate field effect transistor, comprising: In the step of forming the sacrifice layer, a sacrifice layer is formed in a pattern of a gate electrode, and the steps from the step of forming the first source / drain region to the step of forming the second source / drain region are performed. 2. The method for manufacturing an insulated gate field effect transistor according to claim 1, wherein two insulated gate field effect transistors sharing the second source / drain region are collectively formed on both sides of the layer pattern. The first source / drain region and the second source / drain region have the same conductivity type, but differ in at least one of the type of impurity implanted, the impurity concentration, and the impurity distribution shape. The method for manufacturing an insulated gate field effect transistor according to claim 1. The step of forming the first source / drain region includes:
Forming an extension portion by ion implantation using the sacrificial layer as a mask,
Forming a sidewall spacer on a side surface of the sacrificial layer;
Forming an impurity region whose junction depth with the semiconductor is deeper than the extension portion by ion implantation using the sidewall spacer and the sacrificial layer as a mask;
The method for manufacturing an insulated gate field effect transistor according to claim 1, comprising: The step of forming the second source / drain region includes:
Forming an extension portion by ion implantation using the sacrificial layer and the gate electrode as a mask,
Forming a sidewall spacer on a side surface of the gate electrode;
A step of forming an impurity region whose junction depth with the semiconductor is deeper than the extension portion by ion implantation using the sidewall spacer, the gate electrode and the sacrificial layer as a mask,
The method for manufacturing an insulated gate field effect transistor according to claim 1, comprising: 2. The method according to claim 1, further comprising a heat treatment step between the step of forming the first source / drain region and the step of forming the second source / drain region. 2. The method of manufacturing an insulated gate field effect transistor according to claim 1, further comprising a step of introducing a defect that changes carrier lifetime into the formed second source / drain region. A first conductivity type semiconductor in which a channel is formed;
A gate insulating film formed on the semiconductor;
A gate electrode formed on the gate insulating film;
A first source / drain region of a second conductivity type formed in a portion of the semiconductor on one side of the gate electrode;
A second conductive type second electrode formed in the semiconductor portion on the other side of the gate electrode and different from the first source / drain region in at least one of an impurity type, an impurity concentration, and an impurity implantation depth. Source / drain impurity regions of
An insulated gate field effect transistor comprising:

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