JP2012182478A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which suppresses body floating effect, and to provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device having a silicon on insulator (SOI) structure includes: a silicon substrate 1; an embedded insulation layer 2 formed on the silicon substrate 1; and a semiconductor layer 3 formed on the embedded insulation layer 2. The semiconductor layer 3 has a first conductive type body region 4, a second conductive type source region 5, and a second conductive type drain region 6, and a gate electrode 8 is formed on the body region 4 between the source region 5 and the drain region 6 via a gate oxide film 7. The source region 5 includes a second conductive type extension layer 52 and a silicide layer 51 contacting with the extension layer 52 at a side surface. A crystal defect region 12 is formed in a region of a depletion layer occurring in a boundary portion between the silicide layer 51 and the body region 4.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a semiconductor device having an SOI (Silicon on Insulator) structure and a manufacturing method thereof.

  Conventionally, in a MOS transistor having an SOI structure, a buried oxide film is formed on a silicon substrate, and a thin film silicon layer as a semiconductor layer is formed on the oxide film. A source region, a body region, and a drain region are formed in the thin film silicon layer, and a gate electrode is formed on the body region between the source region and the drain region via a gate insulating film, thereby forming a transistor. Has been. Note that by making the body region P-type and the source and drain regions N-type, the MOS transistor becomes an N-channel type.

  The SOI structure MOS transistor is formed so that the buried oxide film is in contact with the source region and the drain region in order to reduce the parasitic capacitance of the source region and the drain region. Further, the periphery of the MOS transistor is covered with an element isolation oxide film after the thin film silicon layer is removed. As inventions related to the SOI structure MOS transistor as described above, there are the following Patent Document 1 and Patent Document 2.

JP 2003-332579 A JP 2003-197634 A

  In the conventional MOS transistor in the SOI structure, the side surface of the P-type body region is surrounded by the N-type source region and drain region, so that a PN junction is formed in this portion. Further, since the buried oxide film is provided on the bottom surface of the body region, the potential of the body region is in a floating state.

  Therefore, in the conventional MOS transistor in the SOI structure, a phenomenon such as a drain current kink phenomenon called a body floating effect, a decrease in source-drain breakdown voltage, and an operating frequency dependency (history effect) of circuit operation time occurs, which is large in operation. There was a problem.

  Therefore, an object of the present invention is to provide a semiconductor device capable of suppressing the body floating effect and a manufacturing method thereof.

  A solution according to the present invention is an SOI structure semiconductor device including a silicon substrate, a buried insulating layer formed on the silicon substrate, and a semiconductor layer formed on the buried insulating layer, A first conductivity type body region, a second conductivity type source region, and a second conductivity type drain region are formed, and a gate electrode is formed on the body region between the source region and the drain region via a gate oxide film. The source region includes a second conductivity type extension layer and a silicide layer in contact with the extension layer on the side surface, and a crystal defect region is formed in a depletion layer region formed at a boundary portion between the silicide layer and the body region. .

  In the semiconductor device described in the present invention, since the crystal defect region is formed in the depletion layer region generated at the boundary between the silicide layer and the body region, the reverse leakage current increases and the body potential becomes the source potential. There is an effect that can be fixed and the body floating effect can be suppressed.

It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. FIG. 3 is a potential diagram of the semiconductor device according to the first embodiment of the present invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 6 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 6 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 6 of this invention. It is a top view of the semiconductor circuit which concerns on Embodiment 7 of this invention. It is a top view of the semiconductor circuit which concerns on Embodiment 7 of this invention. It is a top view of MOSFET using the source tie structure concerning Embodiment 8 of this invention. It is sectional drawing of MOSFET using the source tie structure concerning Embodiment 8 of this invention. It is sectional drawing of MOSFET using the source tie structure concerning Embodiment 8 of this invention. It is a circuit diagram of SRAM which concerns on Embodiment 9 of this invention. It is a top view of SRAM which concerns on Embodiment 10 of this invention. It is a top view of the partial trench isolation structure which concerns on Embodiment 10 of this invention. It is sectional drawing of the partial trench isolation structure which concerns on Embodiment 10 of this invention.

(Embodiment 1)
FIG. 1 shows a cross-sectional view of the semiconductor device according to the present embodiment. The semiconductor device shown in FIG. 1 employs an SOI structure in which a buried oxide film 2 is formed on a silicon substrate 1 and a semiconductor layer 3 is further formed on the buried oxide film 2. Since an N-channel MOS transistor is formed in the semiconductor layer 3, a P-type body region 4, an N-type source region 5 and a drain region 6 are provided.

  The source region 5 includes a Co silicide layer 51 that contacts the body region 4 at the bottom surface, and an N-type source extension layer 52 that contacts the side surface of the Co silicide layer 51. The drain region 6 is embedded in the N-type drain diffusion layer 61 in contact with the buried oxide film 2, the N-type drain extension layer 62 in contact with the side surface of the drain diffusion layer 61, and the N-type drain diffusion layer 61. And a Co silicide layer 63 formed on the substrate.

  On the body region 4 between the source region 5 and the drain region 6, gate polysilicon 8 constituting a gate electrode is formed via a gate oxide film 7. The gate polysilicon 8 has a Co silicide layer 9 formed on the top surface and a sidewall oxide film 10 formed on the side surface. Further, the N-channel MOS transistor shown in FIG. 1 is isolated from other elements by an element isolation oxide film 11.

In the semiconductor device shown in FIG. 1, the bottom surface of the Co silicide layer 51 is in contact with the body region 4. The contact between the Co silicide layer 51 and the body region 4 is not an ohmic contact but a Schottky junction because the P-type impurity concentration in the body region 4 is usually as thin as about 10 ¹⁸ / cm ³ . However, the roughness at the interface between the Co silicide layer 51 and the body region 4 is large, and the leakage current at the Schottky junction is larger than the leakage current at the normal PN junction. Further, since the area where the Co silicide layer 51 and the body region 4 are in contact with each other is relatively large, the Co silicide layer 51 and the body region 4 are electrically connected.

  Furthermore, since the Co silicide layer 51 and the source extension layer 52 are in ohmic contact, the body region 4, the Co silicide layer 51, and the source extension layer 52 are electrically connected. Therefore, the potential of the body region 4 (body potential) is fixed to the source potential via the resistances of the Co silicide layer 51 and the source extension layer 52.

  As shown in FIG. 1, in the present embodiment, a crystal defect region 12 is further formed in a depletion layer generated at the boundary portion between the Co silicide layer 51 and the body region 4. By providing the crystal defect region 12 in a depletion layer generated at the boundary between the Co silicide layer 51 and the body region 4, the reverse leakage current of the Schottky junction can be increased. Here, FIG. 2 shows a potential diagram of the boundary portion between the Co silicide layer 51 and the body region 4. In FIG. 2, a depletion layer is formed on the body region 4 side of the boundary portion, and crystal defects of the crystal defect region 12 exist in this depletion layer portion. Since holes in the valence band flow to the Co silicide layer 51 through crystal defects in the depletion layer, the reverse leakage current of the Schottky junction increases.

  Note that Ev shown in FIG. 2 represents the potential at the upper end of the valence band, and Ec represents the potential at the lower end of the conduction band. Further, Ef represents the Fermi level of the body region 4, and Efm represents the Fermi level of the Co silicide layer 51. In addition, it is considered that the depletion layer shrinks by providing crystal defects and becomes several tens of nm or less.

  As described above, in this embodiment, the body potential is fixed to the source potential via the resistances of the Co silicide layer 51 and the source extension layer 52. Furthermore, by providing the crystal defect region 12, the contact resistance between the body potential and the source potential is reduced, and the temporal followability of the body potential to the source potential is improved.

Next, a method for manufacturing a semiconductor device according to the present embodiment will be described. FIG. 3 shows a cross-sectional view of a semiconductor device in which only the source extension layer 52 is formed in the source region 5 and only the drain extension layer 62 is formed in the drain region 6. The outline of the process until the semiconductor device shown in FIG. 3 is formed will be described below. First, a trench is provided in the semiconductor layer 3 of the SOI substrate to form an element isolation oxide film 11. Next, a gate oxide film 7 is formed by thermal oxidation, and a gate polysilicon 8 is provided on the gate oxide film 7 to form a gate electrode. Then, about 10 ¹⁴ ions / cm ^{2 of} N-type impurities are implanted into the semiconductor layer 3 by an ion implantation method to form the source extension layer 52 and the drain extension layer 62. Next, a sidewall oxide film 10 is formed by depositing a silicon oxide film on the semiconductor layer 3 and anisotropically etching the silicon oxide film.

After the semiconductor device shown in FIG. 3 is formed, the crystal defect region 12 is formed in this embodiment. In the semiconductor device shown in FIG. 3, by implanting about 10 ¹⁴ pieces / cm ² of silicon ions into the crystal defect formation region 13 indicated by the broken line, the crystallinity of the region is destroyed or many crystal defects are generated. Note that the ions to be implanted may be other than silicon as long as the band structure is changed and the reverse leakage current is increased by destroying the crystallinity or generating many crystal defects. For example, germanium, nitrogen, oxygen, aluminum, iron, etc. can be considered.

  Crystal defects are formed by the implantation of silicon ions not only in the source region but also in the drain region as shown in FIG. However, as shown in FIG. 1, in this embodiment, the drain diffusion layer 61 reaching the buried oxide film 2 is formed, so that the crystal defects formed in the drain region are completely covered. Therefore, no increase in reverse leakage current occurs in the PN junction formed in the drain region.

  Further, as in the semiconductor device shown in FIG. 4, the photoresist 14 may be formed only in the drain region by using an optical lithography technique so that silicon ions are not implanted into the drain region. That is, the crystal defect region 12 can be formed only in the source region by adding a step of forming the photoresist 14 before the step of implanting silicon ions.

Specifically, a manufacturing method for forming the drain diffusion layer 61 will be described with reference to FIGS. First, a photoresist 15 is formed only on the source region using an optical lithography technique. FIG. 5 shows a state in which the photoresist 15 is formed only on the left side from the middle of the gate electrode. Then, using this photoresist 15 as a mask, arsenic ions are implanted only into the drain region by an ion implantation method. The number of arsenic ions to be implanted is about 10 ¹⁵ ions / cm ² . After the implantation, the deep drain diffusion layer 61 reaching the buried oxide film 2 can be formed by removing the photoresist 15 and thermally annealing the semiconductor device at about 1000 ° C.

  Next, a Co film is deposited on the semiconductor layer 3 and annealed to form a Co silicide layer 51 in the source region and a Co silicide layer 63 in the drain region. Here, the Co silicide layer 51 is formed deeper than the source extension layer 52, and the boundary between the Co silicide layer 51 and the body region 4 is located at the position of the crystal defect forming region 13 shown in FIG. As a result, the Co silicide layer 51 forms a PN junction with the body region 4, and the crystal defect region 12 is formed in the depletion layer formed at the boundary between the Co silicide layer 51 and the body region 4. Directional leakage current increases.

  As described above, in the semiconductor device according to the present embodiment, since the crystal defect region 12 is formed in the depletion layer generated at the boundary between the Co silicide layer 51 and the body region 4, the semiconductor device according to the present embodiment. Then, the body potential can be fixed to the source potential, and the body floating effect can be suppressed. Furthermore, in the semiconductor device according to the present embodiment, the reverse leakage current flowing between the Co silicide layer 51 and the body region 4 increases, so that the followability of the body potential to the source potential is improved. In this embodiment, the Co silicide layers 9, 51, 63 are formed. However, the present invention is not limited to this, and a layer silicided with a material other than Co, such as a Ni silicide layer, may be used.

(Embodiment 2)
In a semiconductor device with an SOI structure, the body floating effect can be suppressed by reducing the generation of hot carriers. In order to reduce the generation of hot carriers, the electric field in the drain region on the gate electrode side may be relaxed. In other words, the electric field in the drain region on the gate electrode side can be reduced by making the source region a source impurity structure with low parasitic resistance and an asymmetric source-drain structure. The semiconductor device according to the present embodiment employs the above structure.

Specifically, the semiconductor device according to the present embodiment will be described. First, the structure of the semiconductor device according to the present embodiment is basically the same as the structure shown in FIG. However, the present embodiment is different from the first embodiment in that the impurity concentration of the source extension layer 52 and the impurity concentration of the drain extension layer 62 are different. For example, the impurity concentration of the source extension layer 52 is, for example, about 10 ²¹ / cm ³ , whereas the impurity concentration of the drain extension layer 62 is, for example, about 10 ²⁰ / cm ³ .

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described. First, since the source extension layer 52 and the drain extension layer 62 are formed simultaneously by implanting arsenic ions, which are N-type impurities, into the semiconductor layer 3, the impurity concentration of the source extension layer 52 and the impurities of the drain extension layer 62 are formed. The concentration is the same. Therefore, in the present embodiment, a process shown in FIG. 6 is added in order to change the impurity concentration between the source extension layer 52 and the drain extension layer 62.

In the manufacturing process shown in FIG. 6, following the process shown in FIG. 5 of the first embodiment, in order to reduce the effective impurity concentration only in the drain extension layer 62, P-type impurities (for example, boron) are implanted from an oblique direction. Add a process. Note that the number of P-type impurities implanted into the drain extension layer 62 is, for example, about 10 ¹⁹ / cm ³ . As described above, in the semiconductor device shown in FIG. 6, by implanting the P-type impurity into the drain extension layer 62, the N-type impurity (arsenic) in the drain extension layer 62 is compensated to reduce the effective impurity concentration, and the gate The electric field at the end of the drain region on the electrode side can be lowered.

  As described above, the semiconductor device according to this embodiment has a source-drain structure in which the impurity concentration is asymmetric, so that the body floating effect due to hot carriers can be suppressed and the transistor resistance can be reduced by reducing the parasitic resistance of the source region. Driving current can be improved.

In the present embodiment, a P-type impurity is implanted into the drain extension layer 62 to form an asymmetric source / drain structure. However, the present invention is not limited to this, and the source extension layer 52 has an N-type structure. A source-drain structure having an asymmetric impurity concentration may be formed by implanting impurities. For example, the source extension layer 52 and the drain extension layer 62 are formed at an impurity concentration of about 10 ²⁰ atoms / cm ³ , and arsenic ions are implanted only into the source extension layer 52 by an ion implantation method in a later step. The impurity concentration of the layer 52 is set to about 10 ²¹ / cm ³ .

(Embodiment 3)
FIG. 7 shows a cross-sectional view of the semiconductor device according to the present embodiment. The semiconductor device shown in FIG. 7 is different in configuration from the source region 5 shown in FIG. 7 is the same as the semiconductor device shown in FIG. 1 except for the source region 5, and therefore, the same components are denoted by the same reference numerals and detailed description thereof is omitted.

  The source region 5 shown in FIG. 7 is formed in the source extension layer 52 formed in the vicinity of the gate oxide film 7, the Co silicide layer 51 formed in the side surface direction of the source extension layer 52, and the lower layer of the Co silicide layer 51. The N-type source diffusion layer 53 and the P-type diffusion layer 54 formed under the source diffusion layer 53 are configured. The P-type diffusion layer 54 is in contact with the source diffusion layer 53 in a wider area than the area where the source diffusion layer 53 and the body region 4 are in contact. Further, the P type diffusion layer 54 has a higher impurity concentration than the body region 4.

In this case, the leakage current that flows between the P-type diffusion layer 54 and the source diffusion layer 53 increases more than the leakage current that flows between the body region 4 and the source diffusion layer 53, so the body potential is set to the source potential. Can be fixed. The reason why the leakage current increases will be described in more detail. First, generally, a depletion layer due to a junction diffusion potential difference spreads at the junction interface between the P-type and the N-type. However, if the impurity concentration is high as in the junction interface between the P-type diffusion layer 54 and the source diffusion layer 53, the depletion layer does not spread and the electric field becomes steep. Therefore, at the junction interface between the P-type diffusion layer 54 and the source diffusion layer 53, the electric field becomes steep, a tunnel current flows in a quantum manner, and an electric field-induced leakage current increases. Here, the leakage current increases as the impurity concentration increases, but it is sufficient that the impurity concentration is at least 10 ¹⁸ / cm ³ or more.

Next, a method for manufacturing the P-type diffusion layer 54 shown in FIG. 7 will be described. In the semiconductor device shown in FIG. 8, in order to further form the source diffusion layer 53 and the drain diffusion layer 61 in the semiconductor device formed by using the same manufacturing process as that of the above embodiment, a photoresist is used by using a photolithography technique. 16 is formed only on the drain region 6. Then, in order to form the P-type diffusion layer 54, boron ions of about 10 ¹⁵ ions / cm ² are implanted using the photoresist 16 as a mask. Note that the range of boron ions is in the vicinity of the buried oxide film 2 in the source region 5. Thereby, the P-type diffusion layer 54 shown in FIG. 7 can be formed.

  As described above, in the semiconductor device according to the present embodiment, by providing the P-type diffusion layer 54, the body potential can be fixed to the source potential, and the body floating effect can be suppressed. Note that the asymmetric source-drain structure described in Embodiment 2 may be applied to the semiconductor device according to this embodiment. In this embodiment, the Co silicide layers 9, 51, 63 are formed. However, the present invention is not limited to this, and a layer silicided with a material other than Co, such as a Ni silicide layer, may be used.

(Embodiment 4)
In the semiconductor device shown in FIG. 1, the bottom surface of the source extension layer 52 is in contact with only the Co silicide layer 51. Therefore, the source extension layer 52 is in contact only with the side surface portion of the Co silicide layer 51, and the contact resistance between the source extension layer 52 and the Co silicide layer 51 is increased. Therefore, the contact resistance becomes a parasitic resistance to a current path that flows from the Co silicide layer 51 through the source extension layer 52 to the channel inversion layer under the gate electrode, which may cause a reduction in the on-current of the transistor. .

  Therefore, in the semiconductor device according to the present embodiment, the bottom surface of the Co silicide layer 51 has a mixture of a region in contact with the source extension layer 52 and a region in contact with the body region 4 in the bottom surface of the Co silicide layer 51. A region in contact with the source extension layer 52 is also provided in the portion to reduce the contact resistance between the Co silicide layer 51 and the source extension layer 52. FIG. 9 is a cross-sectional view of the semiconductor device according to this embodiment. The semiconductor device shown in FIG. 9 is basically the same as the semiconductor device shown in FIG. 1, but the bottom surface portion of the Co silicide layer 51 is different.

  That is, in the semiconductor device shown in FIG. 1, the bottom surface of the Co silicide layer 51 is joined only to the body region 4, but in the semiconductor device shown in FIG. 9, the bottom surface of the Co silicide layer 51 is connected to the source extension layer 52. The area in contact with and the area in contact with the body area 4 are mixed. Specifically, the mixed state will be described. First, as shown in FIG. 9, the bottom surface of the Co silicide layer 51 has an uneven shape. Therefore, if the bottom surface of the source extension layer 52 is located in the middle of the uneven shape, the convex portion of the Co silicide layer 51 is in contact with the body region 4 and the concave portion is in contact with the source extension layer 52.

  Here, when the Co silicide layer 51 having a film thickness of about 20 nm to 60 nm is formed, the amplitude of the uneven shape formed on the bottom surface is about 5 nm to 10 nm. Therefore, it is possible in manufacturing technology to set the depth of the source extension layer 52 so that the bottom surface of the source extension layer 52 is positioned in the middle of the uneven shape of the Co silicide layer 51. The bottom surface of the Co silicide layer 63 formed in the drain region 6 has an uneven shape as well, but unlike the source region 5, the drain diffusion layer 61 is formed. Will only come into contact with.

  As described above, in the semiconductor device according to the present embodiment, since the region where the bottom surface of the Co silicide layer 51 is in contact with the source extension layer 52 and the region where the body region 4 is in contact are mixed, the Co silicide layer 51 and the source The contact area with the extension layer 52 is increased, and the parasitic resistance against the on-current of the transistor can be suppressed. In the semiconductor device according to the present embodiment, since the Co silicide layer 51 is also in contact with the body region 4, the body potential can be fixed to the source potential, and the body floating effect can be suppressed.

  Note that the asymmetric source-drain structure described in Embodiment 2 may be applied to the semiconductor device according to this embodiment. In this embodiment, the Co silicide layers 9, 51, 63 are formed. However, the present invention is not limited to this, and a layer silicided with a material other than Co, such as a Ni silicide layer, may be used.

(Embodiment 5)
FIG. 10 is a cross-sectional view of the semiconductor device according to this embodiment. Similarly to the fourth embodiment, the semiconductor device according to the present embodiment is configured to suppress the contact resistance between the Co silicide layer 51 and the source extension layer 52. Specifically, in the present embodiment, as shown in FIG. 10, all or most of the Co silicide layer 51 is formed on the semiconductor layer 3. With this structure, the entire bottom surface of the Co silicide layer 51 is in contact with the source extension layer 52, and the source extension layer 52 is in contact only with the side surface of the Co silicide layer 51 as shown in FIG. Compared with the above, the contact area becomes larger and the contact resistance can be reduced.

  However, since the Co silicide layer 51 is not in direct contact with the body region 4 in the semiconductor device shown in FIG. 10, a P-type diffusion layer that connects the Co silicide layer 51 and the body region 4 in order to fix the body potential to the source potential. 55 must be provided.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described below. Although not shown, first, a trench is provided in the semiconductor layer 3 of the SOI substrate to form an element isolation oxide film 11. Next, a gate oxide film 7 is formed by thermal oxidation, and a gate polysilicon 8 is provided on the gate oxide film 7 to form a gate electrode. Then, arsenic ions, which are N-type impurities, are implanted into the semiconductor layer 3 by an ion implantation method to form the source extension layer 52 and the drain extension layer 62. Next, a sidewall oxide film 10 is formed by depositing a silicon oxide film on the semiconductor layer 3 and anisotropically etching the silicon oxide film.

  Further, in the present embodiment, a single crystal layer of silicon is grown on the semiconductor layer 3 in the source region 5 and the drain region 6 by using a selective epitaxial growth technique to form the epitaxial growth layer 18. FIG. 11 shows a cross-sectional view of the semiconductor device in which the epitaxial growth layer 18 is formed. When the selective epitaxial growth technique is used, a silicon single crystal layer does not grow on an insulating film such as an oxide film, but a silicon single crystal layer grows on the gate polysilicon 8. Therefore, before the selective epitaxial growth technique is used, a cap oxide film 19 is formed on the gate polysilicon 8 so that a single crystal layer of silicon is not grown on the gate polysilicon 8.

  Next, using an optical lithography technique or the like, an N-type impurity is implanted only in the drain region by an ion implantation method to form a deep drain diffusion layer 61 (not shown). Then, a P-type impurity is implanted into a part of the source region by ion implantation to form a P-type diffusion layer 55 (not shown). Further, the cap oxide film 19 on the gate polysilicon 8 is removed. FIG. 12 shows a cross section of the semiconductor device after the cap oxide film 19 is removed.

  Next, a Co film is deposited on the semiconductor device shown in FIG. 12 by a sputtering method and annealed. By this treatment, the epitaxial growth layer 18 is silicided to become Co silicide layers 51 and 63, and part of the gate polysilicon 8 is silicided to become the Co silicide layer 9. Depending on the annealing conditions, a part of the epitaxial growth layer 18 remains without being silicided, or even part of the source extension layer 52 and the drain extension layer 62 is silicided to become Co silicide layers 51 and 63. There is a case. However, the portion where the silicon is not exposed (for example, the element isolation oxide film 11) is unreacted with the Co film, and the semiconductor device shown in FIG. 10 is formed by removing the portion.

  As described above, in the semiconductor device according to the present embodiment, all or most of the Co silicide layer 51 is formed on the semiconductor layer 3, so that the contact area between the Co silicide layer 51 and the source extension layer 52 is small. This increases the parasitic resistance against the on-current of the transistor. In the semiconductor device according to the present embodiment, since the P-type diffusion layer 55 is provided and the Co silicide layer 51 is in contact with the body region 4, the body potential can be fixed to the source potential and the body floating effect is suppressed. be able to. Here, the Co silicide layer 51 according to the present embodiment can be easily manufactured by siliciding silicon epitaxially grown on the source extension layer 52.

  Note that the asymmetric source-drain structure described in Embodiment 2 may be applied to the semiconductor device according to this embodiment. In this embodiment, the Co silicide layers 9, 51, 63 are formed. However, the present invention is not limited to this, and a layer silicided with a material other than Co, such as a Ni silicide layer, may be used. Further, in this embodiment, the drain diffusion layer 61 is formed after the epitaxial growth layer 18 is formed. However, the drain diffusion layer 61 may be formed before the epitaxial growth layer 18 is formed. Furthermore, in this embodiment, the silicon layer is formed by epitaxial growth on the semiconductor layer 3, but the present invention is not limited to this, and the silicon layer may be formed on the semiconductor layer 3 by other methods. .

(Embodiment 6)
In the present embodiment, a method for manufacturing a diffusion layer such as a P-type diffusion layer 55 that connects the Co silicide layer 51 and the body region 4 as described in the fifth embodiment will be described. In the following description, a method for manufacturing the P-type diffusion layer 55 will be described using the configuration of the general semiconductor device shown in FIG. In the semiconductor device shown in FIG. 13, unlike the semiconductor device shown in FIG. 10, a Co silicide layer 51 is formed in the semiconductor layer 3. In FIG. 13, the same components as those in FIG. 10 are denoted by the same reference numerals, and detailed description thereof is omitted.

  First, portions other than the P-type diffusion layer 55 shown in FIG. 13 are formed by the manufacturing method described in the above embodiment. Then, as shown in FIG. 14, an interlayer insulating film 20 is formed on the semiconductor layer 3. Thereafter, a contact hole 21 for providing a plug for connecting the source region 5 and a wiring formed on the interlayer insulating film 20 is formed in the interlayer insulating film 20 by using a photolithography technique. Next, using the interlayer insulating film 20 in which the contact hole 21 is formed as a mask, boron, which is a P-type impurity, is implanted into the semiconductor layer 3 to form a P-type diffusion layer 55. That is, in this embodiment, it is not necessary to provide a mask only for forming the P-type diffusion layer 55, and the number of processes can be reduced because the interlayer insulating film 20 in which the contact holes 21 are formed is used as a mask. .

As shown in FIG. 14, since boron ions are implanted using the interlayer insulating film 20 in which the contact hole 21 is formed as a mask, the formed P-type diffusion layer 55 is formed almost directly below the contact hole 21. . Note that boron, which is a P-type impurity, is implanted into the semiconductor layer 3 by an ion implantation method, and the impurity concentration of implanted boron ions is, for example, about 10 ¹⁴ ions / cm ² .

  Next, a plug 22 is formed in the contact hole 21 with a conductive material (for example, tungsten) by sputtering or the like. After forming the plug 22, a copper wiring 23 is formed on the interlayer insulating film 20. Thereby, the source region 5 is electrically connected to the copper wiring 23 via the plug 22. FIG. 15 is a cross-sectional view of a semiconductor device in which the plug 22 and the copper wiring 23 are formed.

  As described above, in the method of manufacturing a semiconductor device according to the present embodiment, the P-type diffusion layer 55 is formed using the interlayer insulating film 20 in which the contact holes 21 are formed. Can be reduced. In this embodiment, the contact hole is provided only on the source side, but may be formed simultaneously on the train side. When a hole is provided on the drain side, boron is also injected into the hole on the drain side, but since deep arsenic has already been injected into the drain side, it does not invert to P-type.

  Furthermore, although the N-type channel MOSFET has been described in the first to sixth embodiments, the present invention can be similarly applied to a P-type channel MOSFET. Further, although CoSi is used as the silicide, NiSi or TiSi may be used.

(Embodiment 7)
In the semiconductor device described in the above embodiment, the body potential is fixed to the source potential by connecting the body region 4 to the source region 5 in some form. Therefore, it is possible to apply a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having the structure of the semiconductor device described in the above embodiment to an inverter circuit portion or the like in which the source side is always fixed. The present invention cannot be applied to a pass transistor circuit portion in which the side and the drain side are inverted depending on the operating condition.

  Therefore, in this embodiment, for example, as shown in FIG. 16, the inverter logic circuit 31 and the input / output interface circuit 32 are always fixedly used on the source side, so that the first to first embodiments are used. 6. The structure of any one of the semiconductor devices described in FIG. 6 is adopted, and the source side and the drain side of the pass transistor circuit 33 are inverted depending on the operation state, so that the structure of a normal semiconductor device is adopted. Thereby, the structure of the semiconductor device according to the above embodiment can be applied to semiconductor circuits having various configurations, and the body floating effect can be appropriately suppressed.

  In FIG. 17, in the semiconductor circuit composed of the inverter logic circuit 31 and the input / output interface circuit 32, a pass transistor circuit 33 portion is formed in a part of the inverter logic circuit 31. Therefore, the structure of the normal semiconductor device is applied to the pass transistor circuit 33 portion, and the structure of the semiconductor device described in the above embodiment is applied to the other portions.

  As described above, in this embodiment, the structure of the semiconductor device described in any of the above embodiments can be applied to semiconductor circuits having various structures, and the body floating effect is suppressed in the portion. be able to.

(Embodiment 8)
In the above embodiment, the structure of the semiconductor device capable of fixing the body potential has been described. In the present embodiment, a structure in which a body potential is fixed by a conventionally known source tie structure is compared with the structure of the present invention.

  First, a source tie structure will be described as a conventional method for fixing a body potential in an SOI structure MOSFET. FIG. 18 shows a plan view of a MOSFET using a source tie structure. The MOSFET shown in FIG. 18 is N-type, and is provided with a spacer portion 82 on both sides of the gate electrode 81 and an N-type source portion 83 and an N-type drain portion 84 on both sides thereof. Further, in the MOSFET shown in FIG. 18, a P-type source tie region 85 is provided on the side where the N-type source portion 83 is formed so as to be in contact with the N-type source portion 83. In the plan view of the MOSFET shown in FIG. 18, the cobalt silicide layer formed on the N-type source portion 83, the N-type drain portion 84, etc. is removed.

  FIG. 19 is a cross-sectional view of the MOSFET of FIG. 18 cut along the AB plane. In the MOSFET shown in FIG. 19, a buried oxide film 92 is formed on a Si substrate 91, and a body portion comprising an N-type drain portion 84, a P-type source tie region 85, and a P-type thin film Si layer provided thereon. 93 is provided. In the MOSFET shown in FIG. 19, a gate electrode 81 is provided on a body portion 93 via a gate insulating film 94, and a spacer portion 82 and an N-type drain portion 84 provided on both side surfaces of the gate electrode 81. An N-type extension portion 95 is provided in contact with the side surface of each of them. Further, in the MOSFET shown in FIG. 19, a cobalt silicide layer 96 is provided on the N-type drain portion 84, the P-type source tie region 85 and the gate electrode 81.

  In the MOSFET shown in FIG. 19, the P-type source tie region 85 is provided in a part of the source region so as to be in contact with the body portion 93 on the side surface. As a result, the P-type body portion 93 and the source tie region 85 have the same potential. FIG. 20 is a cross-sectional view of the MOSFET of FIG. 18 cut along the CD plane.

  As shown in FIG. 20, a cobalt silicide layer 96 is usually formed on the N-type source portion 83 and the P-type source tie region 85 in order to reduce resistance. Therefore, in the source region (the region where the N-type source portion 83 and the P-type source tie region 85 are formed), the cobalt silicide formed over the P-type source tie region 85 and the N-type source portion 83. Due to the layer 96, the P-type source tie region 85 and the N-type source unit 83 have the same potential.

  Accordingly, in the source tie structure MOSFET shown in FIGS. 18 to 20, the body potential and the source portion potential can be set to the same potential.

  In this source tie structure, except for the P-type source tie region 85, the N-type source part 83 and the N-type drain part 84 may have the same impurity diffusion layer structure. It can be formed simultaneously. Therefore, when compared with the structure of the semiconductor device described in the above embodiment, the source tie structure has an advantage that the manufacturing process can be simplified.

  However, in the case of the source tie structure, since the P-type source tie region 85 is provided in the planar direction as shown in FIG. The width is reduced by the width of the P-type source tie region 85. On the contrary, in the structure of the semiconductor device shown in the first to fifth embodiments, there is an advantage that the body potential can be fixed without the need to provide the P-type source tie region 85 and narrowing the channel width. .

(Embodiment 9)
In this embodiment, the structure of the semiconductor device described in any of Embodiments 1 to 6 is applied to an SRAM (Static Random Access Memory) circuit.

  In an SRAM using an SOI structure semiconductor device, when the body potential is not fixed and is left floating, the threshold value Vth varies according to the change in the body potential due to the circuit operation. Therefore, an SRAM using a semiconductor device having an SOI structure has a problem that the operation of the SRAM becomes unstable when data is read or written.

  Therefore, in the SRAM according to this embodiment, the structure of the semiconductor device capable of fixing the body potential shown in Embodiments 1 to 6 to the source potential is applied to solve the above problem. Specifically, how the semiconductor device described in any of Embodiments 1 to 6 is applied will be described with reference to FIGS. FIG. 21 is a circuit diagram of one memory cell in the SRAM according to the present embodiment.

  21 includes an access transistor 101a connected between the bit line and the storage node 1, an access transistor 101b connected between the bit line and the storage node 2, a power supply, and a storage node 1. Load transistor 102a connected between the power supply and storage node 2, load transistor 102b connected between power supply and storage node 2, driver transistor 103a connected between GND and storage node 1, and between GND and storage node 2. And a driver transistor 103b connected to the. A word line is connected to the gate electrodes of the access transistors 101a and 101b.

  In the SRAM according to the present embodiment, the structure of the semiconductor device described in the first to sixth embodiments is applied to the load transistors 102a and 102b and the driver transistors 103a and 103b among the transistors illustrated in FIG. However, the access transistors 101a and 101b have their sources and drains interchanged depending on the operating state, so that the structure of the semiconductor device shown in the first to sixth embodiments cannot be applied and used in a body floating state. That is, in the SRAM according to the present embodiment, the structure of the semiconductor device shown in the first to sixth embodiments is applied to the load transistors 102a and 102b and the driver transistors 103a and 103b whose source side is determined in the operating state. To do.

  Therefore, in the SRAM according to this embodiment, the structure of the semiconductor device described in Embodiments 1 to 6 is applied to the load transistors 102a and 102b and the driver transistors 103a and 103b, and the access transistors 101a and 101b that are pass transistors are applied. Is not applied, the body potentials of the load transistors 102a and 102b and the driver transistors 103a and 103b are fixed, and there is an effect that the operation of the SRAM is stabilized at the time of data reading or writing.

(Embodiment 10)
In the ninth embodiment, the structure of the semiconductor device shown in the first to sixth embodiments is applied only to the load transistors 102a and 102b and the driver transistors 103a and 103b constituting the SRAM, and the access transistors 101a and 101b have a body floating structure. It was.

  However, even if only the access transistors 101a and 101b have a body floating structure, the threshold value Vth varies depending on the circuit operation, which causes a problem of narrowing the operation margin of the SRAM.

  Therefore, in the SRAM according to the present embodiment, the body potential fixing structure shown in the first to sixth embodiments is applied to the load transistors 102a and 102b and the driver transistors 103a and 103b, and another body is applied to the access transistors 101a and 101b. A potential-clamping structure is applied. FIG. 22 is a plan view of the SRAM according to the present embodiment. In the SRAM shown in FIG. 22, the body potential is fixed by using the structure shown in the first to sixth embodiments for the load transistors 102a and 102b and the driver transistors 103a and 103b and the partial trench isolation structure for the access transistors 101a and 101b. is doing. In the partial trench isolation structure shown in FIG. 22, access transistors 101a and 101b and body terminal 104 have the same potential. Further, in FIG. 22, in order to show a region where the isolation oxide film is shallow, a shallow isolation end is indicated by a broken line.

  Next, a partial trench isolation structure used for the access transistors 101a and 101b will be described. FIG. 23 shows a plan view of a specific partial trench isolation structure. FIG. 23 shows a gate electrode 111 constituting the access transistors 101a and 101b, and an N-type source region 112 and an N-type drain region 113 on both sides thereof. Further, FIG. 23 shows the body terminal 104 separated from the access transistors 101 a and 101 b by the isolation oxide film 114. In FIG. 23, since the partial trench isolation structure is employed, the shallower region of the isolation oxide film 114 is inside the shallow isolation end indicated by the broken line.

  24 is a cross-sectional view taken along the plane EF of FIG. As shown in FIG. 24, access transistors 101a and 101b according to the present embodiment have an SOI structure and are therefore formed on buried oxide film 117. The lower layer of the buried oxide film 117 is the Si substrate 116. In access transistors 101a and 101b shown in FIG. 24, P-type body portion 118 and body terminal 104 are separated by isolation oxide film 114. However, the access transistors 101a and 101b and the body terminal 104 are in a region inside the shallow isolation edge, and the isolation oxide film 114 in the region is shallow and the buried oxide film 117 is not formed. In the lower layer, the P-type body portion 118 and the body terminal 104 are electrically connected. Note that a gate insulating film 119 is formed on the P-type body portion 118, and a gate electrode 111 is formed on the gate insulating film 119.

  Therefore, the access transistors 101a and 101b according to the present embodiment can fix the body potential by adopting the partial trench isolation structure shown in FIGS. The body terminal 104 has a higher P-type impurity concentration than the P-type body portion 118. Thereby, in the SRAM according to the present embodiment, the threshold value Vth of the access transistors 101a and 101b is also stabilized without being affected by the circuit operation, and can be secured from the operation margin at the time of data reading or writing of the SRAM.

  A method of fixing the body potential by adopting a partial trench isolation structure for the load transistors 102a and 102b and the driver transistors 103a and 103b is also conceivable. However, when the partial trench isolation structure is used, the body potential is fixed via the thin semiconductor layer under the partial trench isolation film, so that a thin semiconductor layer is formed between the body terminal 104 and the body portion 118 as shown in FIG. There will be resistance. Therefore, the partial trench isolation structure has a problem that when the distance of the thin semiconductor layer portion is long, the resistance of the portion becomes large and the fixing ability of the body potential is lowered.

  Therefore, in the SRAM according to the present embodiment, only the access transistors 101a and 101b adopt the partial trench isolation structure, and the load transistors 102a and 102b and the driver transistors 103a and 103b are described in the first to sixth embodiments. By using the structure of the semiconductor device, the operation of the SRAM can be made more stable at the time of data reading or writing.

  1 silicon substrate, 2 buried oxide film, 3 semiconductor layer, 4 body region, 5 source region, 6 drain region, 7 gate oxide film, 8 gate polysilicon, 9, 51, 63 Co silicide layer, 10 sidewall oxide film, 11 Element isolation oxide film, 12 crystal defect region, 13 crystal defect formation region, 15, 16 photoresist, 18 epitaxial growth layer, 19 cap oxide film, 20 interlayer insulation film, 21 contact hole, 22 plug, 23 copper wiring, 31 inverter logic Circuit, 32 input / output interface circuit, 33 pass transistor circuit, 52 source extension layer, 53 source diffusion layer, 54, 55 P-type diffusion layer, 61 drain diffusion layer, 62 drain extension layer, 81, 111 gate electrode, 82 spacer portion , 83, 112 N-type source part, 84, 113 N-type drain part, 85 P-type source tie region, 91, 116 Si substrate, 92, 117 buried oxide film, 93, 118 body part, 94 gate insulating film, 95 N-type extension part, 96 Cobalt silicide layer, 101 access transistor, 102 load transistor, 103 driver transistor, 104 body terminal, 114 isolation oxide film, 119 gate insulating film.

Claims (4)

An SOI structure semiconductor device comprising a silicon substrate, a buried insulating layer formed on the silicon substrate, and a semiconductor layer formed on the buried insulating layer,
The semiconductor layer includes a body region of a first conductivity type, a source region of a second conductivity type, and a drain region of a second conductivity type, and gate oxidation is performed on the body region between the source region and the drain region. A gate electrode is formed through the film,
The source region includes a second conductivity type extension layer and a silicide layer formed on the semiconductor layer so as to be in contact with the extension layer, and the silicide layer is formed on the semiconductor layer. The semiconductor device is connected to the body region through a diffusion layer. An SOI structure semiconductor device comprising a silicon substrate, a buried insulating layer formed on the silicon substrate, and a semiconductor layer formed on the buried insulating layer,
The semiconductor layer includes a body region of a first conductivity type, a source region of a second conductivity type, and a drain region of a second conductivity type, and gate oxidation is performed on the body region between the source region and the drain region. A gate electrode is formed through the film,
The source region includes a second conductivity type extension layer and a silicide layer formed by siliciding silicon grown selectively on the extension layer, and the silicide layer is formed in the semiconductor layer. A semiconductor device connected to the body region through a diffusion layer of a mold. The semiconductor device according to claim 1 or 2, wherein
The semiconductor device, wherein the extension layer has an effective concentration of second conductivity type impurities higher than that of the extension layer formed in the drain region. A method of manufacturing the semiconductor device according to claim 1 or 2,
(C) selectively epitaxially growing a second conductivity type silicon on the extension layer;
(D) siliciding the silicon formed in the step (c) to form the silicide layer, and a method for manufacturing a semiconductor device.

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