JP2004273589A - Semiconductor device and its fabricating process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which increase in gate capacity can be suppressed by fixing the body potential thereby suppressing substrate suspension effect, and to provide its fabricating process. <P>SOLUTION: The semiconductor device comprises an SOI substrate having a supporting substrate 11, an insulating film 12 and a single crystal Si layer 13, a gate insulating film 19 formed on the single crystal Si layer, a gate electrode 15 formed on the gate insulating film, a diffusion layer 17 in a source region formed in the single crystal Si layer beneath one side face of the gate electrode, a diffusion layer 18 in a drain region formed in the single crystal Si layer beneath the other side face of the gate electrode, a body region formed in the single crystal Si layer beneath the gate electrode, a body contact region 22 formed in the single crystal Si layer, and a Ge region (impurity region) 23 formed in the single crystal Si layer to connect the body region and the body contact region. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of suppressing an increase in gate capacitance while fixing a body potential and suppressing a substrate floating effect, and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, SOI (Silicon On Insulator) substrates have been applied to MOS transistors and other semiconductor elements because of their excellent operation speed and degree of integration of semiconductor elements. Among such semiconductor elements, a so-called partially depleted element is formed in an element active region in which a semiconductor layer of an SOI substrate is processed into an island shape and is electrically isolated from the surroundings. It has various advantages such as junction leakage and small capacitance. However, on the other hand, since the element active region is in an electrically floating state, the potential change affects the operation of the semiconductor element. To cope with this problem, a conductive region (body contact region) is provided near the device active region of the semiconductor layer, and an electrical contact is made to the device active region which is electrically cut off through this region to stabilize the device operation. Need to be
[0003]
FIG. 5 is a plan view showing a conventional semiconductor device (see JP-A-7-302908). This semiconductor device comprises a MOSFET having a body contact formed on an SOI substrate.
5, S is an n ⁺ source region, D is an n ⁺ drain region, G is a gate electrode made of n ⁺ polycrystalline silicon, B is a p ⁺ body contact region, W is a gate width, and L is a gate length. Each is shown.
[0004]
An interlayer insulating film (not shown) is formed on the entire surface including the gate electrode G, and first to third contact holes 101 to 103 for connecting to an upper layer wiring are formed in the interlayer insulating film. ing. The first contact hole 101 is located on the p ⁺ body contact region B, the second contact hole 102 is located on the n ⁺ drain region D, and the third contact hole 103 is located on the n ⁺ source region S are doing.
[0005]
In this semiconductor device, since the p ⁺ body contact region B is connected to the p-type channel region (not shown) below the gate electrode G, the positive electrode generated near the channel side pn junction of the n ⁺ drain region D is formed. The holes are drawn into the p ⁺ body contact region B.
[0006]
FIG. 6 is a sectional view showing another conventional semiconductor device.
This semiconductor device has an SOI substrate 107. The SOI substrate 107 includes a support substrate 104 made of single crystal silicon, a buried oxide film (BOX layer) 105 formed on the support substrate 104, and a buried oxide film. And a single-crystal Si layer 106 formed on the film 105.
[0007]
A partial trench is formed in the single-crystal Si layer 106, and the bottom of the partial trench is located above the bottom of the single-crystal Si layer. A silicon oxide film is buried in the partial trench, and an element isolation oxide film 108 made of a silicon oxide film is formed in an element isolation region on the BOX layer 105. In the single-crystal Si layer 106, a P- type impurity diffusion layer (P well) 109 is formed.
[0008]
A gate oxide film 110 is formed on the surface of single crystal Si layer 106, and a gate electrode 111 is formed on gate oxide film 110. An N-type diffusion layer (not shown) in the source / drain region and a low-concentration N-type impurity diffusion layer (not shown) are formed in the single-crystal Si layer 106. A sidewall 112 is formed on a side wall of the gate electrode 111.
[0009]
Further, a body contact region 113 made of a P- type impurity diffusion layer is formed in the single crystal Si layer 106. The body contact region 113 is formed in a channel region under the gate electrode under a P well under the element isolation oxide film 108. 109 are connected.
[0010]
[Patent Document 1]
JP-A-7-302908 (page 2, FIG. 7)
[0011]
[Problems to be solved by the invention]
As described above, as a method of fixing the body potential, the body is pulled out by a T-gate or Source-Tie structure shown in FIG. General.
In other words, in the above-described conventional and other conventional semiconductor devices, a body contact region for fixing the body potential is formed, and a predetermined voltage is applied to the body contact region to fix the body potential and reduce the substrate floating effect. Can be suppressed.
[0012]
However, in the above-described conventional semiconductor device, the use of T-gate greatly increases the gate capacitance and the area of the transistor. When the gate capacitance increases, the operation speed of the transistor decreases, and power consumption increases.
Further, the other conventional semiconductor device has an element isolation structure using a partial trench, so that latch-up may occur. In order to prevent latch-up, a very complicated element isolation structure using a hybrid partial trench may be considered. However, it is not easy to fabricate this in an SOI substrate.
[0013]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can suppress an increase in gate capacitance while fixing a body potential and suppressing a substrate floating effect. Is to do.
[0014]
[Means for Solving the Problems]
In order to solve the above problem, a semiconductor device according to the present invention includes an SOI substrate including a supporting substrate, an insulating film formed over the supporting substrate, and a single crystal Si layer formed over the insulating film. ,
A gate insulating film formed on the single-crystal Si layer;
A gate electrode formed on the gate insulating film;
A diffusion layer of a source region formed in a single-crystal Si layer below one side surface of the gate electrode;
A diffusion layer of a drain region formed in a single-crystal Si layer below the other side surface of the gate electrode;
A body region formed in the single-crystal Si layer below the gate electrode;
A body contact region formed in the single-crystal Si layer;
An impurity region formed in the single-crystal Si layer and connected to connect the body region and the body contact region;
Is provided.
[0015]
According to the semiconductor device, the body contact region for fixing the body potential is formed in the single crystal Si layer, and the body contact region is electrically connected to the body region by the impurity region. Therefore, the body potential can be fixed and the substrate floating effect can be suppressed. In addition, since the gate electrode can have a straight shape, an increase in gate capacitance can be suppressed.
[0016]
Further, in the semiconductor device according to the present invention, it is preferable that the body contact region is formed adjacent to a diffusion layer of the source region.
Further, in the semiconductor device according to the present invention, it is preferable that the impurity region is formed near an interface between the insulating film and the single crystal Si layer.
[0017]
Further, in the semiconductor device according to the present invention, Ge can be used as an impurity in the impurity region.
The semiconductor device according to the present invention may further include a metal silicide film formed on each of the gate electrode, the diffusion layer in the source region, the diffusion layer in the drain region, and the body contact region.
[0018]
A method for manufacturing a semiconductor device according to the present invention includes a step of preparing an SOI substrate having a supporting substrate, an insulating film formed on the supporting substrate, and a single crystal Si layer formed on the insulating film. ,
Forming a gate insulating film on the single crystal Si layer;
Forming a gate electrode on the gate insulating film;
Forming a source region and a drain region in the single crystal Si layer by introducing the first conductivity type impurity into the single crystal Si layer;
Forming a body contact region in the single crystal Si layer by introducing the second conductivity type impurity into the single crystal Si layer;
Forming an impurity region in the single crystal Si layer so as to connect the body region below the gate electrode and the body contact region by introducing an impurity into the single crystal Si layer;
It is characterized by having.
[0019]
A method for manufacturing a semiconductor device according to the present invention includes a step of preparing an SOI substrate having a supporting substrate, an insulating film formed on the supporting substrate, and a single crystal Si layer formed on the insulating film. ,
Forming an impurity region in the single-crystal Si layer by introducing an impurity into the single-crystal Si layer;
Forming a body contact region in the single crystal Si layer by introducing a first conductivity type impurity into the single crystal Si layer;
Forming a gate insulating film on the single crystal Si layer;
Forming a gate electrode on the gate insulating film;
Forming a source region and a drain region in the single crystal Si layer by introducing a second conductivity type impurity into the single crystal Si layer;
With
The impurity region is formed to connect and electrically connect a body region below the gate electrode and the body contact region.
[0020]
In the method of manufacturing a semiconductor device, the order of the steps can be changed as follows.
A method for manufacturing a semiconductor device according to the present invention includes a step of preparing an SOI substrate having a supporting substrate, an insulating film formed on the supporting substrate, and a single crystal Si layer formed on the insulating film. ,
Forming an impurity region in the single-crystal Si layer by introducing an impurity into the single-crystal Si layer;
Forming a gate insulating film on the single crystal Si layer;
Forming a gate electrode on the gate insulating film;
Forming a source region and a drain region in the single crystal Si layer by introducing a second conductivity type impurity into the single crystal Si layer;
Forming a body contact region in the single crystal Si layer by introducing a first conductivity type impurity into the single crystal Si layer;
With
The impurity region is formed to connect and electrically connect a body region below the gate electrode and the body contact region.
[0021]
A method for manufacturing a semiconductor device according to the present invention includes a step of preparing an SOI substrate having a supporting substrate, an insulating film formed on the supporting substrate, and a single crystal Si layer formed on the insulating film. ,
Forming a body contact region in the single crystal Si layer by introducing a first conductivity type impurity into the single crystal Si layer;
Forming a gate insulating film on the single crystal Si layer;
Forming a gate electrode on the gate insulating film;
Forming a diffusion layer of a source region and a diffusion layer of a drain region in the single crystal Si layer by introducing a second conductivity type impurity into the single crystal Si layer;
Forming an impurity region in the single crystal Si layer so as to connect the body region and the body contact region below the gate electrode by introducing an impurity into the single crystal Si layer;
Is provided.
[0022]
A method for manufacturing a semiconductor device according to the present invention includes a step of preparing an SOI substrate having a supporting substrate, an insulating film formed on the supporting substrate, and a single crystal Si layer formed on the insulating film. ,
Forming a body contact region in the single crystal Si layer by introducing a first conductivity type impurity into the single crystal Si layer;
Forming an impurity region in the single-crystal Si layer by introducing an impurity into the single-crystal Si layer;
Forming a gate insulating film on the single crystal Si layer;
Forming a gate electrode on the gate insulating film;
Forming a source region and a drain region in the single crystal Si layer by introducing a second conductivity type impurity into the single crystal Si layer;
With
The impurity region is formed to connect and electrically connect a body region below the gate electrode and the body contact region.
[0023]
A method for manufacturing a semiconductor device according to the present invention includes a step of preparing an SOI substrate having a supporting substrate, an insulating film formed on the supporting substrate, and a single crystal Si layer formed on the insulating film. ,
Forming a gate insulating film on the single crystal Si layer;
Forming a gate electrode on the gate insulating film;
Forming a source region and a drain region in the single crystal Si layer by introducing a second conductivity type impurity into the single crystal Si layer;
Forming an impurity region in the single-crystal Si layer by introducing an impurity into the single-crystal Si layer;
Forming a body contact region in the single crystal Si layer by introducing a first conductivity type impurity into the single crystal Si layer;
With
The impurity region is formed to connect and electrically connect a body region below the gate electrode and the body contact region.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a plan view showing a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line 1B-1B shown in FIG. This semiconductor device will be described using an n-channel MOSFET as an example.
This semiconductor device has an SOI substrate. The SOI substrate 14 includes a support substrate 11 made of single crystal silicon, a buried oxide film (BOX layer) 12 formed on the support substrate 11, and a single crystal Si layer 13 formed on the buried oxide film 12. And is composed of
[0025]
An element isolation oxide film 16 is formed on the single crystal Si layer 13. Further, a gate oxide film 19 is formed on the surface of the single crystal Si layer 13, and a gate electrode 15 is formed on the gate oxide film 19. Sidewalls 20 are formed on the side walls of the gate electrode 15, and a low-concentration N-type impurity diffusion layer 21 is formed in the single-crystal Si layer 13 below the sidewalls, as shown in FIG. ing. The N ⁺ -type diffusion layer 17 in the source region and the N ⁺ -type diffusion layer 18 in the drain region are formed adjacent to the N-type low-concentration diffusion layer 21 in the single-crystal Si layer 13.
[0026]
In the single-crystal Si layer 13, a body contact region 22 made of a P ⁺ -type impurity diffusion layer is formed so as to be adjacent to the source region diffusion layer 17. The single-crystal Si layer 13 below the gate electrode 15 is a P- type body region. The single-crystal Si layer 13 has a diffusion layer 17 near the interface with the BOX layer 12 and extending from the body region to the source region. Ge region (impurity region) 23 connected to body contact region 22 is formed. That is, the body region is connected to and electrically connected to the body contact region 22 by the Ge region 23.
[0027]
Further, a metal silicide film 24 is formed on each of the gate electrode 15, the diffusion layers 17 and 18 of the source / drain regions, and the body contact region 22. In this embodiment, the Ge region 23 is used. However, the present invention is not limited to this, and a P-type impurity diffusion layer can be used.
[0028]
An interlayer insulating film 25 is formed on the entire surface including the gate electrode. In the interlayer insulating film 25, a contact hole 25a located on the body contact region 22 is formed. A wiring 26 made of a conductive layer such as an Al alloy layer is formed in the contact hole and on the interlayer insulating film 25. The wiring 26 is electrically connected to the diffusion layer 17 in the source region and the body contact region 22 via the metal silicide film 24. By applying a predetermined voltage from the wiring 26 to the body contact region 22, the body potential is fixed and the substrate floating effect is suppressed. Thus, the operation of the transistor can be stabilized.
[0029]
According to the semiconductor device according to the above embodiment, the body contact region 22 for fixing the body potential is formed in the single crystal Si layer 13, and the body contact region 22 is electrically connected to the body region by the Ge region 23. ing. Therefore, the body potential of the transistor formed on the SOI substrate can be fixed at a controlled resistance value. In addition, it is not necessary to form a large area called a hammer head at one end of the gate electrode as in the related art, and a straight gate electrode can be obtained. Therefore, the gate capacitance can be reduced by the area of the hammer head as compared with the related art, in other words, the increase in gate capacitance can be suppressed. Therefore, the operation speed of the transistor can be increased as compared with the related art without increasing the area of the semiconductor device, and an increase in power consumption can be suppressed.
[0030]
In the present embodiment, the Ge region 23 is formed to connect the body region and the body contact region 22 as described above. Since the Ge region 23 is effective for countermeasures against α-rays, the α-ray tolerance can be increased. That is, since the Ge region 23 also functions as an α-ray charge recombination center, it is possible to manufacture a device that is resistant to soft errors.
[0031]
Further, in the present embodiment, since a partial trench is not used unlike other conventional semiconductor devices, complete isolation of elements can be performed. Therefore, a latch-up-free design rule can be applied, and a reduction in chip area can be expected.
[0032]
2 to 4 are cross-sectional views showing a method of manufacturing the semiconductor device shown in FIG. 1 and sequentially showing manufacturing steps.
First, as shown in FIG. 2, an SOI substrate 14 is prepared. The SOI substrate 14 includes a support substrate 11 made of single crystal silicon, a buried oxide film (BOX layer) 12 formed on the support substrate 11, and a single crystal Si layer 13 formed on the buried oxide film 12. , Is composed of. The SOI substrate 14 can be manufactured by various manufacturing methods, and for example, can be manufactured by a bonding method, SIMOX (separation by implanted oxygen), or the like.
[0033]
Next, a silicon nitride film (not shown) is formed on the single crystal Si layer 13 by a CVD (chemical vapor deposition) method. Next, a mask pattern made of the silicon nitride film is formed on the single crystal Si layer 13 by patterning the silicon nitride film. Next, the trenches 13a and 13b are formed in the single-crystal Si layer 13 by selectively etching the single-crystal Si layer 13 using this mask pattern as a mask.
[0034]
Next, an oxide film is deposited in the trench and on the mask pattern by a CVD method. Next, the oxide film and the mask pattern are polished by CMP. As a result, an oxide film is buried in the trench, and an element isolation oxide film 16 made of an oxide film is formed in an element isolation region on the BOX layer 12.
[0035]
Next, a P-type impurity is ion-implanted into the single crystal Si layer 13. Next, a gate oxide film (gate insulating film) 19 is formed on the surface of the single crystal Si layer 13 by a thermal oxidation method. Next, a polysilicon film is deposited on the entire surface including the gate oxide film 19 by the CVD method, and the polysilicon film is patterned to form a straight gate electrode 15 on the gate oxide film 19. . Next, a photoresist film (not shown) is applied on the entire surface including the gate electrode, and the photoresist film is exposed and developed to form a resist pattern covering the body contact region. Next, low-concentration N-type impurity ions are implanted using the resist pattern and the gate electrode 15 as a mask. Next, the resist pattern is stripped. Next, a silicon oxide film is deposited on the entire surface including the gate electrode 15 by the CVD method, and the entire surface of the silicon oxide film is etched, so that a sidewall 20 made of the silicon oxide film is formed on the side wall of the gate electrode 15. You.
[0036]
Next, a photoresist film (not shown) is applied on the entire surface including the gate electrode, and the photoresist film is exposed and developed to form a resist pattern covering the body contact region. Next, N ⁺ -type impurity ions 27 are implanted into the source / drain regions using the resist pattern, the sidewalls 20 and the gate electrode 15 as a mask. Next, the resist pattern is stripped.
[0037]
Next, a photoresist film (not shown) is applied on the entire surface including the gate electrode, and the photoresist film is exposed and developed to form a resist pattern having a body contact region opened. Next, P ⁺ -type impurity ions are implanted into the body contact region using the resist pattern as a mask. Next, the resist pattern is stripped.
[0038]
Thereafter, as shown in FIG. 3, a photoresist film is applied on the entire surface including the gate electrode, and the photoresist film is exposed and developed to form a resist pattern 28 covering a part of the gate electrode 15 and the drain region. Is formed. Next, for example, Ge ions 29 are densely implanted as P-type impurity ions using the resist pattern 28, the sidewalls 20 and the gate electrode 15 as a mask. At this time, the ion implantation conditions are controlled so that Ge ions are implanted in the single crystal Si layer 13 on the source region side and near the interface between the single crystal Si layer 13 and the BOX layer 12. Next, the resist pattern 28 is peeled off.
[0039]
In this embodiment, the order is such that impurity ions are implanted into the source / drain regions, impurity ions are implanted into the body contact region, and Ge ions 29 are implanted. The present invention is not limited thereto, and may be changed as appropriate. For example, the order may be such that Ge ions 29 are implanted, impurities are implanted into the body contact region, and impurity ions are implanted into the source / drain regions. It is possible. Further, when the Ge ions 29 are implanted in order to produce a recombination center of charges generated in the body region as a countermeasure against α rays, Ge ions are also implanted into other body regions (body regions not shown in FIG. 3). May be injected.
[0040]
Thereafter, as shown in FIG. 4, the SOI substrate 14 is annealed. As a result, the low-concentration N-type impurity diffusion layer 21, the N ⁺ -type diffusion layers 17 and 18 in the source / drain region, the P ⁺ -type diffusion layer in the body contact region 22, and the Ge region (impurity region) are formed in the single-crystal Si layer 13. ) 23 are formed. The body contact region 22 is arranged adjacent to the source region diffusion layer 17, and the Ge region 23 is arranged to connect the body region below the gate electrode and the body contact region 22.
[0041]
Next, a metal film (not shown) of Ti, Co, Ni or the like is deposited on the entire surface including the gate electrode 15 by sputtering. Next, by subjecting the SOI substrate 14 to heat treatment, the polysilicon of the gate electrode 15 and the single-crystal Si layer 13 react with the metal film. Thus, as shown in FIG. 1B, a metal silicide film 24 is formed on the gate electrode 15, the diffusion layers 17 and 18 of the source / drain regions, and the body contact region 22 in a self-aligned manner. Next, the remaining metal film is peeled off.
[0042]
Thereafter, an interlayer insulating film 25 made of a silicon oxide film or the like is formed on the entire surface including the gate electrode 15 by a CVD method. Next, a photoresist film (not shown) is applied on the interlayer insulating film 25, and the photoresist film is exposed and developed to form a resist pattern on the interlayer insulating film. Next, by using the resist pattern as a mask, the interlayer insulating film 25 is etched to form a contact hole 25a in the interlayer insulating film 25. This contact hole 25a is located on body contact region 22 or the source region.
[0043]
Next, a conductive layer is formed in the contact hole 25a and on the interlayer insulating film 25, and by patterning the conductive layer, a wiring 26 is formed on the interlayer insulating film 25. The wiring 26 is electrically connected to the body contact region 22 and the diffusion layer 17 in the source region via the metal silicide 24. Note that various conductive layers can be used for a conductive layer included in a wiring, and a single-layer structure or a stacked structure may be used. For example, an Al alloy layer, a W layer, a Ti layer, a TiN layer, or the like can be used. . By applying a predetermined voltage from the wiring 26 to the body contact region 22, the body potential can be fixed and the substrate floating effect can be suppressed.
[0044]
It should be noted that the present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the gist of the present invention.
[Brief description of the drawings]
FIG. 1 illustrates a semiconductor device according to an embodiment.
FIG. 2 is a sectional view showing the method of manufacturing the semiconductor device shown in FIG. 1;
FIG. 3 is a sectional view showing the method of manufacturing the semiconductor device shown in FIG. 1;
FIG. 4 is a sectional view showing the method of manufacturing the semiconductor device shown in FIG. 1;
FIG. 5 is a plan view showing a conventional semiconductor device.
FIG. 6 is a sectional view showing another conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Support substrate, 12 ... Embedded oxide film (BOX layer), 13 ... Single crystal Si layer, 14 ... SOI substrate, 15 ... Gate electrode, 16 ... Element isolation oxide film, 17 ... Diffusion layer of source region, 18 ... Drain Region diffusion layer, 19 gate oxide film, 20 sidewall, 21 low concentration impurity diffusion layer, 22 body contact region, 23 Ge region (impurity region), 24 metal silicide film, 25 interlayer insulating film , 25a: contact hole, 26: wiring, 27: N ⁺ type impurity ion, 28: resist pattern, 29: Ge ion

Claims (7)

An SOI substrate having a supporting substrate, an insulating film formed on the supporting substrate, and a single-crystal Si layer formed on the insulating film;
A gate insulating film formed on the single-crystal Si layer;
A gate electrode formed on the gate insulating film;
A diffusion layer of a source region formed in a single-crystal Si layer below one side surface of the gate electrode;
A diffusion layer of a drain region formed in a single-crystal Si layer below the other side surface of the gate electrode;
A body region formed in the single-crystal Si layer below the gate electrode;
A body contact region formed in the single-crystal Si layer;
An impurity region formed in the single-crystal Si layer and connected to connect the body region and the body contact region;
A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein said body contact region is formed adjacent to a diffusion layer of said source region. The semiconductor device according to claim 1, wherein the impurity region is formed near an interface between the insulating film and the single-crystal Si layer. The semiconductor device according to claim 1, wherein Ge is used as an impurity in the impurity region. 5. The device according to claim 1, further comprising a metal silicide film formed on each of the gate electrode, the source region diffusion layer, the drain region diffusion layer, and the body contact region. 6. Semiconductor device. A step of preparing an SOI substrate having a supporting substrate, an insulating film formed over the supporting substrate, and a single-crystal Si layer formed over the insulating film;
Forming a gate insulating film on the single crystal Si layer;
Forming a gate electrode on the gate insulating film;
Forming a source region and a drain region in the single crystal Si layer by introducing the first conductivity type impurity into the single crystal Si layer;
Forming a body contact region in the single crystal Si layer by introducing the second conductivity type impurity into the single crystal Si layer;
Forming an impurity region in the single crystal Si layer so as to connect the body region below the gate electrode and the body contact region by introducing an impurity into the single crystal Si layer;
A method for manufacturing a semiconductor device, comprising: A step of preparing an SOI substrate having a supporting substrate, an insulating film formed over the supporting substrate, and a single-crystal Si layer formed over the insulating film;
Forming an impurity region in the single-crystal Si layer by introducing an impurity into the single-crystal Si layer;
Forming a body contact region in the single crystal Si layer by introducing a first conductivity type impurity into the single crystal Si layer;
Forming a gate insulating film on the single crystal Si layer;
Forming a gate electrode on the gate insulating film;
Forming a source region and a drain region in the single crystal Si layer by introducing a second conductivity type impurity into the single crystal Si layer;
With
The method of manufacturing a semiconductor device, wherein the impurity region is formed to connect and electrically connect a body region below the gate electrode and the body contact region.

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