JP2000269503A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technique capable of realizing micronization of a partial depletion type MIS FET which has Schottky junction. SOLUTION: A resist pattern 12 is formed on an element isolating region 10 surrounding a source, without being limited by the alignment margin to the element isolating region 10. After that, a third n+-type semiconductor region 6c, whose junction is shallower than the thickness of a silicide layer, is formed in a part of an n+-type semiconductor region constituting a source, by slant ion implantation using a gate electrode 8 and the shadowing of the resist pattern 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly, to an SOI (Silicon) device.
On Insulator) Partially depleted MISF formed on substrate
ET (Metal Insulator Semiconductor Field Effect T
ransistor).

[0002]

2. Description of the Related Art In a partially depleted MISFET, Ids
There is a problem that a kink occurs in the (drain current) -Vg (gate voltage) characteristic, and the threshold voltage decreases. This occurs because holes and electron pairs are generated by impact ionization in the channel region at the drain end, and the generated holes are accumulated in the substrate. So, for example, IED (International Electron Device Me
etings. A Compact Schottky Body Contact Technology
For SOI Transistors PP.419-422, 1997), a method has been proposed in which a Schottky junction is formed on the source side and the same voltage as the source is applied to the substrate to suppress the floating phenomenon of the substrate. ing.

[0003]

However, when a semiconductor region constituting a source is formed, a region where a Schottky junction is to be formed is covered with a photoresist pattern. Although it is introduced into the substrate, it is necessary to provide a sufficient margin for the alignment between the mask and the element isolation region.
It was considered that miniaturization of the ISFET was limited.

An object of the present invention is to provide a technique capable of realizing miniaturization of a partially depleted MISFET having a Schottky junction.

[0005] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) In the semiconductor integrated circuit device of the present invention, the SOI in which the thin silicon layer is provided on the supporting substrate via the buried insulating film is provided.
Partially depleted MI having a source formed by a plurality of semiconductor regions having relatively different impurity concentrations on an I substrate
The semiconductor device has an SFET, a silicide layer is formed on the surface of the active region in which the plurality of semiconductor regions are formed, and the junction depth of some of the semiconductor regions constituting the plurality of semiconductor regions is
It is shallower than the silicide layer and has a Schottky junction formed.

(2) In the semiconductor integrated circuit device according to the present invention, in the partially depleted MISFET of the above (1), a part of the plurality of semiconductor regions constituting the plurality of semiconductor regions is formed by the side wall of the gate electrode and the element isolation region. This is a semiconductor region formed in the active region near the intersection.

(3) In the semiconductor integrated circuit device of the present invention, in the partially depleted MISFET of (1), the silicide layer is a titanium silicide film, a cobalt silicide film or a nickel silicide film.

(4) In the semiconductor integrated circuit device according to the present invention, in the partially depleted MISFET of (1), a part of the semiconductor regions constituting the plurality of semiconductor regions is replaced with an impurity constituting the part of the semiconductor regions. And impurities of a different conductivity type are introduced.

(5) A method of manufacturing a semiconductor integrated circuit device according to the present invention is characterized in that a partially depleted MISFET having a Schottky junction is provided on an SOI substrate having a thin silicon layer provided on a supporting substrate via a buried insulating film. Is formed, the shortest distance from the intersection of the side wall of the gate electrode and the element isolation region is the thickness of the mask pattern × tan θ (θ = 15 to 4
5 °), forming a mask pattern on a part of the element isolation region surrounding the source, and forming the mask pattern at 45 ° with respect to the normal direction of the gate electrode and with respect to the normal direction of the support substrate. a step of ion-implanting an impurity of the same conductivity type as the channel into the active region at an angle of θ; and a step of forming a silicide layer on the surface of the active region.

(6) A method of manufacturing a semiconductor integrated circuit device according to the present invention is characterized in that a partially depleted MISFET having a Schottky junction is formed on an SOI substrate having a thin silicon layer provided on a supporting substrate via a buried insulating film. Is formed, the shortest distance from the intersection of the side wall of the gate electrode and the element isolation region is the thickness of the mask pattern × tan θ (θ = 15 to 4
5 [deg.]), Forming a mask pattern on a part of the element isolation region surrounding the source so as to fall within 45 [deg.] With respect to the normal direction of the gate electrode, ion implantation of an impurity of the same conductivity type as the channel into the active region at an angle of θ, ion implantation of an impurity of a conductivity type different from the channel into the active region, and forming a silicide layer on the surface of the active region And

(7) A method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein the partially depleted MISF according to (5) or (6) above is used.
In the ET manufacturing method, the mask pattern is formed of a resist film or a conductive film of the same layer as the conductive film forming the gate electrode.

(8) A method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein the partially depleted MISF according to (5) or (6) is used.
In the ET manufacturing method, ion implantation is performed from four directions having an angle of 45 degrees with respect to the normal direction of the gate electrode.

According to the above-mentioned means, the oblique ion implantation utilizing shadowing between the mask pattern formed on the element isolation region and the gate electrode is performed without being limited by the margin for alignment with the element isolation region. A plurality of semiconductor regions constituting the source are formed, and a semiconductor region having a junction shallower than the thickness of the silicide layer is formed in a part thereof, so that a Schottky junction can be formed.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIG. 1 is a plan view of a principal part of a semiconductor substrate showing a partially depleted MISFET according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line II-II of FIG. FIG. 3 is a cross-sectional view of a main part of the semiconductor substrate taken along line III-III in FIG. 1. The figure shows an n-channel MISFET.

The n-channel MISFET has a thickness of about 0.2 to 2 provided on a supporting substrate 1 with a buried oxide film 2 interposed therebetween.
It is formed on a p-type well 4 formed on a thin silicon layer 3 of about 0.25 μm.
A pair of n ⁻ type semiconductor regions 5 and a pair of n ⁺ type semiconductor regions 6 constitute a source and a drain. The depth of the n ⁻ type semiconductor region 5 from the surface of the thin film silicon layer 3 is about 0.05 μm.

[0019] The n ⁺ -type semiconductor region 6 constituting the drain, the first 1n ⁺ -type semiconductor regions 6a (indicated by hatching in hanging in FIG relatively dark mesh), about the first 1n ⁺ -type semiconductor regions 6a 2n having an impurity concentration of about 1/2
^{And a +} -type semiconductor region 6b (shown by relatively thin hatching in FIG. 1). Further, the n ⁺ -type semiconductor region 6 constituting the source, the 2n ⁺ -type semiconductor regions 6b having a first 1n ⁺ -type semiconductor regions 6a, the impurity concentration of about half of the first 1n ⁺ -type semiconductor regions 6a And a third n ⁺ -type semiconductor region 6c having an impurity concentration of about １ ／ of that of the first n ⁺ -type semiconductor region 6a. The depth of the first n ⁺ -type semiconductor region 6a from the surface of the thin film silicon layer 3 is about 0.25.
μm and the third n ⁺ formed only on the source.
The depth of the type semiconductor region 6c from the surface of the thin-film silicon layer 3 is about 0.06 μm.

Although not shown, a threshold voltage control layer is formed on the surface of the p-type well 4 between the pair of n ⁻ -type semiconductor regions 5. A gate insulating film 7 is formed of a silicon oxide film on the threshold voltage control layer, and a gate electrode 8 is formed on the gate insulating film 7 of a polycrystalline silicon film doped with an n-type impurity.

Further, a silicide layer 9 is formed on the surface of the gate electrode 8 and the surface of the pair of n ⁺ -type semiconductor regions 6 constituting the source and the drain. The silicide layer 9 is made of, for example, a titanium silicide film (TiSi ₂ ), a cobalt silicide film (CoSi ₂ ), or a nickel silicide film (NiSi), and has a thickness of about 0.07 μm.

Here, the 3n ⁺ th part of the source
Silicide layer 9 formed on the surface of type semiconductor region 6c
Is formed thicker than the junction depth of the third n ⁺ -type semiconductor region 6c to form a Schottky junction.

Next, the partially depleted MI according to the present embodiment is described.
The method of manufacturing the SFET will be described with reference to FIGS.

First, as shown in FIG. 4, a groove-shaped silicon oxide film is formed on a thin silicon layer 3 having a thickness of about 0.25 μm provided through a buried oxide film 2 on a support substrate 1. An element isolation region 10 is formed. Then
After forming a p-type well 4 in the thin-film silicon layer 3, a p-type impurity, for example, boron (B) is introduced into the channel region,
Although not shown, a threshold voltage control layer is formed.

Next, a gate insulating film 7 made of a silicon oxide film is formed on the surface of the thin silicon layer 3 by about 6.5 n.
Then, a polycrystalline silicon film (not shown) to which an n-type impurity, for example, phosphorus (P) is added is deposited on the upper layer of the gate insulating film 7, and then the polycrystalline silicon film is formed using the resist pattern as a mask. The gate electrode 8 is formed by etching the silicon film.

Next, as shown in FIG. 5, n-type impurities into the p-type well 4 of the gate electrode 8 as a mask to introduce for example arsenic (As), a low concentration constituting a source, a drain n ^- -type semiconductor Region 5 is formed. Then, a chemical vapor deposition (Chemical Vapor Depositio) is formed on the upper layer of the gate electrode 8.
n: silicon oxide film deposited by CVD) method (not shown)
Is etched by RIE (Reactive Ion Etching), and sidewall spacers 11 are formed on the side walls of the gate electrode 8.
To form

Next, as shown in FIG. 6, on the device isolation region 10 surrounding the source, the shortest distance d from the intersection of the side wall of the gate electrode 8 and the device isolation region 10 is within R × tan θ. A rectangular resist pattern 12 is formed at least at one position. Here, R is a resist pattern 1
And θ is an angle with respect to the normal direction of the support substrate 1 and is in a range of 15 to 45 degrees.

Next, an n-type impurity, for example, P or As is added to the p-type well 4 by oblique ion implantation using shadowing of the gate electrode 8 and the resist pattern 12.
To form a high-concentration n ⁺ -type semiconductor region 6 constituting a source and a drain. That is, n-type impurities are implanted into the p-type well 4 from four directions at an angle of 45 degrees with respect to the normal direction of the gate electrode 8 and at an angle of θ with respect to the normal direction of the support substrate 1. Is done. In addition,
The injection amount from one direction is, for example, about 5 × 10 ¹⁴ cm ⁻² .

As a result, an n-type impurity from one direction is introduced into a region shielded by the gate electrode 8 and the resist pattern 12 to form a third n ⁺ -type semiconductor region 6c, and the region shielded by the gate electrode 8 Alternatively, n-type impurities from two directions are introduced into a region shielded by resist pattern 12 to form second n ⁺ -type semiconductor region 6b, while n-type impurities from four directions are introduced into other regions. Thus, a first n ⁺ type semiconductor region 6a is formed. FIG. 7 is a cross-sectional view of a main part of the semiconductor substrate taken along line VII-VII in FIG.

Next, a titanium film (not shown) is deposited on the support substrate 1 by a sputtering method or a CVD method. Thereafter, heat treatment (first annealing) is performed by RTA (Rapid Thermal Annealing) at a temperature of 600 to 700 ° C. in a nitrogen atmosphere, and after removing an unreacted titanium film, the film is heated to 800 to 900 ° C. in a nitrogen atmosphere. By performing heat treatment (second annealing) at a temperature by the RTA method, the surface of the pair of n ⁺ -type semiconductor regions 6 constituting the source and the drain and the surface of the gate electrode 8 have a thickness of about 0.2 mm.
A silicide layer 9 composed of a TiSi ₂ film of about 07 μm is formed.

Here, as shown in FIG.
Since the depth of ⁺ -type semiconductor region 6c is approximately 0.06 .mu.m, the thickness of the silicide layer 9 is the 3n ⁺ -type semiconductor region 6c
And the silicide layer 9 contacts the p-type well 4 in the third n ⁺ -type semiconductor region 6c to form a Schottky junction.

In the first embodiment, the resist pattern 12 is used as a mask for the oblique ion implantation, but the polycrystalline silicon film of the same layer as the polycrystalline silicon film forming the gate electrode 8 is used for the oblique ion implantation mask. May be used. At least one portion of the element isolation region 10 surrounding the source has a rectangular shape made of a polycrystalline silicon film so that the shortest distance d from the intersection of the side wall of the gate electrode 8 and the element isolation region 10 is within G × tan θ. Form a pattern. Here, G is the thickness of the polycrystalline silicon film, θ is the angle with respect to the normal direction of the support substrate 1 and is 15 to 45.
Range of degrees. Next, in the same manner as in the above-described manufacturing method, an n-type impurity is introduced into the p-type well 4 by oblique ion implantation using shadowing of the gate electrode 8 and the pattern, thereby forming the first n ⁺ -type semiconductor region 6a, 2n ⁺ type semiconductor region 6b and third n ⁺ type semiconductor region 6
c can be formed.

In the first embodiment, the shape of the resist pattern 12 is rectangular. However, the present invention is not limited to this. The oblique ion implantation using shadowing of the gate electrode 8 and the resist pattern 12 is performed.
Some of the n ⁺ -type semiconductor region 6 constituting the source, shallow n ⁺ -type semiconductor region than the thickness of the silicide layer 9 may be formed.

As described above, according to the first embodiment, the resist pattern 12 is formed on the element isolation region 10 surrounding the source without being restricted by the margin for alignment with the element isolation region 10, and the gate electrode is formed. By the oblique ion implantation using shadowing of the resist pattern 8 and the resist pattern 12, a third n ⁺ -type semiconductor region 6c having a junction smaller than the thickness of the silicide layer 9 is formed in a part of the n ⁺ -type semiconductor region 6 constituting the source. Thus, a Schottky junction can be formed.

(Embodiment 2) FIG. 8 is a cross-sectional view of a main part of a semiconductor substrate showing a partially depleted MISFET according to another embodiment of the present invention. It is principal part sectional drawing of a board | substrate.

As shown in FIG. 8, n forming the drain
^{The +} type semiconductor region 6 includes a first n ⁺ type semiconductor region 6a and a second n ⁺ type semiconductor region 6b having an impurity concentration of about の of the first n ⁺ type semiconductor region 6a. The n ⁺ type semiconductor region 6 constituting the source
Is a first n ⁺ -type semiconductor region 6a and a second n ⁺ -type impurity region having an impurity concentration of about の of the first n ⁺ -type semiconductor region 6a.
^And a third n ⁺ -type semiconductor region 6c having an impurity concentration of about 1/4 of the first n ⁺ -type semiconductor region 6a.
There is a region in which both the p ⁺ -type semiconductor region 13 having an impurity concentration of about １ ／ of the n ⁺ -type semiconductor region 6a are formed, and a Schottky junction is formed in this region.

Next, the partially depleted type M according to the second embodiment will be described.
A method for manufacturing the ISFET will be briefly described.

First, similarly to the manufacturing method shown in FIG. 7 of the first embodiment, an n-type impurity is implanted into the p-type well 4 by ion implantation utilizing shadowing of the gate electrode 8 and the resist pattern 12. Then, a pair of n ⁺ -type semiconductor regions 6 constituting the source and the drain are formed. That is, at an angle of 45 degrees with respect to the normal direction of the gate electrode 8 and at an angle of θ with respect to the normal direction of the support substrate 1, n-type impurities are obliquely ion implanted into the p-type well 4 from four directions. Injected. The injection amount from one direction is, for example, about 5 × 10 ¹⁴ cm ⁻² .

As a result, an n-type impurity from one direction is introduced into a region shielded by the gate electrode 8 and the resist pattern 12 to form a third n ⁺ -type semiconductor region 6c, and the region shielded by the gate electrode 8 Alternatively, n-type impurities from two directions are introduced into a region shielded by resist pattern 12 to form second n ⁺ -type semiconductor region 6b, while n-type impurities from four directions are introduced into other regions. Thus, a first n ⁺ type semiconductor region 6a is formed.

Next, when the n ⁺ type semiconductor region 6 is formed, the amount of implantation from one direction is substantially the same, for example, about 5 × 1
A p-type impurity of about 0 ¹⁴ cm ^-2 , for example, B
Into the p-type semiconductor region 13 by ion implantation.
To form The depth of the p-type semiconductor region 13 from the surface of the thin-film silicon layer 2 is about 0.06 to 0.07 μm,
This cancels out the concentration distribution of the n-type impurity forming the third n ⁺ -type semiconductor region 6c.

Next, a silicide layer 9 composed of a TiSi ₂ film having a thickness of about 0.07 μm is formed on the surface of the pair of n ⁺ -type semiconductor regions 6 constituting the source and drain and the surface of the gate electrode 8. I do. However, in the region where the third n-type semiconductor region 6c and the p-type semiconductor region 13 are formed, the Schottky junction is formed by forming the silicide layer 9 in contact with the p-type semiconductor region 13 or the p-type well 4. Is done.

As described above, according to the second embodiment, 1
Third formed by oblique ion implantation from the direction
By introducing a p-type impurity into the n ⁺ -type semiconductor region 6c to cancel the concentration distribution of the n-type impurity, a Schottky junction can be reliably formed.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, a case where the present invention is applied to an n-channel MISFET has been described. However, the present invention can also be applied to a p-channel MISFET, and a similar effect can be obtained.

[0045]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the oblique ion implantation utilizing the shadowing by the mask pattern and the gate electrode formed on the element isolation region without being limited by the margin for alignment with the element isolation region allows the source to be formed. Since an n ⁺ -type semiconductor region shallower than the thickness of the silicide layer is partially formed and a Schottky junction can be formed in this region, it is possible to reduce the alignment margin between the element isolation region and the mask pattern. This makes it possible to miniaturize a partially depleted MISFET having a Schottky junction.

[Brief description of the drawings]

FIG. 1 shows a partially depleted MIS according to an embodiment of the present invention.
FIG. 3 is a plan view of a principal part of a semiconductor substrate showing an FET.

FIG. 2 is a sectional view of a principal part of the semiconductor substrate taken along line II-II of FIG. 1;

FIG. 3 is a sectional view of a principal part of the semiconductor substrate taken along line III-III in FIG. 1;

FIG. 4 is a partially depleted MIS according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing an FET.

FIG. 5 is a partially depleted MIS according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing an FET.

FIG. 6 shows a partially depleted MIS according to an embodiment of the present invention.
FIG. 4 is a plan view of a main part of a semiconductor substrate, illustrating a method for manufacturing an FET.

7 is a sectional view of a principal part of the semiconductor substrate taken along line VII-VII in FIG. 6;

FIG. 8 shows a partially depleted MI according to another embodiment of the present invention.
FIG. 3 is a cross-sectional view of a main part of a semiconductor substrate showing an SFET.

[Explanation of symbols]

Reference Signs List 1 support substrate 2 buried oxide film 3 thin-film silicon layer 4 p-type well 5 n ^- type semiconductor region 6 n ⁺ type semiconductor region 6a first n ⁺ type semiconductor region 6b second n ⁺ type semiconductor region 6c third n ⁺ type semiconductor region 7 gate Insulating film 8 gate electrode 9 silicide layer 10 element isolation region 11 sidewall spacer 12 resist pattern 13 p-type semiconductor region d distance

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) HM02 HM12 HM15 NN62

Claims (8)

[Claims] 1. A partially depleted MISFET having a source constituted by a plurality of semiconductor regions having relatively different impurity concentrations on an SOI substrate having a thin silicon layer provided on a supporting substrate via a buried insulating film. Wherein a silicide layer is formed on a surface of the active region in which the plurality of semiconductor regions are formed, and a junction depth of a part of the plurality of semiconductor regions constituting the plurality of semiconductor regions is provided. Is shallower than the thickness of the silicide layer,
A semiconductor integrated circuit device wherein a Schottky junction is formed. 2. The semiconductor integrated circuit device according to claim 1, wherein a part of the plurality of semiconductor regions is formed in an active region near a crossing of a side wall of a gate electrode and an element isolation region. A semiconductor integrated circuit device, wherein the semiconductor region is a semiconductor region. 3. The semiconductor integrated circuit device according to claim 1, wherein an impurity of a conductivity type different from an impurity forming said partial semiconductor region is introduced into a partial semiconductor region forming said plurality of semiconductor regions. And a semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein said silicide layer is a titanium silicide film, a cobalt silicide film, or a nickel silicide film. 5. A method of manufacturing a semiconductor integrated circuit device for forming a partially depleted MISFET having a Schottky junction on an SOI substrate having a thin silicon layer provided on a supporting substrate via a buried insulating film. (A) The shortest distance from the point where the side wall of the gate electrode and the element isolation region intersect is
Mask pattern thickness x tan θ (θ = 15 to 45 degrees)
Forming a mask pattern on a part of the element isolation region surrounding the source so as to be within (b) .45 ° with respect to the normal direction of the gate electrode, in the normal direction of the support substrate. A semiconductor comprising: a step of ion-implanting an impurity of the same conductivity type as the channel into the active region at an angle of θ, and (c) forming a silicide layer on the surface of the active region. A method for manufacturing an integrated circuit device. 6. A method of manufacturing a semiconductor integrated circuit device for forming a partially depleted MISFET having a Schottky junction on an SOI substrate having a thin silicon layer provided on a supporting substrate via a buried insulating film. (A) The shortest distance from the point where the side wall of the gate electrode and the element isolation region intersect is
Mask pattern thickness x tan θ (θ = 15 to 45 degrees)
Forming a mask pattern on a part of the element isolation region surrounding the source so as to be within (b) .45 ° with respect to the normal direction of the gate electrode, in the normal direction of the support substrate. (C) ion-implanting an impurity of the same conductivity type as the channel into the active region at an angle of θ, and (c) ion-implanting an impurity of a conductivity type different from the channel into the active region; Forming a silicide layer on the surface of the active region. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the mask pattern is formed of a resist film or a conductive film of the same layer as a conductive film forming a gate electrode. A method for manufacturing a semiconductor integrated circuit device. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the ion implantation in the step (b) is performed in four directions having an angle of 45 degrees with respect to a normal direction of the gate electrode. A method for manufacturing a semiconductor integrated circuit device.