JP2002231937A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the drive performance of a high breakdown voltage MOS transistor. SOLUTION: The semiconductor device comprises a low-concentration P- source and drain layer 11A formed in an N-well 5, a high-concentration P-source and drain layer formed in the low-concentration P-source and drain layer 11A, and an N-body layer 19A which constitutes a channel disposed between the source and drain layers. In the semiconductor device, a P-layer 32 is formed in a surface layer of the body layer 19A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a high voltage MOS transistor structure used for a driver for driving a liquid crystal, for example, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional semiconductor device and a method of manufacturing the same will be described below with reference to the drawings.

Here, the liquid crystal driving driver includes a logic (for example, 3V) N-channel MOS transistor and a P-channel MOS transistor, a high withstand voltage (for example, 30V) N-channel MOS transistor, and a P-channel type. MOS transistor, N-channel type D (Double
diffused) MOS transistor and P-channel type DM
For an OS transistor and a level shifter (for example, 30
V) It is composed of an N-channel MOS transistor or the like.

Here, the above-mentioned DMOS transistor structure means that a diffusion layer formed on the surface side of a semiconductor substrate is diffused with an impurity having a different conductivity type to form a new diffusion layer, and a diffusion layer is formed next to these diffusion layers. The difference in the directional diffusion is used as the effective channel length. By forming a short channel, the element is suitable for low on-resistance.

FIG. 15 is a cross-sectional view for explaining a conventional DMOS transistor.
A MOS transistor structure is illustrated. Note that P
Although the description of the structure of the channel type DMOS transistor is omitted, it is well known that the structure is the same except that the conductivity type is different.

In FIG. 15, reference numeral 51 denotes a semiconductor substrate (P-Sub) of one conductivity type, for example, a P-type, and 52 denotes an N-type well (NW).
B) 53 is formed, an N + type diffusion layer 54 is formed in the P type body layer 53, and an N + type diffusion layer 55 is formed in the N type well 52. A gate electrode 57 is formed on the substrate surface via first and second gate oxide films 56 and 59, and a channel 58 is formed in a surface region of the P-type body layer 53 immediately below the gate electrode 57. I have.

The N + type diffusion layer 54 is used as a source diffusion layer, the N + type diffusion layer 55 is used as a drain diffusion layer, and the N type well 52 under the LOCOS oxide film forming the second gate oxide film 59 is used as a drift layer. And Also, 60,
Reference numeral 61 denotes a source electrode and a drain electrode, respectively.
Is a P + type diffusion layer for taking the potential of the P type body layer 53, and 63 is an interlayer insulating film.

In the above DMOS transistor, N
By diffusion-forming the mold well 52, the concentration on the surface of the N-type well 52 is increased, so that the current can easily flow on the surface of the N-type well 52 and the breakdown voltage can be increased.

The DMOS transistor having such a configuration is called a reduced surface area (hereinafter referred to as RESURF) DMOS, and the dopant concentration of the drift layer of the N-type well 2 is RESURF.
It is set to satisfy the conditions. Such a technique is disclosed in Japanese Patent Application Laid-Open No. 9-139438.

[0010]

Here, the above DMOS
In the case of forming a transistor, a high-temperature heat treatment for forming the P-type body layer 53 is required after the formation of the gate electrode, so that the concentration profile in a low-voltage operation miniaturized device such as the 0.35 μm rule is disordered. For this reason, at present, after the gate electrode of the DMOS transistor is formed and the high-temperature heat treatment for forming the P-type body layer is completed, the miniaturized MOS transistor is started to be manufactured, which causes a problem that the manufacturing process becomes longer.

In addition, since the gate length of the DMOS transistor is basically determined by the diffusion coefficient and the diffusion start position of different ion species, there is a problem that the degree of freedom in designing the gate length is small.

Further, in the above DMOS transistor, when forming a P-channel DMOS transistor, the conductive film forming the gate electrode is often N-type. In this case, the driving capability of the P-channel DMOS transistor is low. Inferior to the N-channel DMOS transistor due to the difference in the mobility of the impurity ions.

[0013] Therefore, to compensate for this, it is necessary to improve the switching characteristics by applying a high voltage, which has been against the trend of lowering the voltage.

[0014]

SUMMARY OF THE INVENTION Accordingly, a semiconductor device according to the present invention has been made in view of the above problems, and includes, for example, a low-concentration reverse conductivity type source / drain layer formed in a semiconductor of one conductivity type; A high-concentration reverse-conductivity-type source / drain layer formed in a low-concentration reverse-conductivity-type source / drain layer, and one having a one-conductivity-type semiconductor layer forming a channel located between the source / drain layers; An opposite conductivity type layer is formed on a surface portion of the semiconductor layer.

By forming the opposite conductivity type layer on the surface layer of the one conductivity type semiconductor layer, the driving capability can be improved. In particular, an N-channel type M configured under the same conditions
By applying the present invention to a P-channel MOS transistor that is inferior to the driving capability of the OS transistor,
The driving capability of the P-channel type MOS transistor is improved,
The matching with the N-channel MOS transistor is improved.

Further, by forming an impurity layer for adjusting the driving capability in each channel corresponding to the semiconductor layer of each conductivity type, the driving capability of transistors of different conductivity types formed on the same substrate can be improved. Can be aligned.

Further, the semiconductor layer is formed only below the gate electrode, so that the body layer (corresponding to the semiconductor layer) surrounds the high concentration source layer as in the conventional structure. In comparison, the junction capacitance can be reduced.

Further, the low-concentration reverse conductivity type source / drain layer is formed so as to be in contact with the one conductivity type semiconductor layer formed below the gate electrode.

Further, a method of manufacturing a semiconductor device according to the present invention
Forming a low-concentration reverse-conductivity-type source / drain layer by injecting reverse-conductivity-type impurity ions into one-conductivity-type semiconductor;
Forming a high-concentration reverse-conductivity-type source / drain layer in the low-concentration reverse-conductivity-type source / drain layer by implanting a reverse-conductivity-type impurity ion into the semiconductor; Implanting to form a semiconductor layer of one conductivity type forming a channel located between the source layer of the opposite conductivity type and the drain layer of the opposite conductivity type; and implanting impurity ions of the opposite conductivity type into the surface layer of the semiconductor layer. Forming a reverse-conductivity-type layer by using the above-mentioned method, and forming a gate electrode on the semiconductor layer via a gate oxide film.

As a result, in the conventional channel forming method using thermal diffusion of impurity ions as in a DMOS transistor, the channel length is uniquely determined.
In the manufacturing method of the present invention, since the semiconductor layer is formed by the ion implantation process, various settings can be made, and the degree of freedom in designing the gate length is increased as compared with the conventional method.

Further, since high-temperature heat treatment after the formation of the gate electrode for forming the semiconductor layer is not required as in the conventional method, it is possible to mount the semiconductor device together with the miniaturization process.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment according to a semiconductor device of the present invention and a method for manufacturing the same will be described with reference to the drawings.

Here, FIG. 10 shows a semiconductor device of the present invention, that is, a liquid crystal driving driver, from the left side of the drawing (a), a logic (for example, 3V) N-channel MOS transistor, a P-channel MOS transistor, and a level shifter. (For example, 30 V) N-channel MOS transistor, and high breakdown voltage (for example, 30 V) N-channel MOS transistor
A transistor, a P-channel MOS transistor of the same high breakdown voltage (for example, 30 V) from the left side of FIG.
The high breakdown voltage (for example, 30 V) N-channel type DMOS transistor and the P
It is composed of a channel type DMOS transistor.

Hereinafter, a method of manufacturing various MOS transistors constituting the liquid crystal driving driver will be described.

First, in FIG. 1, in order to define regions for constituting various MOS transistors, for example, P
A P-type well (P-sub) is provided in a P-type semiconductor substrate (P-Sub) 1.
W) 3 and an N-type well (NW) 5 are formed.

That is, in a state where the N-type well formation region of the substrate 1 is covered with a resist film (not shown) via the pad oxide film 2, for example, boron ions are accelerated to about 8 × 10 ¹² / acceleration voltage of about 80 KeV. Ion implantation is performed under the implantation condition of cm ² . Then, in a state where the upper said P-type well 3 were coated with a resist film 4 as shown in FIG. 1, for example, phosphorus ions at an acceleration voltage of approximately 80 KeV, ions are implanted at an implantation condition of 9 × 10 ¹² / cm ^2. Actually, as described above, each ion species implanted is thermally diffused (for example, 115
The P-type well 3 and the N-type well 5 are formed in an N ₂ atmosphere at 0 ° C. for 4 hours.

Next, in FIG. 2, in order to separate elements for each MOS transistor, an element isolation film 8 of about 500 nm is formed by a LOCOS method, and about 80 nm of an active area other than the element isolation film 8 is formed. A thick gate oxide film 9 for high breakdown voltage is formed by thermal oxidation.

Subsequently, a first low-concentration N-type and P-type source / drain layer (hereinafter referred to as L
These are referred to as an N layer 10 and an LP layer 11. ) Is formed. That is, first, for example, phosphorus ions are implanted into the surface layer of the substrate at an acceleration voltage of about 120 KeV under an implantation condition of 8 × 10 ¹² / cm ² while a region other than the LN layer formation region is covered with a resist film (not shown). Thus, the LN layer 10 is formed. Thereafter, for example, boron ions are applied to the surface layer of the substrate at an acceleration voltage of about 120 KeV at a rate of 8.5 × 10 ¹² / cm while the area other than the area where the LP layer is formed is covered with the resist film (PR).
^The LP layer 11 is formed by ion implantation under the implantation conditions of ² .
Note that, in practice, a subsequent annealing step (for example, 1100
After 2 hours in an N ₂ atmosphere at a temperature of ₂ ° C., the ion species implanted are thermally diffused to form the LN layer 10 and the LP layer 11.

Subsequently, in FIG. 3, a second low-concentration N-type and P-type source / drain layer (hereinafter referred to as SLN layer 13) is formed between the LN layers 10 and between the LP layers 11 using the resist film as a mask. And the SLP layer 14). That is, first, for example, phosphorus ions are applied to the surface layer of the substrate at an acceleration voltage of about 120 KeV for 1.5 × with a resist film (not shown) covering an area other than the SLN layer formation area.
The SLN layer 13 connected to the LN layer 10 is formed by ion implantation under an implantation condition of 10 ¹² / cm ² . Thereafter, for example, boron difluoride ions are applied to the surface layer of the substrate at an acceleration voltage of about 140 KeV at a rate of 2.5 × 10 ¹² / cm 2 while areas other than the SLP layer formation area are covered with the resist film (PR).
^The SLP layer 14 connected to the LP layer 11 is formed by ion implantation under the implantation conditions of ² . Incidentally, the LN layer 10 and the S
The impurity concentrations of the LN layer 13 or the LP layer 11 and the SLP layer 14 are set to be substantially equal or one of them becomes higher.

Further, in FIG. 4, the resist film is masked.
High-concentration N-type and P-type source / drain layers
Below, they are referred to as an N + layer 15 and a P + layer 16. ) Is formed. Immediately
First, a resist film (not shown) other than on the N + layer forming region
In the state of covering the area of the substrate, for example, phosphorus ions
At an acceleration voltage of about 80 KeV and 2 × 10¹⁵/ Cm ^Two
The N + layer 15 is formed by ion implantation under the implantation conditions described above. So
After that, the resist film (PR) is used to cover areas other than the P + layer formation area.
In the state where the area is covered, for example, boron difluoride
The ions were accelerated at about 140 KeV and 2 × 10¹⁵
/ Cm^TwoP + layer 16 is formed by ion implantation under the following implantation conditions.
I do.

Next, referring to FIG. 5, using a resist film as a mask, a reverse conductivity type impurity is ion-implanted into the center of the SLN layer 13 connected to the LN layer 10 and the center of the SLP layer 14 connected to the LP layer 11, respectively. By injecting, the S
P-type body layer 1 separating LN layer 13 and SLP layer 14
8 and the N-type body layer 19 are formed. That is, first, boron difluoride ions are implanted into the surface of the substrate at an acceleration voltage of about 120 KeV at a dose of 5 × 10 ¹² / cm ^{2 while} a region other than the P-type layer forming region is covered with a resist film (not shown). P-type body layer 18 is formed by ion implantation under conditions. Thereafter, with the resist film (PR) covering the area other than the N-type layer forming area, for example, phosphorus ions are applied to the surface of the substrate at an acceleration voltage of about 190 KeV at 5 × 10 ¹² / c.
The N-type body layer 19 is formed by ion implantation under the implantation condition of m ² . The order of the operation steps related to the ion implantation step shown in FIGS. 3 to 5 can be appropriately changed.
Channels are formed in the surface layers of the mold body layer 18 and the N-type body layer 19.

Further, a second P-type well (SPW) 21 is provided in the substrate (P-type well 3) of the miniaturized N-channel type and P-channel type MOS transistor formation region for the normal breakdown voltage.
And a second N-type well (SNW) 22 is formed.

That is, the normal breakdown voltage N-channel MOS
Using a resist film (not shown) having an opening on the transistor formation region as a mask, for example, boron ions are introduced into the P-type well 3 at an acceleration voltage of about 190 KeV for 1.5 ×.
After ion implantation under the first implantation condition of 10 ¹³ / cm ² , boron ions are also implanted at an acceleration voltage of about 50 KeV.
Ion implantation is performed under the second implantation condition of 6 × 10 ¹² / cm ² to form a second P-type well 21. Further, the resist film (PR) having an opening on the P-channel type MOS transistor formation region for normal withstand voltage is used as a mask to form the P-type MOS transistor.
For example, about 380 KeV phosphorus ions are introduced into the mold well 3.
The second N-type well 22 is formed by ion implantation at an acceleration voltage of 1.5 × 10 ¹³ / cm ² . still,
In the case where there is no high acceleration voltage generator of about 380 KeV, a double charge system may be used in which divalent phosphorus ions are implanted at an acceleration voltage of about 190 KeV and under an implantation condition of 1.5 × 10 ¹³ / cm ² . Followed by an acceleration voltage of approximately 140KeV phosphorous ions, 4.0 × 10 ¹² / cm
Ion implantation is performed under the implantation conditions of ² .

Next, in FIG. 7, after removing the gate oxide film 9 on the N-channel type and P-channel type MOS transistor forming regions for normal breakdown voltage and on the N-channel type MOS transistor forming region for level shifters, A gate oxide film having a desired thickness is newly formed on the region.

That is, first, the entire surface is about 14 nm for the N-channel type MOS transistor for the level shifter (about 7 nm at this stage, but the film thickness increases when a later-described gate oxide film for normal withstand voltage is formed). .)
Is formed by thermal oxidation. continue,
After removing the gate oxide film 24 of the level shifter N-channel type MOS transistor formed on the N-type and P-channel type MOS transistor formation regions for normal withstand voltage, a thin gate oxide film for normal withstand voltage is formed in this region. 25 (about 7 nm) is formed by thermal oxidation.

Subsequently, in FIG.
A polysilicon film of about 0 nm is formed, and this polysilicon
POCl on the membrane_ThreeMade conductive by heat diffusion as heat diffusion source
Later, on this polysilicon film, about 100 nm
Tungsten silicide (WSix) film, and about
About 150nm SiO_TwoLaminate the film and use a resist (not shown)
Pattern for each MOS transistor
Gate electrodes 27A, 27B, 27C, 27D, 27
E, 27F and 27G are formed. The SiO _Twofilm
Act as a hard mask during patterning.

Subsequently, in FIG. 9, low-concentration source / drain layers are formed for the normal breakdown voltage N-channel and P-channel MOS transistors.

That is, first, an N-channel type M for normal withstand voltage is used.
Low concentration source / drain layer formation area for OS transistor
Mask the resist film (not shown) that covers the area other than the area
Then, for example, the phosphorous ion is accelerated by about 20 KeV.
By pressure, 6.2 × 10¹³/ Cm ^TwoImplantation under the same implantation conditions
Then, a low concentration N- type source / drain layer 28 is formed.
You. Also, a P-channel MOS transistor for normal withstand voltage
Area except on the low concentration source / drain layer formation area
Using the resist film (PR) covering the mask as a mask, for example,
Acceleration voltage of about 20 KeV for boron difluoride ion
And 2 × 10¹³/ Cm^TwoIon implantation under the implantation conditions of
A low concentration P- type source / drain layer 29 is formed.

Further, in FIG. 10, the gate electrodes 27A, 27B, 27C, 27D, 27E, 27
F, T of about 250 nm to cover 27G
An EOS film 30 is formed by an LPCVD method, and the TEOS film 30 is anisotropically etched using a resist film (PR) having openings on the N-type and P-channel type MOS transistor formation regions for the normal breakdown voltage as a mask. .
As a result, as shown in FIG.
A, side wall spacer films 30 on both side walls of 27B
A is formed, and the TEOS film 30 remains in a region covered with the resist film (PR).

The gate electrode 27A, the side wall spacer film 30A, and the gate electrode 27B
Then, using the sidewall spacer film 30A as a mask, a high-concentration source / drain layer is formed for the normal breakdown voltage N-channel and P-channel MOS transistors.

That is, by using a resist film (not shown) covering a region other than the region for forming the high-concentration source / drain layers for the N-channel MOS transistor for normal breakdown voltage as a mask, for example, arsenic ions are accelerated at about 100 KeV. Then, ion implantation is performed under an implantation condition of 5 × 10 ¹⁵ / cm ² ,
A high concentration N + type source / drain layer 31 is formed. Also, using a resist film (not shown) covering a region other than the region for forming the high-concentration source / drain layer for the normally-breakdown-voltage P-channel MOS transistor as a mask, for example, boron difluoride ion at an acceleration voltage of about 40 KeV , 2 ×
Ion implantation is performed under an implantation condition of 10 ¹⁵ / cm ² to form a high concentration P + type source / drain layer 32.

Although not shown in the drawings, the entire surface is made of a TEOS film, a BPSG film, etc.
By forming a metal wiring layer in contact with each of the high-concentration source / drain layers 15, 16, 31 and 32 after forming an interlayer insulating film of the order of magnitude, a normal withstand voltage for the liquid crystal driving driver is formed. N-channel MOS transistor and P-channel MOS transistor, N-channel MOS transistor for level shifter, N for high breakdown voltage
Channel type MOS transistor and P channel type MOS
Transistor, N-channel DMOS transistor for high breakdown voltage with reduced on-resistance and P-channel DMO
The S transistor is completed.

FIGS. 11A and 11B respectively show the gate electrodes 27 of the N-channel MOS transistor and the P-channel MOS transistor shown in FIG. 10B.
X1-X1 line and X2 for indicating the width direction of F and 27G
FIG. 3 is a cross-sectional view taken along line X2.

As described above, according to the structure of the present invention, in the N-channel MOS transistor and the P-channel MOS transistor for high withstand voltage with a reduced on-resistance, the P-type body layer or the N-type body layer is connected to the gate electrode. Since it is formed only below, the junction capacitance can be reduced as compared with a conventional structure in which a P-type body layer or an N-type body layer wraps a high concentration source layer.

Further, in the above structure, since the P-type body layer or the N-type body layer is formed by ion implantation, miniaturization can be achieved as compared with the conventional diffusion-formed one.

Further, according to the above-described manufacturing method, when forming a DMOS transistor as in the conventional method, a high-temperature heat treatment after forming a gate electrode for forming a body layer is not required. Will be possible.

In a conventional channel forming method by thermal diffusion of impurity ions as in a DMOS transistor,
Although the channel length is uniquely determined, in the method of manufacturing a high-breakdown-voltage MOS transistor with a reduced on-resistance according to the present invention, as described above, the P-type body layer or the N-type
Since the mold body layer is formed through an ion implantation process,
Various settings can be made, and the degree of freedom in designing the gate length is increased as compared with the conventional method.

The body region is preferably formed by an ion implantation method, but other steps can be appropriately changed, such as a gas phase or diffusion from a solid phase.

Further, when a high breakdown voltage MOS transistor is formed as in the conventional method, a high-temperature heat treatment after the formation of the gate electrode for forming the body layer is not required, so that it can be mounted together with a miniaturization process. Drivers (for example, liquid crystal display drivers) for various display elements and a controller can be integrated into one chip.

Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. 12 (a) and 12 (b).

Here, the feature of the second embodiment is that the P-channel type MO for high withstand voltage, which has a low on-resistance as described above, is used.
This means that a P-type layer 32 for adjusting the threshold voltage is formed in the surface layer (channel region) of the N-type body layer 19A of the S transistor. Here, the P-type layer 32 is formed by forming at least the gate electrode 2 after forming the N-type body layer 19A.
By the previous step of forming 7G, P-type impurities, for example, boron difluoride ions are implanted at an acceleration voltage of about 120 KeV and under an implantation condition of 3 × 10 ¹² / cm ² .

As described above, the P-type layer 32 for adjusting the threshold voltage is formed in the surface layer (channel region) of the N-type body layer 19A.
Is formed, the P which is inferior to the driving capability of the N-channel type MOS transistor when configured under the same conditions.
The driving capability of the channel type MOS transistor can be improved.

Therefore, by adjusting the concentration of the P-type layer, the driving capability of the N-channel MOS transistor can be set to be substantially the same as that of the N-channel MOS transistor. There is no need to apply the voltage, which is advantageous for lowering the voltage.

Although illustration is omitted, FIG.
(A) and (b) show the structure of a P-channel MOS transistor, but the driving capability can be similarly improved by configuring the N-channel MOS transistor in the same manner except that the conductivity type is different.

As described above, in the P-channel MOS transistor and the N-channel MOS transistor,
By forming an impurity layer for adjusting the driving capability in each channel corresponding to the body layers of various conductivity types, the driving capability of transistors of different conductivity types formed on the same substrate can be uniformed.

Further, according to the present invention, when a plurality of transistors having the same conductivity type but different sizes are formed on the same substrate, an impurity layer having a conductivity type opposite to that of the body layer is formed in each body layer. , It is also possible to adjust the driving capability.

Also, in the first and second embodiments, the source / drain layer structure is left-right symmetric, so that it can be easily applied to a circuit which can be connected bidirectionally in a circuit, for example, an analog switch. Although there is an advantage that the manufacturing process is simplified, the present invention is not limited to this, and if there is no restriction on the direction of the source / drain layer, a source / drain layer structure which is not symmetrical between the right and left sides may be adopted. .

That is, the third embodiment will be described by taking a P-channel type MOS transistor as an example as shown in FIG. 13 in the high breakdown voltage MOS transistor in which the on-resistance is reduced. Note that the N-channel MOS transistor is similarly configured except that the conductivity type is different.

For example, a gate electrode 27G formed on a P-type semiconductor substrate 1 via a gate oxide film 9, and a high-concentration P + type source layer formed adjacent to one end of the gate electrode 27G 16A and the gate electrode 27G
And a high-concentration P + type drain layer 16A formed separately from the other end of the gate electrode 27G.
A low-concentration P-type drain layer (LP) 11A formed so as to surround the + -type drain layer 16A, and formed between the P + -type source layer 16A and the P-type drain layer (LP) 11A below the gate electrode 27G. N-type body layer 19
B.

Then, the manufacturing method is performed by a resist (not shown).
In a state where the area other than the LP layer forming area is covered with the
For example, boron ions of about 120
8.5 × 10 at KeV accelerating voltage¹²/ Cm^TwoInjection strip
In this case, ions are implanted to form the LP layer 11A. Incidentally, actually
A post-annealing step (for example, N _Two
After 2 hours in an atmosphere, the boron ions are thermally expanded.
It is scattered to become the LP layer 11A.

Subsequently, in a state where a region other than the SLP layer forming region is covered with a resist film (not shown), for example, boron difluoride ion is applied to the surface layer of the N-type well 5 at about 140 KeV.
At an acceleration voltage of 2.5 × 10 ¹² / cm ² , ions are implanted under a condition of 2.5 × 10 ¹² / cm ² to form a second low-concentration P-type drain layer (hereinafter referred to as an SLP layer 14A) so as to be continuous with the LP layer 11A. ) Is formed. The LP layer 11A and the SLP
The impurity concentration of the layer 14A is set to be substantially equal or one of them is higher.

Further, using a resist film (not shown) as a mask, a high-concentration P-type source / drain layer (hereinafter referred to as a P + layer 16).
Called A. ) Is formed. That is, first, for example, boron difluoride ion is applied to the surface layer of the N-type well 5 in a state where the resist film covers an area other than the P + layer forming area.
The P + layer 16A is formed by ion implantation at an acceleration voltage of 40 KeV under an implantation condition of 2 × 10 ¹⁵ / cm ² .

Next, an impurity of the opposite conductivity type is ion-implanted into the SLP layer 14A connected to the LP layer 11A by using a resist film (not shown) as a mask, so that the N + is adjacent to the P + layer 16A on the source side. The mold body layer 19B is formed. That is, with the resist film covering the region other than the N-type layer forming region, the surface layer of the N-type well 5 is doped with, for example, phosphorus ions at an acceleration voltage of about 190 KeV at 5 × 10 ¹² /
N-type body layer 19B by ion implantation under the implantation condition of cm ²
To form The above-mentioned SLP layer 14A, P + layer 16
The order of the operation steps for the various ion implantation steps for forming the A and N-type body layers 19B can be changed as appropriate.
A channel is formed on the surface of the N-type body layer 19B.

Then, a gate electrode 27G may be formed via the gate insulating film 9 formed on the substrate 1 (N-type well 5).

By adopting such a structure, the driving capability can be improved because there is no low-concentration layer on the source side as compared with the symmetrical source / drain layer structure.

FIG. 14 shows an example of a high-breakdown-voltage MOS transistor according to the fourth embodiment of the present invention. The N-body layer in the left-right asymmetric source / drain layer structure according to the third embodiment described above. A P-type layer 32A, which is an impurity layer of a conductivity type opposite to that of the N-body layer 19B, is formed in the surface layer portion of the substrate 19B. Here, the P-type layer 32A is formed, for example, by adding boron difluoride ion as a P-type impurity to about 120 Ke after the formation of the N body layer 19B and before the step of forming the gate electrode 27G.
It is formed by ion implantation at an acceleration voltage of V under an implantation condition of 3 × 10 ¹² / cm ² .

By adopting such a structure, the third embodiment can improve the driving capability by forming an impurity layer of a conductivity type opposite to that of the body layer in the surface layer of the body layer in the second embodiment. The driving capability can be further improved by the synergistic effect of the improvement of the driving capability due to the absence of the low concentration layer on the source side in the embodiment. Note that the N-channel MOS transistor is similarly configured except that the conductivity type is different.

[0068]

According to the present invention, since the semiconductor layer constituting the channel is formed only under the gate electrode, the junction capacitance is reduced as compared with the conventional structure in which the semiconductor layer wraps the high-concentration source layer. Can be achieved.

Further, since the semiconductor layer is formed by ion implantation, miniaturization is possible as compared with a conventional diffusion-formed one.

Further, since high-temperature heat treatment after forming a gate electrode for forming a semiconductor layer is not required, mixed mounting with a miniaturization process becomes possible.

In the conventional method of forming a channel by thermal diffusion of impurity ions as in the case of a DMOS transistor, the channel length is uniquely determined. In the present invention, however, the semiconductor layer is subjected to the ion implantation step as described above. Since it is formed after passing through, various settings can be made, and the degree of freedom in designing the gate length is increased as compared with the conventional method.

Further, the surface portion (channel region) of the semiconductor layer
The driving capability is improved by forming an impurity layer for adjusting the threshold voltage in the semiconductor device. Particularly, by applying the present invention to a P-channel type MOS transistor, the driving capability of the N-channel type MOS transistor can be reduced under the same conditions. It is possible to improve the driving ability of the inferior P-channel MOS transistor. Therefore, by adjusting the concentration of the P-type layer formed in the surface portion of the N-type semiconductor layer, the driving capability of the P-channel MOS transistor can be set to be substantially equal to the driving capability of the N-channel MOS transistor. In order to improve the switching characteristics of the MOS transistor, for example, it is not necessary to apply a high voltage, which is advantageous in lowering the voltage.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a sectional view illustrating the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a sectional view illustrating the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a sectional view illustrating the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a sectional view illustrating the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 7 is a sectional view illustrating the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 8 is a sectional view illustrating the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 9 is a sectional view illustrating the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 10 is a sectional view illustrating the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 11 is a sectional view illustrating the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 12 is a sectional view illustrating the method of manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 13 is a sectional view illustrating the method of manufacturing the semiconductor memory device according to the third embodiment of the present invention.

FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 15 is a sectional view showing a conventional semiconductor device.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Kazuhiro Yoshitake 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term in Sanyo Electric Co., Ltd. (reference) 5F040 DA02 DA05 DA12 DA22 DB03 EA09 EC01 EC07 EC13 EE05 EF02 EF11 EF13 EJ08 EK01 EM01 EM02 FA01 FA03 FA05 FA16 FA17 FA19 FB02 5F048 AA08 AB03 AC01 AC03 BA01 BB05 BB08 BB12 BB16 BC03 BC06 BC18 BC19 BD04 BE03 BG12 DA18 DA21 DA25

Claims (10)

[Claims] 1. A semiconductor device having a reverse conductivity type source / drain layer formed in a semiconductor of one conductivity type and a semiconductor layer of one conductivity type forming a channel located between the source / drain layers. A semiconductor device, characterized in that a reverse conductivity type layer is formed on the surface layer of (1). 2. A gate electrode formed on a semiconductor of one conductivity type via a gate oxide film, a source / drain layer of a low concentration opposite conductivity type formed adjacent to the gate electrode, and the gate A high-concentration reverse-conductivity-type source / drain layer separated from an electrode and formed in the low-concentration reverse-conductivity-type source / drain layer; and the reverse-conductivity-type source layer and the reverse-conductivity-type drain below the gate electrode. A semiconductor device comprising: a semiconductor layer of one conductivity type forming a channel positioned between layers; and a layer of a reverse conductivity type formed in a surface portion of the semiconductor layer. 3. The semiconductor device according to claim 1, wherein the semiconductor layer is formed only in a predetermined region below the gate electrode. 4. The semiconductor device according to claim 2, wherein the low-concentration reverse conductivity type source / drain layer is formed to be in contact with a semiconductor layer formed below the gate electrode. 5. The semiconductor device according to claim 1, wherein the low-concentration reverse conductivity type source / drain layer is formed so as to be shallowly extended in the semiconductor surface layer so as to be in contact with the semiconductor layer formed below the gate electrode. 3. The semiconductor device according to 2. 6. A method of manufacturing a semiconductor device having a reverse conductivity type source / drain layer formed on a semiconductor of one conductivity type and a semiconductor layer of one conductivity type forming a channel located between the source / drain layers. The method of manufacturing a semiconductor device, wherein the step of forming the one conductivity type semiconductor layer includes a step of implanting one conductivity type impurity ion into the semiconductor by an ion implantation method. 7. A low-concentration reverse-conductivity-type source / drain layer formed in one-conductivity-type semiconductor and a high-concentration reverse-conductivity-type source / drain layer formed in said low-concentration reverse-conductivity-type source / drain layer. In a method for manufacturing a semiconductor device having a drain layer and a one-conductivity-type semiconductor layer forming a channel located between the source / drain layers, the step of forming the one-conductivity-type semiconductor layer includes: A method of manufacturing a semiconductor device, comprising a step of implanting impurity ions of one conductivity type. 8. A low-concentration source / drain layer having a low concentration formed in a semiconductor of one conductivity type, and a source / drain layer having a high concentration formed in the low-concentration source / drain layer having a low concentration. In a method of manufacturing a semiconductor device having a drain layer and a semiconductor layer of one conductivity type forming a channel located between the source / drain layers, a source of a low-concentration reverse conductivity type is formed by implanting a reverse conductivity type impurity ion into the semiconductor. A step of forming a drain layer; and a step of implanting a reverse conductivity type impurity ion into the semiconductor to form a high concentration reverse conductivity type source / drain layer in the low concentration reverse conductivity type source / drain layer. Implanting impurity ions of one conductivity type into the semiconductor to form a semiconductor layer of one conductivity type constituting a channel located between the source layer of the opposite conductivity type and the drain layer of the opposite conductivity type; Forming a reverse conductivity type layer by implanting a reverse conductivity type impurity ion into a surface portion of the conductor layer; and forming a gate electrode on the semiconductor via a gate oxide film. A method for manufacturing a semiconductor device. 9. The method according to claim 7, wherein the step of forming the low-concentration reverse-conductivity-type source / drain layer is performed by an ion implantation method so as to be in contact with a semiconductor layer formed below the gate electrode. A method for manufacturing a semiconductor device according to claim 8. 10. The step of forming the low-concentration reverse-conductivity-type source / drain layer includes forming a shallow extension on the semiconductor surface layer so as to be in contact with the semiconductor layer formed below the gate electrode by at least an ion implantation method. 9. The method for manufacturing a semiconductor device according to claim 7, wherein: