CN116568038A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN116568038A CN116568038A CN202310840227.6A CN202310840227A CN116568038A CN 116568038 A CN116568038 A CN 116568038A CN 202310840227 A CN202310840227 A CN 202310840227A CN 116568038 A CN116568038 A CN 116568038A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000002513 implantation Methods 0.000 claims abstract description 94
- 238000002347 injection Methods 0.000 claims abstract description 85
- 239000007924 injection Substances 0.000 claims abstract description 85
- 238000005468 ion implantation Methods 0.000 claims abstract description 85
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 59
- 150000002500 ions Chemical class 0.000 claims abstract description 53
- 238000003860 storage Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims description 90
- 239000007943 implant Substances 0.000 claims description 37
- 238000010884 ion-beam technique Methods 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 description 4
- 230000015654 memory Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ion Chemical class 0.000 description 1
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
Abstract
The invention provides a manufacturing method of a semiconductor device, which is characterized in that a first drain end injection region of a storage device region and a second source end injection region and a second drain end injection region of a high-voltage device region are subjected to light doped ion injection at a preset inclination angle, so that partial ions injected into the first drain end injection region are blocked by a patterned photoresist layer to form a shadow region on the first drain end injection region, and the dose of the ions injected into the first drain end injection region is smaller than that of the ions injected into the second source end injection region or the second drain end injection region by utilizing the shadow region. Therefore, the same patterned photoresist layer can be used as a mask, and meanwhile, lightly doped ion implantation is carried out on the high-voltage device region and the storage device region, so that the dosage of ions implanted into the first drain end implantation region is smaller than that of ions implanted into the second source end implantation region or the second drain end implantation region, the mask can be saved, the process flow is simplified, and the effective channel length of the storage device region is ensured.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
Flash memory (flash) is used as a safe and quick storage body, and becomes the most main carrier of data and programs in an embedded system by a series of advantages of small volume, large capacity, low cost, no loss of power-down data and the like.
In the existing manufacturing process of flash memories such as embedded flash memories, lightly doped ion implantation is required for the region for forming the drain region in the substrate of the memory device region, and lightly doped ion implantation is required for the region for forming the source region and the drain region in the substrate of the high-voltage device region to adjust the threshold voltage and the like; in the prior art, since the channel length of the memory device region is smaller than that of the high-voltage device region, in order to ensure the effective channel length of the memory device region after the lightly doped ion implantation, the dosage of the lightly doped ion implantation to the substrate of the memory device region is smaller than that of the lightly doped ion implantation to the substrate of the high-voltage device region, and therefore, the lightly doped ion implantation to the substrate of the memory device region and the lightly doped ion implantation to the substrate of the high-voltage device region are respectively performed in different steps, and two layers of masks are required for the two doping steps, so that the process is complex, the manufacturing cost is increased, and the process time is increased.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which is used for simplifying the process flow and saving masks.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate, wherein the substrate is provided with a high-voltage device region and a storage device region which are adjacent, a first source end injection region and a first drain end injection region are defined in the substrate of the storage device region, and a second source end injection region and a second drain end injection region are defined in the substrate of the high-voltage device region; forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer at least exposes the first drain end injection region, the second source end injection region and the second drain end injection region; and performing lightly doped ion implantation on the first drain end implantation region, the second source end implantation region and the second drain end implantation region by using the patterned photoresist layer as a mask and at a preset inclination angle, so that part of ions implanted into the first drain end implantation region are shielded by the patterned photoresist layer to form a shadow region on the first drain end implantation region, and the shadow region is utilized to enable the dose of ions implanted into the first drain end implantation region to be smaller than the dose of ions implanted into the second source end implantation region or the second drain end implantation region.
Optionally, in the method for manufacturing a semiconductor device, the preset inclination angle is an included angle between an ion beam and a plane perpendicular to the substrate, and the preset inclination angle is 30 ° to 45 °.
Optionally, in the method for manufacturing a semiconductor device, the method for lightly doping ion implantation in the first drain implantation region, the second source implantation region and the second drain implantation region at a preset inclination angle includes: placing a substrate with a patterned photoresist layer on an ion implantation tray, so that the substrate is positioned at a first preset position, and performing first lightly doped ion implantation on the first drain end implantation region, the second source end implantation region and the second drain end implantation region at the preset inclination angle; rotating the substrate to a second preset position along the clockwise direction, and carrying out second lightly doped ion implantation on the first drain end implantation region, the second source end implantation region and the second drain end implantation region at the preset inclination angle; rotating the substrate to a third preset position along the clockwise direction, and carrying out third lightly doped ion implantation on the first drain end implantation region, the second source end implantation region and the second drain end implantation region at the preset inclination angle; rotating the substrate to a fourth preset position along the clockwise direction, and carrying out fourth lightly doped ion implantation on the first drain end implantation region, the second source end implantation region and the second drain end implantation region at the preset inclination angle; wherein the first lightly doped ion implantation, the second lightly doped ion implantation, the third lightly doped ion implantation and the fourth lightly doped ion implantation have the same dosage.
Optionally, in the method for manufacturing a semiconductor device, when lightly doped ion implantation is performed on the first drain implantation region, the second source implantation region and the second drain implantation region, a total dose of ions implanted into the first drain implantation region is not greater than one half of a total dose of ions implanted into the second source implantation region or the second drain implantation region.
Optionally, in the method for manufacturing a semiconductor device, ions of the first lightly doped ion implantation, the second lightly doped ion implantation, the third lightly doped ion implantation, and the fourth lightly doped ion implantation, which are two times of lightly doped ion implantation into the first drain implant region, are blocked by the patterned photoresist layer.
Optionally, in the method for manufacturing a semiconductor device, the first preset position, the second preset position, the third preset position, and the fourth preset position are spaced at the same angle.
Optionally, in the method for manufacturing a semiconductor device, a high-voltage gate structure is formed on a substrate of the high-voltage device region, and the second source end injection region and the second drain end injection region are respectively located in the substrates of the high-voltage device regions at two sides of the high-voltage gate structure; and a control gate structure and a selection gate structure which are arranged at intervals are formed on the substrate of the storage device region, and the first source end injection region and the first drain end injection region are respectively positioned in the substrates of the storage device regions at two sides of the selection gate structure.
Optionally, in the method for manufacturing a semiconductor device, the high-voltage gate structure includes a high-voltage gate oxide layer and a high-voltage gate located on the high-voltage gate oxide layer.
Optionally, in the method for manufacturing a semiconductor device, the control gate structure includes a floating gate oxide layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially stacked from bottom to top; the select gate structure includes a select gate oxide layer and a select gate on the select gate oxide layer.
Optionally, in the method for manufacturing a semiconductor device, when a patterned photoresist layer is formed on the substrate, the patterned photoresist layer covers the first source-end injection region, the high-voltage gate structure, the control gate structure, a part of the select gate structure and a part of the substrate of the high-voltage device region, and the patterned photoresist layer also exposes a part of the select gate structure, a part of the substrate of the high-voltage device region on a side, away from the high-voltage gate structure, of the second source-end injection region and a part of the substrate of the high-voltage device region on a side, away from the high-voltage gate structure, of the second drain-end injection region, wherein the part of the substrate of the high-voltage device region, exposed by the patterned photoresist layer, is closer to the high-voltage gate structure than the part covered by the patterned photoresist layer.
In the method for manufacturing the semiconductor device, the first drain injection region of the memory device region and the second source injection region and the second drain injection region of the high-voltage device region are subjected to light doped ion injection at the preset inclination angle, so that part of ions injected into the first drain injection region are blocked by the patterned photoresist layer to form a shadow region on the first drain injection region, and the dose of the ions injected into the first drain injection region is smaller than that of the ions injected into the second source injection region or the second drain injection region by utilizing the shadow region. Therefore, the same patterned photoresist layer can be used as a mask, light doped ion implantation is carried out on the high-voltage device region and the storage device region, and the dosage of ions implanted into the first drain end implantation region of the storage device region is smaller than that of ions implanted into the second source end implantation region or the second drain end implantation region of the high-voltage device region, so that one layer of mask can be saved, the process flow is simplified, the effective channel length of the storage device region is ensured, and the channel leakage of the storage device region is avoided.
Drawings
Fig. 1 is a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of the structure of a high-voltage device region and a memory device region in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a structure in a step of forming a patterned photoresist layer in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a structure in a step of performing lightly doped ion implantation in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 5 is a top view in a step of performing lightly doped ion implantation in the method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a substrate placed on an ion implantation tray in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Wherein reference numerals are as follows: 100-a substrate; 101-a high voltage device region; 1011-a second source implant region; 1012-a second drain implant region; 102-a memory device region; 1021-a first source implant region; 1022-a first drain implant; a 110-high voltage gate structure, a 111-high voltage gate oxide layer; 112-high voltage gate; 112 a-a first portion of the high voltage gate; 112 b-a second portion of the high voltage gate; 113-a high voltage inter-gate dielectric layer; 120-control gate structure; 121-a floating gate oxide layer; 122-floating gate; 123-an inter-gate dielectric layer; 124-control gate; 130-select gate structure; 131-a select gate oxide; 132-select gates; 132 a-a first portion of the select gate; 132 b-a second portion of the select gate; 133-selecting an inter-gate dielectric layer; 140-patterning the photoresist layer; 140 a-a first opening; 140 b-a second opening; 140 c-a third opening; 200-ion implantation tray.
Detailed Description
The method for manufacturing the semiconductor device according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 is a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention. As shown in fig. 1, the present embodiment provides a method for manufacturing a semiconductor device, including: step S1: providing a substrate, wherein the substrate is provided with a high-voltage device region and a storage device region which are adjacent, a first source end injection region and a first drain end injection region are defined in the substrate of the storage device region, and a second source end injection region and a second drain end injection region are defined in the substrate of the high-voltage device region; step S2: forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer at least exposes the first drain end injection region, the second source end injection region and the second drain end injection region; and, step S3: and carrying out lightly doped ion implantation on the first drain end implantation region, the second source end implantation region and the second drain end implantation region by taking the patterned photoresist layer as a mask and a preset inclination angle, so that part of ions implanted into the first drain end implantation region are shielded by the patterned photoresist layer to form a shadow region on the first drain end implantation region, and the dose of ions implanted into the first drain end implantation region is smaller than that of ions implanted into the second source end implantation region or the second drain end implantation region by utilizing the shadow region.
Fig. 2 is a schematic cross-sectional view of the structure of a high-voltage device region and a memory device region in a method of manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 3 is a schematic cross-sectional view of a structure in a step of forming a patterned photoresist layer in a method of manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 4 is a schematic cross-sectional view of a structure in a step of performing lightly doped ion implantation in a method of manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 5 is a top view in a step of performing lightly doped ion implantation in the method of manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 6 is a schematic diagram of a substrate placed on an ion implantation tray in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
The method for manufacturing the semiconductor device according to the present embodiment will be described in more detail with reference to fig. 2 to 6.
Referring to fig. 2, in step S1, a substrate 100 is provided, the substrate 100 having a memory device region 102 and a high voltage device region 101 adjacent to each other, a first source implant region 1021 and a first drain implant region 1022 are defined in the substrate 100 of the memory device region 102, and a second source implant region 1011 and a second drain implant region 1012 are defined in the substrate 100 of the high voltage device region 101. The substrate 100 may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, and may be a die, or may be a wafer processed by an epitaxial growth process, and in detail, the substrate 100 may be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate 100 is a silicon substrate.
In this embodiment, the memory device region 102 is used to form a memory device, and the high-voltage device region 101 is used to form a high-voltage device. Specifically, a high-voltage device is used as a decoding area (address selector), and a memory device is used as a core unit for storing data. In this embodiment, the memory device formed in the memory device region 102 may be a P-type memory device.
In this embodiment, as shown in fig. 2, a high-voltage gate structure 110 is formed on the substrate 100 of the high-voltage device region 101, the high-voltage gate structure 110 includes a high-voltage gate oxide layer 111 and a high-voltage gate 112 located on the high-voltage gate oxide layer 111, and the second source-end injection region 1011 and the second drain-end injection region 1012 are respectively located in the substrate 100 of the high-voltage device region 101 at two sides of the high-voltage gate structure 110. The second source end implantation region 1011 is used to define an ion implantation region of the source region of the high voltage device region 101, and the second drain end implantation region 1012 is used to define an ion implantation region of the drain region of the high voltage device region 101. Specifically, the high-voltage gate 112 is formed by two parts, the second part 112b of the high-voltage gate is located on the first part 112a of the high-voltage gate, a part of a region between the first part 112a of the high-voltage gate and the second part 112b of the high-voltage gate has the high-voltage inter-gate dielectric layer 113, and the material of the high-voltage inter-gate dielectric layer 113 may be, for example, silicon oxide.
In this embodiment, the substrate 100 of the memory device region 102 is formed with a control gate structure 120 and a select gate structure 130 that are disposed at intervals, for example, the substrate 100 of the memory device region 102 may be formed with one control gate structure 120 and two select gate structures 130, and the two select gate structures 130 are disposed adjacently. The first source implant region 1021 and the first drain implant region 1022 are respectively located in the substrate 100 of the memory device region 102 on both sides of the select gate structure 130. The first source implantation region 1021 is used to define an ion implantation region of the source region of the memory device region 102, and the first drain implantation region 1022 is used to define an ion implantation region of the drain region of the memory device region 102.
As shown in fig. 2, the control gate structure 120 is used to form a control gate transistor, i.e., a cell for storing 0 or 1. The control gate structure 120 includes a floating gate oxide layer 121, a floating gate 122, an inter-gate dielectric layer 123, and a control gate 124, which are sequentially stacked from bottom to top.
The select gate structure 130 is used to form a select gate transistor through which selection during erase, program and read operations of the semiconductor device is accomplished. Wherein the select gate structure 130 includes a select gate oxide layer 131 and a select gate 132 on the select gate oxide layer 131. The selection gate 132 includes a first portion and a second portion, the second portion 132b of the selection gate is located on the first portion 132a of the selection gate, a partial area between the first portion 132a of the selection gate and the second portion 132b of the selection gate has a dielectric layer 133 between the selection gates, and the material of the dielectric layer 133 between the selection gates may be silicon oxide, for example.
As shown in fig. 3, in step S2, a patterned photoresist layer 140 is formed on the substrate 100, and the patterned photoresist layer 140 exposes at least the first drain implant region 1022, the second source implant region 1011, and the second drain implant region 1012. Specifically, the patterned photoresist layer 140 covers the high voltage gate structure 110 and the control gate structure 120. The patterned photoresist layer 140 also covers a portion of the select gate structure 130, that is, the patterned photoresist layer 140 exposes a portion of the select gate structure 130, that is, the boundary of the patterned photoresist layer 140 on the select gate structure 130 is located on the select gate structure 130, so as to be beneficial to blocking a portion of ions implanted into the first drain implant region 1022 during the subsequent lightly doped ion implantation of the first drain implant region 1022.
Further, the patterned photoresist layer 140 also covers a portion of the substrate 100 of the high-voltage device region 101 on a side of the second source-side injection region 1011 away from the high-voltage gate structure 110, and the patterned photoresist layer 140 also covers a portion of the substrate 100 of the high-voltage device region 101 on a side of the second source-side injection region 1011 away from the high-voltage gate structure 110, i.e., the patterned photoresist layer 140 also exposes a portion of the substrate 100 of the high-voltage device region 101 on a side of the second source-side injection region 1011 away from the high-voltage gate structure 110, and the patterned photoresist layer 140 also exposes a portion of the substrate 100 of the high-voltage device region 101 on a side of the second drain-side injection region 1012 away from the high-voltage gate structure 110. Wherein the portion of the substrate 100 of the high voltage device region 101 exposed by the patterned photoresist layer 140 is closer to the high voltage gate structure 110 than the portion covered by the patterned photoresist layer 140. That is, the boundary of the patterned photoresist layer 140 on the substrate 100 of the high voltage device region 101 has a certain distance from the second source injection region 1011 and the second drain injection region 1012, so that ions injected into the second source injection region 1011 and the second drain injection region 1012 are not blocked by the patterned photoresist layer 140 when the first drain injection region 1022, the second source injection region 1011 and the second drain injection region 1012 are subsequently lightly doped.
Further, as shown in fig. 3, the patterned photoresist layer 140 has a first opening 140a, a second opening 140b and a third opening 140c, where the first opening 140a exposes a portion of the substrate 100 of the high voltage device region 101 and the second source implant region 1011, the second opening 140b exposes a portion of the substrate 100 of the high voltage device region 101 and the second drain implant region 1012, and the third opening 140c exposes the first drain implant region 1022 and a portion of the select gate structure 130, wherein the widths of the first opening 140a and the second opening 140b may be the same, and the widths of the first opening 140a and the second opening 140b may be greater than the width of the third opening 140c, so that the ions implanted into the second source implant region 1011 and the second drain implant region 1012 may be prevented from being blocked by the patterned photoresist layer 140.
As shown in fig. 4, in step S3, the patterned photoresist layer 140 is used as a mask, and the first drain injection region 1022, the second source injection region 1011 and the second drain injection region 1012 are lightly doped with ions at a preset inclination angle α, so that a portion of the ions injected into the first drain injection region 1022 are blocked by the patterned photoresist layer 140 to form a shadow region on the first drain injection region 1022, and the shadow region is used to make the dose of the ions injected into the first drain injection region 1022 smaller than the dose of the ions injected into the second source injection region 1011 or the second drain injection region 1012. That is, when lightly doped ion implantation is performed by using the patterned photoresist layer 140 as a mask and using the predetermined tilt angle α, part of the ions implanted into the first drain implantation region 1022 are blocked by the patterned photoresist layer 140, so as to form a shadow region which cannot be reached by the lightly doped ion implantation of the predetermined tilt angle α, i.e., a shadow effect (shadow effect) is generated. In this way, the same patterned photoresist layer 140 is used as a mask, so that lightly doped ion implantation can be performed on the high-voltage device region 101 and the memory device region 102 at the same time, and the dose of ions implanted into the first drain end implantation region 1022 of the memory device region 102 is smaller than the dose of ions implanted into the second source end implantation region 1011 or the second drain end implantation region 1012 of the high-voltage device region 101, thereby saving a layer of mask, simplifying the process flow, ensuring the effective channel length of the memory device region 102, and avoiding channel leakage of the memory device region 102.
The purpose of lightly doped ion implantation of the first drain implantation region 1022 is to lightly dope the first drain implantation region 1022 to form a lightly doped drain region. The purpose of lightly doped ion implantation of the second source implant region 1011 and the second drain implant region 1012 is to form a first lightly doped region in the second source implant region 1011 and a second lightly doped region in the second drain implant region 1012, thereby adjusting the breakdown voltage (BV, breakdown voltage) of the high voltage device region 101 by the first lightly doped region and the second lightly doped region.
Specifically, the method for lightly doping ion implantation in the first drain implantation region 1022, the second source implantation region 1011, and the second drain implantation region 1012 at the preset inclination angle α includes: as shown in fig. 6, first, a substrate 100 having a patterned photoresist layer 140 is placed on an ion implantation tray 200 such that the substrate 100 is at a first predetermined position a. As shown in fig. 5, the first drain implantation region 1022, the second source implantation region 1011, and the second drain implantation region 1012 are subjected to a first lightly doped ion implantation at the predetermined inclination angle α. The irradiation direction of the ion beam a of the first lightly doped ion implantation is shown in fig. 5. Then, the substrate 100 is rotated in a clockwise direction to a second preset position B, and the first drain implantation region 1022, the second source implantation region 1011, and the second drain implantation region 1012 are subjected to a second lightly doped ion implantation at the preset tilt angle α. The irradiation direction of the ion beam b of the second lightly doped ion implantation is shown in fig. 5. Then, the substrate 100 is rotated clockwise to a third predetermined position C, and the first drain implantation region 1022, the second source implantation region 1011, and the second drain implantation region 1012 are subjected to a third lightly doped ion implantation at the predetermined tilt angle α. The irradiation direction of the ion beam c of the third lightly doped ion implantation is shown in fig. 5. Then, the substrate 100 is rotated clockwise to a fourth predetermined position D, and the first drain implantation region 1022, the second source implantation region 1011, and the second drain implantation region 1012 are subjected to a fourth lightly doped ion implantation at the predetermined tilt angle α. The irradiation direction of the ion beam d of the fourth lightly doped ion implantation is shown in fig. 5.
Further, the substrate 100 may be rotated to the first preset position a, the second preset position B, the third preset position C, and the fourth preset position D by rotating the ion implantation tray 200. The first preset position a, the second preset position B, the third preset position C and the fourth preset position D are the same in angle, for example, the first preset position a, the second preset position B, the third preset position C and the fourth preset position D may be 90 °.
In this embodiment, the first lightly doped ion implantation, the second lightly doped ion implantation, the third lightly doped ion implantation, and the fourth lightly doped ion implantation have the same dose. I.e., the total dose of ions that are lightly doped ions implanted into the first drain implant region 1022, the second source implant region 1011, or the second drain implant region 1012 is divided into four implants. Further, ions of the first lightly doped ion implantation, the second lightly doped ion implantation, the third lightly doped ion implantation, and the fourth lightly doped ion implantation, which are two times of lightly doped ion implantation into the first drain implant region 1022, are blocked by the patterned photoresist layer 140. For example, as shown in fig. 4, the ions in the ion beam a of the first ion implantation and the ions in the ion beam c of the third ion implantation are blocked by the patterned photoresist layer 140 so that the total dose of the ions implanted into the first drain implantation region 1022 is not more than one half of the total dose of the ions implanted into the second source implantation region 1011 or the second drain implantation region 1012. In this way, not only the breakdown voltage of the high-voltage device region 101 can be regulated, but also the effective channel length of the memory device region 102 can be ensured, and the channel leakage of the memory device region 102 can be avoided.
In this embodiment, the preset inclination angle α is an angle between the ion beam and a plane perpendicular to the substrate 100, and the preset inclination angle α may be 30 ° to 45 °, for example, may be 30 °, 35 °, 40 °, or 45 °. Preferably, the preset inclination angle α in this embodiment is 45 ° so as to maximize the breakdown voltage of the high-voltage device region 101 after the lightly doped ion implantation.
In this embodiment, the type of the ion implanted by the lightly doped ion is P-type ion, such as boron ion, gallium ion or indium ion. The energy of the lightly doped ion implantation is 20 Kev-30 Kev, and the total dosage of the lightly doped ion implantation is 2E11/cm 2 ~4E11/cm 2 。
Further, the semiconductor device in this embodiment may be an embedded flash memory.
In summary, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, by lightly doping the first drain injection region of the memory device region and the second source injection region and the second drain injection region of the high voltage device region at a predetermined inclination angle, a portion of ions injected into the first drain injection region may be blocked by the patterned photoresist layer to form a shadow region on the first drain injection region, and the dose of ions injected into the first drain injection region may be smaller than the dose of ions injected into the second source injection region or the second drain injection region by using the shadow region. Therefore, the same patterned photoresist layer can be used as a mask, light doped ion implantation is carried out on the high-voltage device region and the storage device region, and the dosage of ions implanted into the first drain end implantation region of the storage device region is smaller than that of ions implanted into the second source end implantation region or the second drain end implantation region of the high-voltage device region, so that one layer of mask can be saved, the process flow is simplified, the effective channel length of the storage device region is ensured, and the channel leakage of the storage device region is avoided.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate is provided with a high-voltage device region and a storage device region which are adjacent, a first source end injection region and a first drain end injection region are defined in the substrate of the storage device region, and a second source end injection region and a second drain end injection region are defined in the substrate of the high-voltage device region;
forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer at least exposes the first drain end injection region, the second source end injection region and the second drain end injection region; the method comprises the steps of,
and carrying out lightly doped ion implantation on the first drain end implantation region, the second source end implantation region and the second drain end implantation region by taking the patterned photoresist layer as a mask and a preset inclination angle, so that part of ions implanted into the first drain end implantation region are shielded by the patterned photoresist layer to form a shadow region on the first drain end implantation region, and the dose of ions implanted into the first drain end implantation region is smaller than that of ions implanted into the second source end implantation region or the second drain end implantation region by utilizing the shadow region.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the predetermined inclination angle is an angle between an ion beam and a plane perpendicular to the substrate, and the predetermined inclination angle is 30 ° to 45 °.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the lightly doping ion implantation of the first drain implant region, the second source implant region, and the second drain implant region at a predetermined tilt angle comprises:
placing a substrate with a patterned photoresist layer on an ion implantation tray, so that the substrate is positioned at a first preset position, and performing first lightly doped ion implantation on the first drain end implantation region, the second source end implantation region and the second drain end implantation region at the preset inclination angle;
rotating the substrate to a second preset position along the clockwise direction, and carrying out second lightly doped ion implantation on the first drain end implantation region, the second source end implantation region and the second drain end implantation region at the preset inclination angle;
rotating the substrate to a third preset position along the clockwise direction, and carrying out third lightly doped ion implantation on the first drain end implantation region, the second source end implantation region and the second drain end implantation region at the preset inclination angle; the method comprises the steps of,
rotating the substrate to a fourth preset position along the clockwise direction, and carrying out fourth lightly doped ion implantation on the first drain end implantation region, the second source end implantation region and the second drain end implantation region at the preset inclination angle;
wherein the first lightly doped ion implantation, the second lightly doped ion implantation, the third lightly doped ion implantation and the fourth lightly doped ion implantation have the same dosage.
4. The method for manufacturing a semiconductor device according to claim 3, wherein a total dose of ions injected into the first drain injection region is not more than one half of a total dose of ions injected into the second source injection region or the second drain injection region when lightly doping the first drain injection region, the second source injection region, and the second drain injection region.
5. The method of manufacturing a semiconductor device according to claim 3, wherein ions of the first lightly doped ion implantation, the second lightly doped ion implantation, the third lightly doped ion implantation, and the fourth lightly doped ion implantation, which are two times lightly doped ions implanted into the first drain implant region, are blocked by the patterned photoresist layer.
6. The method for manufacturing a semiconductor device according to claim 3, wherein an angle of a space between the first preset position, the second preset position, the third preset position, and the fourth preset position is the same.
7. The method of manufacturing a semiconductor device according to claim 1, wherein a high-voltage gate structure is formed on the substrate of the high-voltage device region, and the second source-side injection region and the second drain-side injection region are respectively located in the substrate of the high-voltage device region on both sides of the high-voltage gate structure; and a control gate structure and a selection gate structure which are arranged at intervals are formed on the substrate of the storage device region, and the first source end injection region and the first drain end injection region are respectively positioned in the substrates of the storage device regions at two sides of the selection gate structure.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the high-voltage gate structure includes a high-voltage gate oxide layer and a high-voltage gate on the high-voltage gate oxide layer.
9. The method of manufacturing a semiconductor device according to claim 7, wherein the control gate structure comprises a floating gate oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate, which are sequentially stacked from bottom to top; the select gate structure includes a select gate oxide layer and a select gate on the select gate oxide layer.
10. The method of manufacturing a semiconductor device of claim 7, wherein when a patterned photoresist layer is formed on the substrate, the patterned photoresist layer covers the first source side implant region, the high voltage gate structure, the control gate structure, a portion of the select gate structure, and a portion of the substrate of the high voltage device region, and the patterned photoresist layer also exposes a portion of the select gate structure, a portion of the substrate of the high voltage device region on a side of the second source side implant region remote from the high voltage gate structure, and a portion of the substrate of the high voltage device region on a side of the second drain side implant region remote from the high voltage gate structure, wherein the portion of the substrate of the high voltage device region exposed by the patterned photoresist layer is closer to the high voltage gate structure than the portion covered by the patterned photoresist layer.
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