JP4833527B2 - Insulated gate semiconductor device and driving method thereof - Google Patents

Description

  The present invention relates to an insulated gate semiconductor device and a driving method thereof, and in particular, an insulation characteristic of a source / drain structure for realizing high drive current and low power consumption in an insulated gate field effect semiconductor device. The present invention relates to a gate type semiconductor device and a driving method thereof.

In recent years, there has been a demand for MOSFETs with high drive current and miniaturization, and in order to achieve high drive current, subthreshold leakage or off-leakage I _off , that is, drain current I _ds when the gate voltage is 0V ( At V _g = 0V), the control is difficult.
On the other hand, there is a strong demand for low power consumption. However, since high drive current hinders low power consumption, it is difficult to achieve both.

In order to realize this coexistence, it has been proposed to control the _off- leakage I _off by arbitrarily changing the threshold value V _th without changing the impurity concentration in the semiconductor substrate using the substrate bias effect ( For example, refer nonpatent literature 1).

  In order to achieve a high driving current of the MOSFET, it is necessary to increase the impurity concentration of the source / drain extension, but in order to achieve miniaturization at the same time, it is necessary to shorten the channel length L.

  When the channel length L is shortened, the short channel effect becomes prominent so that the number of carriers that can be controlled by the gate electrode is reduced, and the substrate bias described above is strongly influenced by the space charge (depletion layer) of the source region and the drain region. Since the effect is less likely to occur, this situation will be described with reference to FIGS.

See FIG.
FIG. 21 is a conceptual cross-sectional view of a MOSFET having a gate length of about 43 to 45 nm, and schematically shows the substrate bias V _b dependency of the channel charge region 48, that is, a region where carriers that can be controlled by the gate voltage are present. Here, for an n-channel MOSFET, a case where V _b = 0V is indicated by a broken line, a case where V _b = −2 V is indicated by a one-dot chain line, and a case where V _b = −4 V is indicated by a two-dot chain line. Yes.
As can be seen from the figure, as the substrate bias V _b is increased, the channel charge region 48 is expanded, and the substrate bias effect is effectively generated.

See FIG.
FIG. 22 is a conceptual cross-sectional view of a MOSFET having a gate length of about 38 to 40 nm, and schematically shows the substrate bias V _b dependency of the channel charge region 58. , V _b = 0V is indicated by a broken line, V _b = −2 V is indicated by a one-dot chain line, and V _b = −4 V is indicated by a two-dot chain line.
As is apparent from the figure, the channel charge region 58 hardly expands even when the substrate bias _Vb is deepened, and the substrate bias effect is less likely to occur.

See FIG.
FIG. 23 is an IV characteristic diagram of an n-channel MOSFET having a gate length L _g = 40 nm. A solid line indicates an IV characteristic of V _d / V _b = 1V / 0V, and V _d / V _b = 1V. The IV characteristic of −4V is shown, and it was confirmed that even when the substrate bias was actually applied at −4V, the off-leakage I _off and the threshold value _Vth were hardly changed.
Here, in order to see the substrate bias effect, I _off of I _off / drive time when I _off ratio = wait as described above the I _off ratio
In this case, in FIG. 23, I _off ratio = 21.9%.

See FIG.
FIG. 24 is an IV characteristic diagram of a p-channel MOSFET having a gate length L _g = 40 nm formed in the same manner. A solid line indicates an IV characteristic of V _d / V _b = −1 V / 0 V, and V _d This shows the IV characteristic of / V _b = -1V / 4V, and it was confirmed that even when the substrate bias was actually applied 4V, the off-leakage I _off and the threshold value V _th were hardly changed. .
In this case, _Ioff ratio = 30.3%.

Therefore, normally, a channel doping step for adjusting the threshold is used slightly above the shaded portion 59 in FIG. 22 to dope impurities higher in concentration than normal channel doping, or It has been proposed that additional channel implantation is performed in the shaded portion 59 in a separate process from doping to reduce the influence of space charge (depletion layer) (see, for example, Patent Document 1).
2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 88-89, 2004 JP 11-354785 A

However, although the method according to Patent Document 1 described above is effective for substrate bias dependence, it is performed in addition to channel doping for threshold adjustment, or instead of channel doping. Since there is a problem that an arbitrary threshold value V _th cannot be obtained, this situation will be described with reference to FIGS. 25 and 26.

See FIG.
FIG. 25 is an IV characteristic diagram when an additional channel is implanted into an n-channel MOSFET having a gate length L _g = 40 nm. A solid line indicates an IV characteristic of V _d / V _b = 1 V / 0 V, and V _The IV characteristic of _d / V _b = 1V / −4V is shown, and it can be seen that V _th greatly changes due to the substrate bias.
Further, as is apparent from the figure, the off-leakage I _off is greatly increased, and the power consumption is reduced, and the I _off ratio is 118.2%.

Furthermore, since the additional channel implantation naturally affects the impurity concentration of the channel portion, the mobility and the driving current are also affected and deteriorated.
In addition, since the substrate impurity concentration becomes high, there is a concern about an increase in junction leakage current (GIDL) and junction capacitance, which introduces a substrate bias effect in order to control _off- leakage I _off without changing the substrate impurity concentration. It will contradict the purpose.

See FIG.
FIG. 26 is an IV characteristic diagram when an additional channel is implanted into a p-channel MOSFET having a gate length L _g = 40 nm, and a solid line indicates an IV characteristic of V _d / V _b = −1 V / 0 V, shows the the I-V characteristic of _{V d / V b = -1V /} 4V, it can be seen that V _th by the substrate bias is changed significantly.
Also in this case, the off-leakage I _off is significantly increased, will be counter to lower power consumption, I _off ratio becomes 306.3%, the off-leak I _off than n-channel MOSFET shown in FIG. 25 Will increase.

  On the other hand, in order to realize a high drive current and miniaturization, the present applicant provides an intermediate region doped with a diffusion control element between the source / drain extension region and the source / drain region to form a triple source / drain. A structure is proposed (for example, see Japanese Patent Application No. 2003-373499).

However, even in the above-mentioned proposal, no investigation has been made on the substrate bias effect for reducing the _off- leakage I _off .

Accordingly, an object of the present invention is to realize low power consumption by reducing _off- leakage I _off by the substrate bias effect even in a high drive current and miniaturized structure.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
In the figure, reference numeral 2 denotes a gate insulating film.
In order to solve the above-described problems, the present invention provides a semiconductor substrate 1, a channel region formed in the semiconductor substrate 1, and a gate insulating film formed on the channel region in an insulated gate semiconductor device. 2, a gate electrode 3 formed on the gate insulating film 2, a first sidewall having a width of 3 nm to 20 nm formed on the sidewall of the gate electrode 3, and the first sidewall 4. A second sidewall 5 having a width of 30 nm to 60 nm, a third sidewall 6 formed on the second sidewall 5, and the semiconductor substrate under the first sidewall 4. and Aix Ten Deployment region 7 formed in 1, is formed on the semiconductor substrate 1 under the second side wall 5, and a deep buffer territory than the extension region 7 A region 8 and a source region and a drain region formed in the semiconductor substrate 1 below the third sidewall 6 and deeper than the buffer region 8, and the source region and the drain region have a symmetrical structure. The buffer region 8 on the source region side and the buffer layer 8 on the drain region side have a symmetrical structure, and the extension region 7 on the source region side and the extension region 7 on the drain region side have a symmetrical structure, A negative voltage is applied to the channel region when the channel region is n-type, and a positive voltage is applied to the channel region when the channel region is p-type. To do.

As a result of diligent research, the present inventor has found that the width of the intermediate region, that is, the buffer layer in the above-mentioned triple source / drain structure MOSFET is self-aligned with the second sidewall 5 of 30 nm to 60 nm. The present inventors have found that the substrate bias effect can be effectively exhibited.
In this case, by providing the first sidewall 4 having a width of 3 to 20 nm, the effect of space charge can be reduced and the substrate bias effect can be more effectively exhibited.

  In this case, the angle formed by the lower end of the outer wall surface of the third sidewall 6 and the main surface of the semiconductor substrate 1 may be 60 ° or less, whereby the end portion of the deep junction source / drain region 9 is formed. Since the shape becomes smooth, the boundary with the buffer region 8 is fused, the parasitic resistance is reduced, and the on-current can be increased.

  The second sidewall 5 and the third sidewall 6 are preferably composed of a low-temperature oxide film that can be formed at a low temperature of 550 ° C. or less, and thereby the thermal process associated with the sidewall formation process. The lateral diffusion of the extension region 7 can be reduced. In particular, when the first sidewall 4 is provided and the offset region is formed in advance, the end of the final extension region 7 and the end of the gate electrode 3 can be substantially matched.

  Further, according to the present invention, in an insulated gate semiconductor device, the extension region 7 has a length that is self-aligned with a sidewall having a width of 30 nm to 60 nm between the extension region 7 and the deep junction source / drain region 9, and the extension region 7 A buffer region 8 having a depth intermediate between the deep junction source / drain regions 9 is provided to make the source / drain structure a triple structure, and a substrate bias applying means 10 for applying a substrate bias different from at least 0 V is provided. It is characterized by that.

  As described above, the present inventor, as a result of earnest research, the intermediate region in the triple source / drain structure MOSFET, that is, when the buffer layer has a width that self-aligns with a sidewall having a width of 30 nm to 60 nm, It has been discovered that the substrate bias effect can be effectively exhibited.

In this case, by applying a substrate bias different from 0 V during standby, the subthreshold can be reduced and the off-leakage current I _off can be reduced.
Further, a substrate bias other than 0 V may be applied during driving as in standby.

  Alternatively, a first substrate bias including 0 V may be applied during driving, and a second substrate bias that is larger in absolute value than the first substrate bias may be applied during standby. Both drive current and low power consumption can be achieved.

The above-described configuration is effective in an insulated gate semiconductor device having a gate length L _g of 0.1 μm or less, particularly 40 nm or less. In this case, the drain voltage is typically 1 V or less, and is in a standby state. The substrate bias may be 0.1 V or higher in absolute value.

  According to the present invention, a substrate bias effect can be effectively exhibited in a fine high drive current insulated gate semiconductor device by providing a buffer region having a length that is self-aligned to a sidewall having a width of 30 nm to 60 nm. It is possible to achieve both high drive current and low power consumption.

  The present invention provides a sidewall having a width of 30 nm to 60 nm, that is, a buffer layer and a sidewall on the outer side thereof, and has a length that is self-aligned with the buffer layer immediately below the buffer layer. A buffer region having a depth in the middle of the drain region is provided to make the source / drain structure a triple structure, and a substrate bias of 0.1 V or more, for example, 2 to 6 V in absolute value is applied during standby. .

  In addition, when forming the extension region, an offset region is formed in advance by providing a sidewall having a width of 3 to 20 nm, and the end of the extension region and the end of the gate electrode are almost formed by a final heat treatment process. They may be matched.

Here, the manufacturing process of the CMOS type semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 2 to 11. However, since the CMOS is not essential, only the n-channel type MOSFET is illustrated. The p-channel MOSFET is not shown.
See Figure 2
First, an element isolation insulating layer 12 having, for example, an STI (Shallow Trench Isolation) structure is formed on a p-type silicon substrate 11, and then B is ion-implanted into a region where an n-channel MOSFET is to be formed to form a p-type well region 13. Then, As is ion-implanted in the region where the p-channel MOSFET is to be formed to form an n-type well region.

Next, after channel implantation is performed in the p-type well region 13 at a dose of 0.1 to ² × 10 ¹³ cm ⁻² at an acceleration energy of 5 to 20 KeV, for example, an acceleration energy of 35 to 180 KeV is used for In. Then, additional channel implantation is performed at a dose of 0.1 to 5 × 10 ¹³ cm ⁻² .

On the other hand, in the n-type well region, for example, As is channel-implanted with an acceleration energy of 70 to 180 KeV and a dose of 0.1 to ² × 10 ¹³ cm ⁻² , and then As is accelerated to an energy of 100 to 230 KeV. Then, additional channel implantation is performed at a dose of 0.1 to 5 × 10 ¹³ cm ⁻² .

See Figure 3
Next, after forming a gate insulating film made of a silicon oxynitride film having a thickness of, for example, 0.7 to 1.5 nm as a physical film thickness using the plasma CVD method, the plasma CVD method is used over the entire surface. A polycrystalline silicon film having a thickness of 50 to 150 nm is sequentially deposited and then patterned to form a gate electrode 15 and a gate insulating film 14 having a gate length of 38 nm to 40 nm, for example, 40 nm.

Next, referring to FIG. 4, a silicon oxide film having a thickness of 3 to 20 nm, for example, 10 nm is deposited at 580 ° C. by using a low pressure CVD method using TEOS (tetraethoxysilane) on the entire surface. By performing etching, the sidewall 16 for offset is formed on the sidewall of the gate structure.
At this time, the thickness of the sidewall 16 is substantially the same as the thickness of the formed silicon oxide film.

Next, after covering the n-type well region with a photoresist, for example, In is implanted from four directions at a dose of 0.1 to 3 × 10 ¹³ cm ⁻² at an acceleration energy of 30 to 100 KeV. Pocket region 17 is formed, and then n-type extension region 18 is formed by implanting As at a dose of 0.5 to 5 × 10 ¹⁵ cm ⁻² at an acceleration energy of 0.5 to 10 KeV.

Next, after removing the photoresist, the p-type well region 13 is covered with a new photoresist, and then, for example, As is applied at an acceleration energy of 40 to 90 KeV and a dose of 0.1 to 3 × 10 ¹³ cm ^−2. After forming a pocket region by implanting from four directions, a p-type extension region is formed by implanting B at a dose of 0.5 to 5 × 10 ¹⁵ cm ⁻² at an acceleration energy of 0.1 to 5 KeV. To do.

Next, after removing the photoresist, by a low pressure CVD method using BTBAS (Bis Tertiary-Butylamino Silene) and O ₂ as raw materials, at a temperature of 500 ° C. to 580 ° C., preferably 550 ° C. or less, After a silicon oxide film having a thickness of 30 to 60 nm is deposited on the entire surface, anisotropic etching is performed to form the second sidewall, that is, the buffer layer 19.
At this time, the thickness of the buffer layer 19 is substantially the same as the thickness of the formed silicon oxide film.

Next, after covering the n-type well region with a photoresist, for example, As is implanted at an acceleration energy of 1 to ¹⁵ KeV at a dose of 0.1 to 4 × 10 ¹⁵ cm ^−2. Region 20 is formed.

Next, after removing the photoresist, the p-type well region 13 is covered with a new photoresist, and then, for example, B is dosed at 0.1 to 4 × 10 ¹⁵ cm ⁻² at an acceleration energy of 0.1 to 7 KeV. A p-type buffer region is formed by implanting in an amount.

Next, after removing the photoresist, the thickness of the entire surface is reduced by a low pressure CVD method using BTBAS and O ₂ as raw materials at a temperature of 500 ° C. to 580 ° C., preferably 550 ° C. or less. After depositing a silicon oxide film of 50 to 100 nm, for example, 90 nm, the sidewall 21 is formed by performing anisotropic etching.
At this time, the skirting structure is such that the angle formed by the lower end of the outer surface of the sidewall 21 with respect to the main surface of the substrate is 60 ° or less.

Next, after covering the n-type well region with a photoresist, for example, P is implanted at an acceleration energy of 2 to 25 KeV at a dose of 0.1 to 5 × 10 ¹⁶ cm ^−2. -The drain region 22 is formed.
At this time, since the angle formed by the lower end of the outer surface of the sidewall 21 with respect to the main surface of the substrate is 60 ° or less, the end shape of the n-type source / drain region 22 becomes smooth, and the n-type buffer The boundary with the region 20 is fused, the parasitic resistance is reduced, and the on-current can be increased.

Next, after removing the photoresist, the p-type well region 13 is covered with a new photoresist, and then, for example, B is dosed at 0.1 to 5 × 10 ¹⁶ cm ⁻² at an acceleration energy of 0.1 to 10 KeV. A p-type source / drain region is formed by implanting in an amount.

See FIG. 10 Next, spike impurity ions are activated by performing spike annealing at a temperature of 800 to 1200 ° C. in a nitrogen atmosphere.
At this time, the impurity is laterally diffused in the ion implantation region such as the n-type extension region 18, the end of the n-type extension region 18 substantially coincides with the end of the gate electrode 15, and the offset region disappears.

Next, after a Co film is deposited on the entire surface, silicidation is performed by heat treatment to form a Co silicide layer 23 made of CoSi _{2 on} the exposed surfaces of the n-type source / drain regions 22 and the p-type source / drain regions. Then, the unreacted Co film (not shown) is removed.

  Thereafter, although not shown in the figure, a CMOS type semiconductor is formed by repeating a process for forming an interlayer insulating film, a process for forming a via, a process for depositing a conductive film, a process for patterning a conductive film, etc. The basic configuration of the device is completed.

FIG. 12 to FIG. 14 are IV characteristic diagrams in the case where the buffer layer of the n-channel MOSFET in which the offset sidewall is not formed and the additional channel implantation is not performed is 30 nm, and the solid line is _{V d / V b = 1V /} 0V of shows the characteristics at the time of driving, the broken line shows the characteristics at the time of waiting for _{V d / V b = 0.6V /} -4V.

Here, in order to see the substrate bias effect, I _off of I _off / drive time when I _off ratio = wait as described above the I _off ratio
In FIG. 12, I _off ratio = 12.0%, and the effect of providing the buffer layer begins to appear.

FIG. 13 is an IV characteristic diagram during driving and standby when the thickness of the buffer layer in the MOSFET of Example 1 is 40 nm. In this case, the I _off ratio is 2.7%. A significant improvement effect was obtained.

FIG. 14 is a diagram of IV characteristics during driving and standby when the thickness of the buffer layer in the MOSFET of Example 1 is 50 nm. In this case, I _off ratio = 1.9%. The improvement effect was obtained compared with the case where the buffer layer was 40 nm.

FIG. 15 to FIG. 17 are IV characteristic diagrams in the case where the buffer layer of the p-channel MOSFET in which the offset sidewall is not formed and the additional channel implantation is not performed is 30 nm, and the solid line is _{V d / V b = -1V /} 0V of shows the characteristics at the time of driving, the dashed line are those showing characteristics during standby of _{V d / V b = -0.6V /} 4V, even if the p-type MOSFET , I _off ratio = 11.9, providing a buffer layer and the effect begins to appear.

FIG. 16 is an IV characteristic diagram for driving and standby when the thickness of the buffer layer in the MOSFET of Example 1 is 40 nm. In this case, I _off ratio = 1.6%. A significant improvement effect was obtained.

FIG. 17 is an IV characteristic diagram during driving and standby when the thickness of the buffer layer in the MOSFET of Example 1 is 50 nm. In this case, I _off ratio = 1.3%. The improvement effect was obtained compared with the case where the buffer layer was 40 nm.

As described above, in Example 1 of the present invention, the buffer layer having a width of 30 nm to 60 nm is provided, and is self-aligned with the buffer layer immediately below, and has a depth intermediate between the extension region and the source / drain region. Since the buffer region is provided, the I _off ratio can be made small while maintaining a high driving current, that is, the standby I _off can be controlled by the substrate bias, and the standby power consumption can be reduced. .

  In the first embodiment, when the extension region is formed, the offset sidewall is provided to form the offset. Therefore, in the spike annealing process, the overlap with the gate electrode is undesirably caused by lateral diffusion. Since it is not increased, the short channel effect can be reduced and the parasitic capacitance can be reduced.

  Next, with reference to FIG. 18, the manufacturing process of the CMOS type semiconductor device according to the second embodiment of the present invention will be described. Basically, the offset sidewall is not formed when the extension region is formed. Since this is the same as the first embodiment, only the final structure is illustrated, and differences from the first embodiment will be described.

See FIG. 18. After forming the extension region of FIG. 5 in Example 1 above, the n-type well region is covered with a photoresist without forming the offset sidewall, and then, for example, In is accelerated by 25 to 95 KeV. The pocket region 31 is formed by implanting from four directions at a dose of 0.1 to 3 × 10 ¹³ cm ⁻² with energy, and then As is 0.5 to 4 with an acceleration energy of 0.5 to 10 KeV. The n-type extension region 32 is formed by implanting from four directions at a dose of 5 × 10 ¹⁵ cm ⁻² .

Next, after removing the photoresist, the p-type well region 13 is covered with a new photoresist, and then, for example, As is applied at an acceleration energy of 30 to 80 KeV and a dose of 0.1 to 3 × 10 ¹³ cm ^−2. After forming the pocket region by implanting from 4 directions, B is implanted from 4 directions at a dose of 0.5 to 4.5 × 10 ¹⁵ cm ⁻² with an acceleration energy of 0.1 to 5 KeV. A mold extension region is formed.

  Thereafter, the same process as in the first embodiment is performed to obtain the basic structure of the CMOS semiconductor device shown in FIG.

FIG. 19 is an IV characteristic diagram at the time of driving and standby when the thickness of the buffer layer in the n-channel MOSFET of Example 2 is 40 nm. In this case as well, the I _off ratio = 3. A significant improvement effect was obtained at 4%.
However, the characteristics are slightly inferior to those of Example 1 employing the offset structure.
The applied voltage during driving and standby is the same as that in the first embodiment.

FIG. 20 is an IV characteristic diagram during driving and standby when the thickness of the buffer layer in the p-channel MOSFET of Example 2 is 40 nm. In this case as well, I _off ratio = 1. 9%, a significant improvement effect was obtained.
However, the characteristics of the p-type MOSFET are slightly inferior to those of the first embodiment that employs the offset structure, as in the case of the n-type MOSFET.

  As described above, also in the second embodiment of the present invention, the same effect as in the first embodiment can be obtained by providing the buffer area.

Each embodiment of the present invention has been described above, but the present invention is not limited to the configuration and conditions described in each embodiment, and various changes can be made to the dose, acceleration energy, material, impurity species, and the like. It is.
For example, in each of the above embodiments, the buffer layer is made of BTBAS. However, the buffer layer is not limited to BTBAS, and may be formed at a low temperature. For example, TEOS may be used.

  In each of the above embodiments, each of the lower end of the outer side wall of the outer side wall with respect to the main surface of the substrate is set to 60 ° or less, but it may be a substantially vertical side wall as in the case of a normal side wall. good.

  In each of the above embodiments, As is used when forming the n-type buffer layer and P is used when forming the n-type source / drain regions. As may be used when forming n-type source / drain regions using Sb.

  In each of the above embodiments, the silicide layer is provided using Co. However, the present invention is not limited to Co, and a silicide layer made of NiSi may be formed using Ni.

Further, in the above-mentioned embodiments, although a silicon oxynitride film as a gate insulating film, not limited to a silicon oxynitride film, SiO ₂ film, Si ₃ N ₄ film, or, Ta ₂ O ₅ A high dielectric constant film such as a film may be used, and further, a multilayer structure film of these may be used.

  In each of the above embodiments, a silicon substrate is used. However, the present invention is not limited to a silicon substrate. An SiGe substrate having an arbitrary composition ratio or a SiGe epitaxial layer having an arbitrary composition ratio is provided on a silicon substrate. Further, an SiGe epitaxial layer having an arbitrary composition ratio is provided on a part of the silicon substrate, an n-channel MOSFET is formed on the silicon substrate side, and a p-type MOSFET is formed on the SiGe epitaxial layer side. A channel-type MOSFET may be provided to improve the balance of operation speed.

  In each of the above embodiments, the CMOS type semiconductor device has been described. However, the present invention is not limited to the CMOS type semiconductor device, but can be applied to a single n-channel MOSFET or a single p-channel MOSFET. Is.

  Further, in each of the above embodiments, the additional channel implantation and the pocket implantation are performed, but the additional channel implantation and the pocket implantation are not essential, and only one of them may be performed, and further, both may not be performed. Is.

In each of the above embodiments, the absolute value of the drain voltage V _d at the time of driving is set to 1 V. However, the drain voltage V _d is arbitrary and may be 1 V or more. It is desirable to drive.

In each of the above embodiments, the absolute value of the drain voltage V _d during standby is set to 0.6 V. However, the drain voltage V _d is arbitrary, and other than 0 V, 0.2 V, 0.4 V, etc. The voltage may be adopted.

In each of the above embodiments, the absolute value of the substrate bias V _b during standby is 4 V. However, the absolute value of the substrate bias V _b is arbitrary, and may be at least 0.1 V or more other than 0 V. .

In each of the embodiments described above, the substrate bias _Vb during driving is set to 0 V, but is not limited to 0 V, and an arbitrary voltage may be applied. A potential substrate bias may be applied.

  In each of the above embodiments, the gate length is set to 38 to 40 nm. However, the gate length is arbitrary, and it is effective when the gate length is 40 nm or more, but the substrate bias effect becomes more prominent when it is 38 nm or less. Become.

Here, the detailed configuration of the present invention will be described again with reference to FIG.
Again see Figure 1
(Supplementary note 1) a semiconductor substrate 1, a channel region formed in the semiconductor substrate 1, a gate insulating film 2 formed on the channel region, a gate electrode 3 formed on the gate insulating film 2, A first sidewall having a width of 3 nm to 20 nm, a second sidewall 5 having a width of 30 nm to 60 nm, formed on the sidewall of the gate electrode 3; a third side wall 6 formed on the second side wall 5, and Aix Ten Deployment region 7 formed in the semiconductor substrate 1 below the first sidewall 4, the second sidewall 5 is formed on the semiconductor substrate 1 below the extension region 7, and is formed on the semiconductor substrate 1 below the third sidewall 6 and the buffer region 8 deeper than the extension region 7. Serial and a deep source region and the drain region than the buffer region 8, the a the drain region and the symmetrical structure as the source region, and the source region side buffer region 8 and the drain region side of the buffer layer 8 is When the extension region 7 on the source region side and the extension region 7 on the drain region side have a symmetrical structure and the channel region is n-type, a negative voltage is applied to the channel region. When the channel region is p-type, a positive voltage is applied to the channel region.
(Supplementary note 2) The insulated gate semiconductor device according to supplementary note 1, wherein an angle formed between a lower end of an outer wall surface of the third sidewall 6 and a main surface of the semiconductor substrate 1 is 60 ° or less.
(Appendix 3) The insulated gate according to appendix 1 or appendix 2, wherein the second sidewall 5 and the third sidewall 6 are made of a low-temperature oxide film that can be formed at a low temperature of 550 ° C. or less. Type semiconductor device.
(Appendix 4 ) In the insulated gate semiconductor device according to any one of appendices 1 to 3, a first substrate for applying a first bias potential to the channel region when the insulated gate semiconductor device is driven Insulation comprising bias application means and second substrate bias application means for applying a second bias potential that is larger in absolute value than the first bias potential during standby of the insulated gate semiconductor device Gate type semiconductor device.
(Supplementary Note 5 ) In the method for driving an insulated gate semiconductor device according to any one of supplementary notes 1 to 4, the drain voltage is set to 1 V or less, and the substrate bias during standby of the insulated gate semiconductor device is an absolute value. The method for driving an insulated gate semiconductor device, wherein the voltage is 0.1 V or higher.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the manufacturing process to the middle of the CMOS type semiconductor device of Example 1 of this invention. It is explanatory drawing of the manufacturing process until the middle of FIG. 2 or later of the CMOS type semiconductor device of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 3 of the CMOS type semiconductor device of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 4 of the CMOS type semiconductor device of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 5 of the CMOS type semiconductor device of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 6 of the CMOS type semiconductor device of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 7 of the CMOS type semiconductor device of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 8 of the CMOS type semiconductor device of Example 1 of this invention. It is explanatory drawing of the manufacturing process until the middle of FIG. 9 or later of the CMOS type semiconductor device of Example 1 of this invention. FIG. 11 is an explanatory diagram of the manufacturing process of FIG. 10 and subsequent drawings of the CMOS type semiconductor device of Example 1 of the present invention. FIG. 5 is an IV characteristic diagram of an n-channel MOSFET in which a buffer layer has a thickness of 30 nm. It is an IV characteristic view when the buffer layer in the n-channel MOSFET of Example 1 of the present invention is 40 nm. It is an IV characteristic view when the buffer layer in the n-channel MOSFET of Example 1 of the present invention is 50 nm. FIG. 5 is an IV characteristic diagram of a p-channel MOSFET with a buffer layer thickness of 30 nm. FIG. 6 is an IV characteristic diagram when the buffer layer in the p-channel MOSFET of Example 1 of the present invention is 40 nm. It is an IV characteristic view when the buffer layer in the p-channel MOSFET of Example 1 of the present invention is 50 nm. It is a schematic sectional drawing of n channel type MOSFET which constitutes a CMOS type semiconductor device of Example 2 of the present invention. It is an IV characteristic view when the buffer layer in the n-channel MOSFET of Example 2 of the present invention is 40 nm. It is an IV characteristic diagram when the buffer layer in the p-channel MOSFET of Example 2 of the present invention is 40 nm. It is a conceptual sectional view of a conventional n-channel MOSFET having a gate length of about 43 to 45 nm. It is a conceptual sectional view of a conventional n-channel MOSFET having a gate length of about 38 to 40 nm. FIG. 10 is an IV characteristic diagram of a conventional n-channel MOSFET having a gate length L _g = 40 nm. It is an IV characteristic view of a conventional p-channel MOSFET having a gate length L _g = 40 nm. FIG. 10 is an IV characteristic diagram when an additional channel is implanted into a conventional n-channel MOSFET having a gate length L _g = 40 nm. FIG. 6 is an IV characteristic diagram when an additional channel is implanted into a conventional p-channel MOSFET having a gate length L _g = 40 nm.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate insulating film 3 Gate electrode 4 1st sidewall 5 2nd sidewall 6 3rd sidewall 7 Extension region 8 Buffer region 9 Deep junction source / drain region 10 Substrate bias application means 11 p-type Silicon substrate 12 Element isolation insulating layer 13 p-type well region 14 gate insulating film 15 gate electrode 16 sidewall 17 pocket region 18 n-type extension region 19 buffer layer 20 n-type buffer region 21 sidewall 22 n-type source / drain region 23 Co Silicide layer 31 Pocket region 32 n-type extension region 41 p-type well region 42 gate insulating film 43 gate electrode 44 n-type extension region 45 n-type source region 46 n-type drain region 47 space charge region 48 channel charge region 51 p-type Well region 52 gate insulating film 53 gate electrode 54 n-type extension region 55 n-type source region 56 n-type drain region 57 space charge region 58 channel charge region 59 shaded portion

Claims (4)

A semiconductor substrate;
A channel region formed in the semiconductor substrate;
A gate insulating film formed on the channel region;
A gate electrode formed on the gate insulating film;
A first sidewall formed on a sidewall of the gate electrode and having a width of 3 nm to 20 nm;
A second sidewall formed on the first sidewall and having a width of 30 nm to 60 nm;
A third side The Wall formed on the second sidewall,
And Aix Ten Deployment region formed in the semiconductor substrate beneath the first side wall,
A buffer region formed on the semiconductor substrate under the second sidewall and deeper than the extension region;
A source region and a drain region formed in the semiconductor substrate under the third sidewall and deeper than the buffer region;
The source region and the drain region are symmetrical structures;
The buffer region on the source region side and the buffer layer on the drain region side have a symmetrical structure,
The extension region on the source region side and the extension region on the drain region side have a symmetrical structure,
A negative voltage is applied to the channel region when the channel region is n-type, and a positive voltage is applied to the channel region when the channel region is p-type. An insulated gate semiconductor device.   2. The insulated gate semiconductor device according to claim 1, wherein an angle formed between a lower end of an outer wall surface of the third sidewall and a main surface of the semiconductor substrate is 60 ° or less. 3. The insulated gate semiconductor device according to claim 1 , wherein a first substrate bias applying means for applying a first bias potential to the channel region when the insulated gate semiconductor device is driven,
2. An insulated gate semiconductor device comprising: a second substrate bias applying means for applying a second bias potential that is larger in absolute value than the first bias potential during standby of the insulated gate semiconductor device. The driving method of an insulated gate semiconductor device according to any one of claims 1 to 3, with the drain voltage below 1V, the substrate bias in the standby state of the insulated gate semiconductor device in the absolute value A method for driving an insulated gate semiconductor device, wherein the voltage is 0.1 V or higher.

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