JPH05218077A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form a spacer of desired thickness which is larger than the film thickness of a gate electrode by repeating several times the deposition of an insulating film which has the same or larger thickness than the thickness of the gate electrode and the formation of a subspacer by etchback. CONSTITUTION:A field oxide film 21 for element isolation is formed on the surface of a P type silicon substrate 11 and then a gate oxide film of 15nm thickness 31 and a gate electrode of 100nm thickness 41 are formed. On the whole surface of the substrate, a first silicon oxide film 61 is deposited. Then, the silicon oxide film 61 is etched back and is left over as a first subspacer 61a only on a side wall of the gate electrode 41. Nextly, a second silicon oxide film 71 is deposited. Then, the silicon oxide film 71 is etched back and is left over as a second subspacer 71a only on a side wall of the first subspacer 61a. By this method, the spacers (the first and the second subspacer 61a, 71a) which are thicker than the gate electrode 41 can be formed on the side wall of the gate electrode 41.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a spacer on a side wall of a gate electrode.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to the drawings.

Conventionally, in a method of manufacturing a semiconductor device having a spacer of this type, first, as shown in FIG. 3A, a field oxide film 21 in an element isolation region is formed on the surface of a P-type silicon substrate 11, for example. After forming the gate oxide film 31, a film for the gate electrode is deposited to a thickness of about 300 to 400 nm to form the gate electrode 41, and then the first N-type impurity diffusion layer 51 is formed using the gate electrode 41 as a mask. After that, a silicon oxide film 62 having a thickness of about 500 nm is deposited,
By etching back, as shown in FIG. 3B, a silicon oxide film is left as a spacer 62a on the side wall of the gate electrode. Next, as shown in FIG. 3C, a second N-type impurity diffusion layer 81 having a higher concentration than that of the first N-type impurity diffusion layer 51 is formed using the spacer 62a as a mask. In this way, an LDD structure MOS transistor can be formed.

[0004]

In recent years, along with the miniaturization of semiconductor devices, the vertical structure is becoming thinner, and the gate electrode is becoming thinner to about 100 nm. The thickness of 200 nm on the side wall of the gate electrode is about 100 nm by the conventional technique.
An example of forming spacers of a certain degree will be described with reference to FIG. FIG. 4A shows a state in which the silicon oxide film 62 is deposited after the gate electrode 41a is formed, and FIG. 4B shows the silicon oxide film 61 after that by etching back the spacer 62.
The state which formed b is shown. Since the thickness of the silicon oxide with respect to the gate electrode 41a is increased, FIG.
As shown in FIG. 3, the silicon oxide film 62 is flattened as compared with FIG. Therefore, when the silicon oxide film is etched back, the width is 150 nm as shown in FIG.
Spacers having a bad shape are formed to some extent. As described above, according to the conventional technique, it is difficult to form a spacer having a width of about 200 nm for a gate electrode having a thickness of about 100 nm.

[0005]

According to a method of manufacturing a semiconductor device of the present invention, a gate electrode is formed in a predetermined region of a surface of a semiconductor substrate via a gate insulating film, an insulating film having a predetermined thickness is deposited, and then anisotropically formed. Conductive etching is performed to leave the insulating film as a spacer on the side wall of the gate electrode. In the spacer forming step, deposition of an insulating film thinner than the thickness of the gate electrode and formation of a sub spacer by etching are repeated. It is a thing.

[0006]

The present invention will be described below with reference to the drawings.

1A to 1F are sectional views in order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1A, a field oxide film 2 for element isolation is formed on the surface of a P-type silicon substrate 11.
1 is formed, a gate oxide film 31 having a thickness of 15 nm, a thickness of 1
The 00 nm gate electrode 41 is formed, and the first N-type impurity diffusion layer 51 is formed. Next, as shown in FIG. 1B, 100 n of the first silicon oxide film 61 is formed by a low pressure CVD method.
m is deposited. Then, the silicon oxide film is etched back by 100 nm to remove the gate electrode 4 as shown in FIG.
A silicon oxide film on the side wall of the first sub spacer 61a.
To remain as. Furthermore, as shown in FIG.
The second silicon oxide film 72 is formed to 100 by the low pressure CVD method.
nm deposition. Then, the second silicon oxide film is removed by 100
nm etch back, and as shown in FIG. 1E, a second silicon oxide film is further formed on the side wall of the first sub spacer 61a.
To remain as a sub-spacer. Then, the second N-type impurity diffusion layer 81 is formed by the ion implantation method.

According to this embodiment, a spacer (consisting of the first and second sub-spacers) thicker than the thickness of the gate electrode is formed on the side wall of the gate electrode having a thickness of 100 nm, which is difficult with the conventional technique. Will be possible.

Next, a second embodiment will be described.

A third silicon oxide film having a thickness of about 100 nm is further deposited on the MOS transistor according to the first embodiment shown in FIG. 1 (f) by a low pressure CVD method, and the silicon oxide film is etched back by 100 nm. Then, as shown in FIG. 2, the third sub-spacer 710a is provided with a third side wall.
To form the sub spacer 91a. After that, the third N-type diffusion layer 101 is formed by the ion implantation method. According to this embodiment, it is possible to obtain a spacer having a film thickness three times that of the gate electrode, and by increasing the impurity concentration in the order of the first, second, and third N-type impurity diffusion layers, three steps can be performed. Since a source / drain region having a difference in concentration can be formed, an electric field near the drain is relaxed, and a MOS with high hot carrier resistance
It becomes possible to form a type transistor. In the present embodiment, the impurity diffusion layers are formed after the gate electrode is formed, after the second subspace is formed, and after the third subspacer is formed, but it is also possible to form each subspacer impurity diffusion layer. The number of sub spacers and the number of times the impurity diffusion layers are formed are not particularly limited.

[0012]

As described above, according to the present invention, by repeating the step of forming the sub-spacer by depositing an insulating film having a thickness equal to or smaller than that of the gate electrode and etching back a plurality of times, an arbitrary thickness larger than that of the gate electrode can be obtained. It has an effect that a spacer having a thickness can be formed.

Further, since the spacer width can be freely set to some extent, the impurity concentration in the source / drain regions can be freely changed to some extent, and a transistor having excellent hot carrier resistance can be formed.

[Brief description of drawings]

1A to 1F are sectional views in order of steps, which are illustrated in FIGS. 1A to 1F for use in describing a first embodiment of the present invention.

FIG. 2 is a sectional view used to describe a second embodiment.

FIG. 3A to FIG. 3A are used for explaining the prior art.
It is a process order sectional view divided and shown in (c).

FIG. 4 is used for explaining the prior art (a),
It is a process order sectional view divided and shown in (b).

[Explanation of symbols]

 11 P-type silicon substrate 21 Field oxide film 31 Gate oxide film 41 Gate electrode 51 First N-type impurity diffusion layer 61 First silicon oxide film 61a First sub spacer 62 Silicon oxide film 62a, 62b Spacer 71 Second Silicon oxide film 71a Second sub spacer 81 Second N type impurity diffusion layer 91 Third silicon oxide film 91a Third sub spacer 101 Third N type impurity diffusion layer

Claims (2)

[Claims] 1. A gate electrode is formed on a predetermined region of a surface of a semiconductor substrate via a gate insulating film, an insulating film having a predetermined thickness is deposited, and then anisotropic etching is performed to form the insulating film on the side wall of the gate electrode. A method of manufacturing a semiconductor device, comprising a step of leaving as a spacer, and in the spacer forming step, deposition of an insulating film thinner than a film thickness of the gate electrode and formation of a sub spacer by etching are repeated. 2. A source / drain region including at least first to third impurity diffusion layers having a higher impurity concentration is formed farther from the gate electrode by performing ion implantation after forming the gate electrode and forming the sub spacer. The method for manufacturing a semiconductor device according to claim 1.