JP2012248561A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that allows improvement of the drain breakdown voltage of a high breakdown voltage transistor even if miniaturized.SOLUTION: Surface portions of a semiconductor substrate (an active region) 101 in regions located at lower portions of side surfaces of a gate electrode 104A are removed and dug-down portions 121 are formed. A low-concentration drain region 105A2 is formed in a region near the sidewall surface and the bottom surface of one dug-down portion 121 in the semiconductor substrate 101. An insulating sidewall spacer 108A is formed so as to cover the side surfaces of the gate electrode 104A and the sidewall surfaces and a part of the bottom surfaces of the dug-down portions 121. A high-concentration drain region 109A2 is formed, so as to be surrounded by the low-concentration drain region 105A2, in a region located outside the insulating sidewall spacer 108A and near the bottom surface of the one dug-down portion 121 in the semiconductor substrate 101.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a high breakdown voltage transistor and a manufacturing method thereof.

  In recent years, the usage applications of semiconductor devices have spread to various fields. In particular, with the expansion to the in-vehicle field and the environmental field, there is an increasing demand for higher breakdown voltage of semiconductor devices. On the other hand, with the reduction in power consumption, high integration, and high speed of semiconductor devices, miniaturization of transistors is rapidly progressing. As a result, there are an increasing number of semiconductor devices in which a fine transistor portion for high integration and high-speed operation and a high breakdown voltage transistor portion required for a power supply controller, a motor controller, and the like are required to be mounted together.

  However, the reduction of the width and height of the gate electrode and the shallow junction due to miniaturization cause deterioration of the breakdown voltage, so that the reliability can be maintained even for miniaturization even when used with a high breakdown voltage (for example, at a power supply voltage of 5 V). A transistor having a breakdown voltage is required.

  Various studies have been made on the structure of a high breakdown voltage transistor. For example, in Patent Document 1, a high-concentration impurity-doped region that becomes a source / drain region is formed by digging a substrate as shown in FIG. A structure has been proposed. A manufacturing method of the conventional semiconductor device shown in FIG. 12 is as follows. First, after forming the well region 11 on the semiconductor substrate 10, the gate electrode 13 is formed on the well region 11 via the gate insulating film 12. Here, the upper surface of the gate electrode 13 is covered with the protective film 14. Next, after lightly doped impurity doped regions 15 are formed below both sides of the gate electrode 13 in the well region 11, sidewall spacers 16 are formed on both side surfaces of the gate electrode 13. Next, after the semiconductor substrate 10 in the region adjacent to the side wall spacer 16 is dug down, a high concentration impurity doped region 17 is formed on the surface portion of the semiconductor substrate 10 in the dug down region. Next, after covering the surface of the low-concentration impurity doped region 15 exposed in the dug-down region with the sidewall oxide film 19, a silicide layer 18 is formed on the surface portion of the high-concentration impurity doped region 17.

  According to the conventional semiconductor device shown in FIG. 12, the distance between the gate electrode 13 and the high-concentration impurity doped region 17 serving as the drain region can be increased, so that the breakdown voltage can be improved.

JP-A 63-90853

  However, the conventional semiconductor device shown in FIG. 12 has the following problems. That is, with the miniaturization, the height of the gate electrode 13 is reduced (that is, the gate electrode polysilicon film is thinned) and the impurity doped region is shallowly formed. 10 has been formed shallowly on the surface portion. For this reason, when the semiconductor substrate 10 is dug after forming the low-concentration impurity doped region 15 and the high-concentration impurity doped region 17 is formed on the surface portion of the semiconductor substrate 10 in the dug-down region, the lower side of the high-concentration impurity doped region 17 The thickness of the low concentration impurity doped region 15 becomes insufficient, or the high concentration impurity doped region 17 is formed deeper than the low concentration impurity doped region 15. As a result, the concentration gradient between the high concentration impurity doped region 17 and the well region 11 becomes large, which causes a problem that the drain breakdown voltage is lowered when a high voltage is applied to the junction between the two. Similar problems also occur in the conventional structure shown in FIG. 13 (see, for example, Patent Document 1) in which the semiconductor substrate 10 is dug down to a position deeper than the low-concentration impurity-doped region 15 to form the high-concentration impurity-doped region 17. To do.

  In view of the above, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can improve the drain breakdown voltage of a high breakdown voltage transistor even when miniaturized.

  In order to achieve the above-mentioned object, the present inventors have conducted various studies. As a result, after forming the gate electrode, the semiconductor substrate around the gate electrode is dug down, and in the vicinity of the side wall surface and the bottom surface of the dug-down portion formed thereby. After forming the low concentration drain region in the semiconductor substrate in the position, an insulating sidewall spacer is formed so as to cover the side surface of the gate electrode and the side wall surface of the digging portion, and then positioned near the bottom surface of the digging portion. The inventors have devised an invention in which a high concentration drain region is formed in a portion of the semiconductor substrate.

  According to the present invention, since the high-concentration drain region is formed in the portion of the semiconductor substrate located near the bottom surface of the dug-down portion, the distance between the gate electrode and the high-concentration drain region can be increased, thereby improving the drain breakdown voltage. Can be achieved. Specifically, the drain breakdown voltage in the OFF state and the drain breakdown voltage (that is, the sustain breakdown voltage) in the ON state (operation state) of the n-type MIS (Metal-Insulator-Semiconductor) transistor can be improved by, for example, about 7V or more. The drain breakdown voltage and the sustain breakdown voltage in the OFF state of the p-type MIS transistor can be improved by, for example, about 10V or more.

  Conventionally, since the semiconductor substrate is dug down after forming the low concentration drain region, the high concentration drain region is formed deeper than the low concentration drain region, and the high concentration drain region and the well region are close to each other. As a result, the leakage current increased. On the other hand, according to the present invention, since the low concentration drain region and the high concentration drain region are sequentially formed after the semiconductor substrate is dug down, the high concentration drain region is surely formed at a shallow position with respect to the low concentration drain region. Therefore, the leak current can be suppressed by sufficiently separating the high concentration drain region and the well region. Therefore, according to the present invention, even when the shallow junction with the miniaturization is advanced, the high breakdown voltage transistor and the low voltage are not changed without a large change from the normal MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) formation process. It is possible to easily obtain a semiconductor device that can be mixed with a driving fine transistor. In addition, by selectively digging out a drain formation region of a transistor that requires high breakdown voltage, the drain region of a specific transistor can be increased in breakdown voltage. It is also possible to increase the breakdown voltage of only the drain region of the source / drain region of a specific transistor. The high breakdown voltage transistor structure in which the gate end and the high-concentration impurity-doped region are separated from each other brings about a decrease in driving capability. However, as described above, the reduction in driving capability is minimized by increasing the breakdown voltage only in necessary portions. Therefore, the chip area can be reduced. Note that in the case where it is necessary to increase the breakdown voltage of both the source region and the drain region of a specific transistor, both the source formation region and the drain formation region may be dug down.

  Specifically, a semiconductor device according to the present invention includes a first gate electrode formed on a first active region in a semiconductor substrate via a first gate insulating film, and a first gate electrode of the first gate electrode. A first digging portion formed by removing a surface portion of the first active region in a region located laterally below one side surface, the first side surface of the first gate electrode, and the first A first insulating sidewall spacer formed so as to cover a part of the side wall surface and the bottom surface of the digging portion; an outer side of the first insulating sidewall spacer; and the bottom surface of the first digging portion. A high-concentration drain region formed in the first active region in a portion located in the vicinity, and a portion in the first active region in a portion located in the vicinity of the side wall surface and the bottom surface of the first dug-down portion. The high concentration drain region is surrounded by It is formed on, and a low concentration drain region and having an impurity concentration lower than the high concentration drain region.

  In the present application, the “semiconductor substrate” includes a substrate having a semiconductor region such as a silicon layer formed by, for example, epitaxial growth or the like.

  In the semiconductor device according to the present invention, the first insulating side wall spacer may be in contact with the side wall surface and the bottom surface of the first digging portion.

  In the semiconductor device according to the present invention, an angle formed by the side wall surface of the first dug-down portion with respect to a main surface of the semiconductor substrate may be 80 ° or less.

  In the semiconductor device according to the present invention, the depth of the first digging portion is not less than 50 nm and not more than 150 nm with reference to the surface of the first active region in the portion in contact with the first gate insulating film. Also good.

  In the semiconductor device according to the present invention, a surface portion of the first active region located on a lower side of the second side surface opposite to the first side surface of the first gate electrode is removed. 2 digging portions, a second insulating sidewall spacer formed so as to cover a part of the second side surface of the first gate electrode and a side wall surface and a bottom surface of the second digging portion; A high concentration source region formed in the first active region in a portion located outside the second insulating sidewall spacer and in the vicinity of the bottom surface of the second digging portion; The first active region in the portion located near the side wall surface and the bottom surface of the dug-down portion is formed so as to surround the high concentration source region, and has an impurity concentration lower than that of the high concentration source region. Low concentration Source region and may further include a. In this case, the width in the gate length direction of the portion sandwiched between the first digging portion and the second digging portion in the first active region is from the surface in contact with the first gate insulating film. You may become large toward the downward direction.

  In the semiconductor device according to the present invention, a first insulating offset spacer may be interposed between the first insulating sidewall spacer and the first side surface of the first gate electrode.

  In the semiconductor device according to the present invention, a silicide layer may be formed on the high-concentration drain region so as to be separated from the first insulating sidewall spacer.

  In the semiconductor device according to the present invention, a liner insulating film is formed on the semiconductor substrate so as to cover the first gate electrode and the first insulating sidewall, and the first insulating side The wall spacer may include an inner side wall spacer having an L-shaped cross-sectional shape and an outer side wall spacer formed on the inner side wall spacer.

  In the semiconductor device according to the present invention, a liner insulating film is formed on the semiconductor substrate so as to cover the first gate electrode and the first insulating sidewall, and the first insulating side The wall spacer may have an L-shaped cross-sectional shape, and the surface of the L-shaped first insulating sidewall spacer may be in contact with the liner insulating film.

  Here, the liner insulating film may be a stressor film.

  In the semiconductor device according to the present invention, a second gate electrode formed on a second active region in the semiconductor substrate via a second gate insulating film, and the second gate in the second active region A drain extension region formed on the side of the electrode; a third insulating sidewall spacer formed on one side of the second gate electrode; and the third active region in the second active region. A drain region formed adjacent to the drain / extension region below the insulating sidewall spacer and having an impurity concentration higher than that of the drain / extension region may be further provided. In this case, the height of the first insulating sidewall spacer may be greater than the height of the third insulating sidewall spacer. The impurity concentration of the drain extension region may be higher than the impurity concentration of the low concentration drain region. The impurity concentration of the drain region may be substantially the same as the impurity concentration of the high concentration drain region. Further, the thickness of the first gate insulating film may be larger than the thickness of the second gate insulating film. The gate length of the first gate electrode may be larger than the gate length of the second gate electrode. The voltage applied to the first gate electrode may be greater than the voltage applied to the second gate electrode. The first gate electrode may be a gate electrode of an input / output circuit transistor, and the second gate electrode may be a gate electrode of a logic circuit transistor.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first gate electrode on a first active region in a semiconductor substrate through a first gate insulating film; Removing a surface portion of the first active region in a region located laterally below the first side surface to form a first digging portion; and a side wall surface and a bottom surface of the first digging portion Forming a low-concentration drain region in the first active region at a portion located in the vicinity of the first gate electrode, and forming the first side surface of the first gate electrode and the side wall surface and the bottom surface of the first dug down portion. A step of forming a first insulating sidewall spacer so as to cover a part thereof; and a portion of the first insulating sidewall spacer located outside the first insulating portion and in the vicinity of the bottom surface of the first digging portion. In the first active region, Serial so as to be surrounded by the lightly doped drain region, and a step of forming a heavily doped drain region having a higher impurity concentration than the lightly doped drain region.

  In the method for manufacturing a semiconductor device according to the present invention, oblique ion implantation of impurities may be used in the step of forming the low concentration drain region.

  According to the present invention, it is possible to provide a semiconductor device capable of improving the drain breakdown voltage of a high breakdown voltage transistor even when miniaturized, and a manufacturing method thereof.

FIG. 1 is a cross-sectional view of the semiconductor device according to the embodiment. FIG. 2 is a plan view of a high voltage transistor in the semiconductor device according to the embodiment. FIG. 3A and FIG. 3B are cross-sectional views illustrating each process of the method for manufacturing a semiconductor device according to the embodiment. 4A and 4B are cross-sectional views illustrating each step of the method of manufacturing a semiconductor device according to the embodiment. FIG. 5A and FIG. 5B are cross-sectional views illustrating each process of the method for manufacturing a semiconductor device according to the embodiment. FIG. 6 is a cross-sectional view of a semiconductor device according to a modification of the embodiment. FIG. 7 is a cross-sectional view of a semiconductor device according to a modification of the embodiment. FIG. 8 is a cross-sectional view of a semiconductor device according to a modification of the embodiment. FIG. 9 is a cross-sectional view of a semiconductor device according to a modification of the embodiment. FIGS. 10A and 10B are cross-sectional views illustrating each process of a method for manufacturing a semiconductor device according to a modification of the embodiment. FIGS. 11A and 11B are cross-sectional views illustrating each process of a method for manufacturing a semiconductor device according to a modification of the embodiment. FIG. 12 is a cross-sectional view of the semiconductor device according to the first conventional example. FIG. 13 is a cross-sectional view of a semiconductor device according to a second conventional example.

  Hereinafter, for a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention, for example, a high voltage transistor to which a 5V power supply voltage used in a motor driver device or the like is applied and a high speed to which a 1.2V power supply voltage is applied are used. An example of a semiconductor device provided with fine transistors for operation (core transistors) on the same substrate will be described with reference to the drawings. In the present embodiment, as an example, a case where both the high breakdown voltage transistor and the core transistor are n-type MIS transistors will be described.

  FIG. 1 is a cross-sectional view of the semiconductor device according to the present embodiment.

  First, the high breakdown voltage transistor in the semiconductor device according to the present embodiment will be described.

As shown in FIG. 1, a semiconductor substrate (specifically, an active region comprising a semiconductor substrate surrounded by an element isolation region not shown) in a high breakdown voltage transistor formation region (hereinafter referred to as a high breakdown voltage transistor region). A p-type well region 102A is formed on the upper portion of 101. On the p-type well region 102A, for example, an n-type polysilicon film with a thickness of about 100 nm to 150 nm is formed, for example, with a thickness of about 300 nm to 1000 nm via a gate insulating film 103A made of a SiO ₂ film with a thickness of about 15 nm to 20 nm. A gate electrode 104A having a moderate gate length is formed. The surface portion of the region located below both sides of the gate electrode 104A in the semiconductor substrate 101 is removed, for example, the depth (depth with reference to the surface of the semiconductor substrate 101 (active region) in the portion in contact with the gate insulating film 103A) is 50 nm. A digging portion 121 of about ˜150 nm is formed. Here, the depth of the digging portion 121 is set in consideration of the element isolation region depth, the well region depth, and the like, and is not limited to the above-described range. In the present embodiment, the side wall surface 122 of the dug-down portion 121 has an inclination angle θ of about 80 degrees or less with respect to the surface of the semiconductor substrate 101 in a portion in contact with the gate insulating film 103A. That is, the width in the gate length direction of the portion sandwiched between the respective dug-down portions 121 in the semiconductor substrate 101 (active region) is increased downward from the surface in contact with the gate insulating film 103A.

  FIG. 2 is a plan view of a high breakdown voltage transistor in the semiconductor device according to the present embodiment. As shown in FIG. 2, for example, a gate electrode 104A is formed so as to be surrounded by an element isolation region 112 having an STI (Shallow Trench Isolation) structure and to cross an active region made of a semiconductor substrate. Each of the active regions (that is, both the source formation region and the drain formation region) located below is formed with a digging portion 121 surrounded by the side wall surface 122 and having a depth of, for example, about 50 nm to 150 nm. Yes. FIG. 2 shows a state immediately after performing a dry etching process for forming the dug-down portion 121 after the formation of the gate electrode 104A.

Further, as shown in FIG. 1, an n-type low concentration source region is included in a portion of the p-type well region 102A located in the vicinity of the side wall surface and the bottom surface of each dug portion 121 formed on both sides of the gate electrode 104A. 105A1 and an n-type low concentration drain region 105A2 are formed. In the n-type low concentration source region 105A1 and the n-type low concentration drain region 105A2, for example, an n-type impurity such as P (phosphorus) or As (arsenic) is 1 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm ^3. It is introduced at a concentration of about. Further, the impurity diffusion depth (depth with reference to the bottom surface of each digging portion 121) of each of the n-type low concentration source region 105A1 and the n-type low concentration drain region 105A2 is, for example, about 150 nm to 500 nm. Insulating sidewall spacers 108A are formed so as to cover both side surfaces of the gate electrode 104A and a part of the side wall surface and bottom surface of each dug portion 121. Here, each insulating side wall spacer 108 </ b> A is in contact with the side wall surface and the bottom surface of each dug portion 121. The insulating sidewall spacer 108A has an L-shaped cross-sectional shape and includes an inner sidewall spacer 106A made of, for example, a SiO ₂ film, and an outer sidewall spacer 107A made of, for example, an SiN film, covering the inner sidewall spacer 106A. And have. In addition, each side surface of the gate electrode 104A and the side wall surface of each digging portion 121 are substantially continuous.

As shown in FIG. 1, the n-type low-concentration source region 105A1 includes an n-type low-concentration source region 105A1 in a portion of the n-type low-concentration source region 105A1 located outside the insulating sidewall spacer 108A and in the vicinity of the bottom surface of the dug-down portion 121. An n-type high concentration source region 109A1 having an impurity concentration higher than that of the n-type low concentration source region 105A1 is formed so as to surround the bottom surface and the side surface. Also, the bottom and side surfaces of the n-type low concentration drain region 105A2 are surrounded by the n-type low concentration drain region 105A2 in the portion of the n-type low concentration drain region 105A2 located outside the insulating sidewall spacer 108A and in the vicinity of the bottom surface of the dug portion 121. In addition, an n-type high-concentration drain region 109A2 having an impurity concentration higher than that of the n-type low-concentration drain region 105A2 is formed. In the n-type high concentration source region 109A1 and the n-type high concentration drain region 109A2, for example, an n-type impurity such as P (phosphorus) or As (arsenic) is 1 × 10 ¹⁹ atoms / cm ³ to 1 × 10 ²² atoms / cm ^3. It is introduced at a concentration of about. Further, the impurity diffusion depths (depths based on the bottom surface of each digging portion 121) of the n-type high-concentration source region 109A1 and the n-type high-concentration drain region 109A2 are the n-type low-concentration source region 105A1 and n-type. It is shallower than the respective impurity diffusion depths of the low-concentration drain region 105A2, for example, about 100 nm or less.

  Further, as shown in FIG. 1, a silicide layer 110A made of, for example, Ni silicide is formed on each surface portion of the gate electrode 104A, the n-type high concentration source region 109A1, and the n-type high concentration drain region 109A2. Further, a liner insulating film 111 made of, for example, a silicon nitride film (SiN film) is formed so as to cover the silicide layer 110A and the insulating sidewall spacer 108A.

  Next, a core transistor (fine transistor) in the semiconductor device according to the present embodiment will be described.

As shown in FIG. 1, a semiconductor substrate (specifically, an active region made of a semiconductor substrate surrounded by an element isolation region not shown) 101 in a core transistor formation region (hereinafter referred to as a core transistor region) 101 A p-type well region 102B is formed in the upper part. On the p-type well region 102B, for example, an n-type polysilicon film having a thickness of about 100 nm to 150 nm and a thickness of, for example, 40 nm to 100 nm are provided via a gate insulating film 103B made of a SiO ₂ film having a thickness of about ₂ nm to 3 nm. A gate electrode 104B having a moderate gate length is formed. Here, the thickness of the gate insulating film 103A of the high voltage transistor is larger than the thickness of the gate insulating film 103B of the core transistor. Further, the gate length (for example, 300 nm to 1000 nm) of the gate electrode 104A of the high breakdown voltage transistor is larger than the gate length (for example, 40 nm to 100 nm) of the gate electrode 104B of the core transistor. In the semiconductor substrate 101, a dug-down portion such as a high breakdown voltage transistor region is not formed on the surface portion of the region located on both sides below the gate electrode 104 </ b> B.

In addition, as shown in FIG. 1, an n-type source / extension region 105B1 and an n-type drain / extension region 105B2 are formed in the p-type well region 102B located below both sides of the gate electrode 104B. In the n-type source / extension region 105B1 and the n-type drain / extension region 105B2, for example, n-type impurities such as P (phosphorus) and As (arsenic) are 1 × 10 ¹⁹ atoms / cm ³ to 1 × 10 ²² atoms / cm ^3. It is introduced at a concentration of about. Here, the impurity concentrations of the n-type source / extension region 105B1 and the n-type drain / extension region 105B2 are higher than the impurity concentrations of the n-type low-concentration source region 105A1 and the n-type low-concentration drain region 105A2. The impurity diffusion depths of the n-type source / extension region 105B1 and the n-type drain / extension region 105B2 are shallower than the impurity diffusion depths of the n-type low-concentration source region 105A1 and the n-type low-concentration drain region 105A2. For example, it is about 70 nm or less.

As shown in FIG. 1, insulating sidewall spacers 108B are formed so as to cover both side surfaces of the gate electrode 104B. The insulating sidewall spacer 108B has an L-shaped cross-sectional shape and includes, for example, an inner sidewall spacer 106B made of a SiO ₂ film and an outer sidewall spacer 107B that covers the inner sidewall spacer 106B and is made of, for example, a SiN film. Have.

Further, as shown in FIG. 1, an n-type source region 109B1 and an n-type drain region 109B2 are formed in the p-type well region 102B located at the lower side of each insulating sidewall spacer 108B. It is formed adjacent to each of the extension region 105B1 and the n-type drain / extension region 105B2. In the n-type source region 109B1 and the n-type drain region 109B2, for example, an n-type impurity such as P (phosphorus) or As (arsenic) has a concentration of about 1 × 10 ¹⁹ atoms / cm ³ to 1 × 10 ²² atoms / cm ^3. Has been introduced. Here, the impurity concentrations of the n-type source region 109B1 and the n-type drain region 109B are substantially the same as the impurity concentrations of the n-type high-concentration source region 109A1 and the n-type high-concentration drain region 109A2. The impurity diffusion depths of the n-type source region 109B1 and the n-type drain region 109B2 are deeper than the impurity diffusion depths of the n-type source / extension region 105B1 and the n-type drain / extension region 105B2, for example, 80 nm to It is about 120 nm.

  Further, as shown in FIG. 1, a silicide layer 110B made of, for example, Ni silicide is formed on each surface portion of the gate electrode 104B, the n-type source region 109B1, and the n-type drain region 109B2. Further, a liner insulating film 111 made of, for example, a SiN film is formed so as to cover the silicide layer 110B and the insulating sidewall spacer 108B.

  A method for manufacturing the semiconductor device according to this embodiment, specifically, a method for manufacturing the semiconductor device according to this embodiment shown in FIG. 1 will be described below with reference to the drawings.

  3 (a), 3 (b), 4 (a), 4 (b), 5 (a), and 5 (b) are cross-sectional views showing respective steps of the method of manufacturing a semiconductor device according to the present embodiment. .

  First, as shown in FIG. 3A, a p-type well region 102A is formed on the semiconductor substrate 101 in the high breakdown voltage transistor region, and a p-type well region 102B is formed on the semiconductor substrate 101 in the core transistor region. . Although not shown in the figure, the active region serving as each transistor region is surrounded by an element isolation region.

Next, as shown in FIG. 3A, on the p-type well region 102A, for example, about 100 nm to 150 nm in thickness via a gate insulating film 103A made of SiO ₂ film about 15 nm to 20 nm in thickness, for example. A gate electrode 104A made of a non-doped polysilicon film is formed. Further, a gate electrode 104B made of a non-doped polysilicon film having a thickness of about 100 nm to 150 nm is formed on the p-type well region 102B via a gate insulating film 103B made of a SiO ₂ film having a thickness of about ₂ nm to 3 nm, for example. To do. Here, in order to protect the gate electrodes 104A and 104B in a substrate digging process, which will be described later, protective films 113A and 113B covering the upper surfaces of the gate electrodes 104A and 104B are formed. When the gate electrodes 104A and 104B and the protective films 113A and 113B are patterned and formed together by dry etching, the polysilicon film that becomes the gate electrodes 104A and 104B is formed before the film that becomes the protective films 113A and 113B is formed. For example, the n-type impurity may be selectively implanted by ion implantation using a resist mask. This makes it possible to suppress depletion at the interface between the gate insulating films 103A and 103B and the polysilicon film, adjust the transistor threshold voltage, and the like, and polysilicon necessary for a CMIS (Complementary Metal-Insulator-Semiconductor) structure. A gate electrode can be formed.

  Next, as shown in FIG. 3B, a resist mask 114 covering the core transistor region is formed in order to dig into the substrate for increasing the breakdown voltage of the source region and the drain region of the high breakdown voltage transistor. In this embodiment, the transistor structure in which both the source region and the drain region of the high breakdown voltage transistor are increased in voltage is described as an example. However, the transistor structure in which only the drain region of the high breakdown voltage transistor is increased in breakdown voltage is also described. This can be realized by digging down the substrate using a resist mask. Next, dry etching treatment is performed on the semiconductor substrate 101 in a portion located in the opening of the resist mask 114 (that is, a portion located on both sides of the gate electrode 104A), for example, to obtain a depth (gate insulating film). A dug-down portion 121 having a depth of about 50 nm to 150 nm (a depth based on the surface of the semiconductor substrate 101 (active region) in a portion in contact with 103A) is formed in each of the source formation region and the drain formation region. Thereafter, the resist mask 114 is removed.

  In the present embodiment, the inclination angle θ of the side wall surface 122 of the dug-down portion 121 is reduced to, for example, about 80 degrees or less by adjusting the etching conditions such as the gas component and the composition ratio in the dry etching process shown in FIG. Set. Specifically, when the inclination angle θ of the sidewall surface 122 is increased, for example, an etching condition with a small sidewall protection effect is used, and when the inclination angle θ of the sidewall surface 122 is decreased, for example, an etching with a large sidewall protection effect is performed. Use conditions. In the present embodiment, a high voltage transistor requiring a breakdown voltage of about 5V is described as an example. However, when realizing a high voltage transistor requiring a breakdown voltage of about 7V or about 10V or more, it is dug down. What is necessary is just to make the depth (namely, substrate digging amount) of the part 121 still larger.

  Next, by performing ion implantation using a resist mask (not shown) having an opening in a region where ion implantation is required, as shown in FIG. An n-type low-concentration source region 105A1 and an n-type low-concentration drain region 105A2 are formed in a portion of the p-type well region 102A located near the side wall surface and the bottom surface of 121. In the core transistor region, an n-type source / extension region 105B1 and an n-type drain / extension region 105B2 are formed in the p-type well region 102B located below both sides of the gate electrode 104B.

Specifically, in the high breakdown voltage transistor region, for example, oblique ion implantation is performed at a tilt angle of about 30 to 60 degrees (an angle formed with respect to a direction perpendicular to the substrate main surface), for example, while changing the tilt direction by 90 degrees. By performing four times, impurities are implanted into the side wall surface and the bottom surface of each dug portion 121 to form the n-type low concentration source region 105A1 and the n-type low concentration drain region 105A2. Even when it is necessary to form a plurality of high breakdown voltage transistors having different gate electrode arrangement directions by changing the inclination direction by 90 degrees and performing oblique ion implantation four times, the side of the digging portion 121 of each transistor It becomes possible to make the amount of impurities injected into the wall surface uniform. The ion implantation conditions for forming the n-type low-concentration source region 105A1 and the n-type low-concentration drain region 105A2 (conditions for each of the four oblique ion implantations) are, for example, that the implanted ions are P (phosphorus) ions. The implantation energy is about 40 keV to 60 keV, and the implantation dose is about 7 × 10 ¹² atoms / cm ^{2 to} 1.5 × 10 ¹³ atoms / cm ² .

On the other hand, in the core transistor region, shallow extension implantation is performed using a resist mask (not shown) having an opening in a region where an extension region which is a low-concentration impurity doped region is formed, whereby an n-type source extension region 105B1 is formed. Then, the n-type drain extension region 105B2 is formed. The ion implantation conditions for forming the n-type source / extension region 105B1 and the n-type drain / extension region 105B2 are, for example, that the implanted ions are As (arsenic), the implantation energy is about 2 keV to 4 keV, and the implantation dose amount. Is about 1 × 10 ¹⁵ atoms / cm ^{2 to} 3 × 10 ¹⁵ atoms / cm ² , and the tilt angle is about 0 to 20 degrees.

  Next, on the semiconductor substrate 101 including the gate electrode 104A in the high breakdown voltage transistor region and the gate electrode 104B in the core transistor region, for example, a thickness of 10 nm by LP-CVD (Low Pressure-Chemical Vapor Deposition) method. After forming a TEOS film (Tetraethylorthosilicate) of about 10 nm or an NSG (Nondoped Silicate Glass) film having a thickness of about 10 nm by SA (Sub Atmospheric) -CVD method, for example, thickness by ALD (Atomic Layer Deposition) method is used. A SiN film having a thickness of about 35 to 60 nm is formed. Thereafter, the laminated structure of the formed insulating films is etched back by anisotropic dry etching, and as shown in FIG. 4B, both side surfaces of the gate electrode 104A and the side of each digging portion 121 are provided. An insulative side wall spacer 108A composed of an inner side wall spacer 106A having an L-shaped cross section and an outer side wall spacer 107A covering the inner side wall spacer 106A is formed so as to cover a part of the wall surface and the bottom surface. Further, an insulating sidewall spacer 108B composed of an inner sidewall spacer 106B having an L-shaped cross section and an outer sidewall spacer 107B covering the inner sidewall spacer 106B is formed so as to cover both side surfaces of the gate electrode 104B. To do. Note that the protective films 113A and 113B covering the upper surfaces of the gate electrodes 104A and 104B may be removed during the etching of the laminated structure of the insulating films.

Next, by performing ion implantation using a resist mask (not shown) having an opening in a region where ion implantation is required, an insulating side is formed in the high breakdown voltage transistor region as shown in FIG. The n-type low-concentration source region 105A1 and the n-type low-concentration in the n-type low-concentration source region 105A1 and the n-type low-concentration drain region 105A2 located outside the wall spacer 108A and in the vicinity of the bottom surface of each dug portion 121. An n-type high concentration source region 109A1 and an n-type high concentration drain region 109A2 having an impurity concentration higher than that of the drain region 105A2 are formed. Here, the n-type high-concentration source region 109A1 and the n-type high-concentration drain region 109A2 are formed so that the side surface and the bottom surface are surrounded by the n-type low-concentration source region 105A1 and the n-type low-concentration drain region 105A2. In the core transistor region, the portion of the p-type well region 102B located on the lower side of each insulating sidewall spacer 108B is higher than the n-type source / extension region 105B1 and the n-type drain / extension region 105B2. An n-type source region 109B1 and an n-type drain region 109B2 having an impurity concentration are formed. The ion implantation conditions for forming the n-type high-concentration source region 109A1 and the n-type high-concentration drain region 109A2 and the n-type source region 109B1 and the n-type drain region 109B2 are, for example, that the implanted ions are As (arsenic) ions. The implantation energy is about ¹⁵ keV to 40 keV, and the implantation dose is about 2 × 10 ¹⁵ atoms / cm ² to 8 × 10 ¹⁵ atoms / cm ² . Instead of or in addition to the ion implantation conditions, for example, the implanted ions are P (phosphorus) ions, the implantation energy is about 5 keV to ¹⁵ keV, and the implantation dose is 1 × 10 ¹⁵ atoms / cm ² to Ion implantation conditions of about 5 × 10 ¹⁵ atoms / cm ² may be used.

  Next, on the semiconductor substrate 101 including the gate electrode 104A in the high breakdown voltage transistor region and the gate electrode 104B in the core transistor region, a film made of a refractory metal such as Ni and having a thickness of about 5 nm to 20 nm is formed. After being deposited by sputtering or the like, a silicidation heat treatment is performed, and then the metal film that has not been silicidized is removed by, for example, wet etching or the like, and then a heat treatment is appropriately performed. As a result, as shown in FIG. 5B, a silicide layer 110A is formed on the respective surface portions of the gate electrode 104A, the n-type high concentration source region 109A1, and the n-type high concentration drain region 109A2, and the gate electrode 104B. , Silicide layers 110B are formed on the surface portions of the n-type source region 109B1 and the n-type drain region 109B2.

A non-silicided region that does not form silicide is formed in the gate electrode 104A, the n-type high concentration source region 109A1, the n-type high concentration drain region 109A2, and the gate electrode 104B, the n-type source region 109B1, and the n-type drain region 109B2. In this case, after depositing a silicide block film such as a SiO ₂ film for suppressing the silicide reaction, an unnecessary silicide block film is removed by dry etching or wet etching using a mask pattern having an opening in the silicidation region, and then Ni A silicide is selectively formed by depositing a metal film such as a film and performing a silicidation heat treatment.

  Next, by forming a liner insulating film 111 made of, for example, a SiN film on the semiconductor substrate 101 including the gate electrode 104A in the high breakdown voltage transistor region and the gate electrode 104B in the core transistor region, FIG. The semiconductor device according to this embodiment shown is completed.

  As described above, according to the present embodiment, in the high breakdown voltage transistor region, the semiconductor substrate 101 around the gate electrode 104A is dug after the gate electrode 104A is formed, and in the vicinity of the side wall surface and the bottom surface of the dug portion 121 formed thereby. After forming the n-type low-concentration drain region 105A2 in the portion of the semiconductor substrate 101, an insulating sidewall spacer 108A is formed so as to cover the side surface of the gate electrode 104A and the side wall surface of the digging portion 121, and then An n-type high concentration drain region 109A2 is formed in a portion of the semiconductor substrate 101 located in the vicinity of the bottom surface of the dug-down portion 121.

  That is, according to the present embodiment, the n-type high concentration drain region 109A2 is formed in the semiconductor substrate 101 in the portion located near the bottom surface of the dug down portion 121, so that the drain region is offset with respect to the gate electrode in the horizontal direction. Compared with the conventional drain extended MIS transistor structure, the distance between the gate electrode 104A and the n-type heavily doped drain region 109A2 is increased without increasing the transistor arrangement area in the main surface of the substrate ( That is, the drain breakdown voltage can be improved by relaxing the electric field between the gate electrode 104A and the n-type heavily doped drain region 109A2. Specifically, the drain breakdown voltage in the OFF state and the drain breakdown voltage (that is, the sustain breakdown voltage) in the ON state (operation state) of the high breakdown voltage transistor made of the n-type MIS transistor can be improved by, for example, about 7V or more.

  Conventionally, since the semiconductor substrate is dug down after forming the low concentration drain region, the high concentration drain region is formed deeper than the low concentration drain region, and the high concentration drain region and the well region are close to each other. As a result, the leakage current increased. On the other hand, according to the present embodiment, since the n-type low concentration drain region 105A2 and the n-type high concentration drain region 109A2 are sequentially formed after the semiconductor substrate 101 is dug down, the n-type low concentration drain region 105A2 is n-type. Since the high-concentration drain region 109A2 can be reliably formed at a shallow position, the n-type high-concentration drain region 109A2 and the p-type well region 102A can be sufficiently separated from each other to suppress the leakage current. Therefore, according to the present embodiment, even when the shallow junction accompanying the miniaturization is advanced, the high breakdown voltage transistor and the low voltage driven fine transistor (core transistor) are not changed greatly from the normal MISFET forming process. A semiconductor device capable of being mounted together can be easily obtained. In addition, by selectively digging out a drain formation region of a transistor that requires high breakdown voltage, the drain region of a specific transistor can be increased in breakdown voltage. It is also possible to increase the breakdown voltage of only the drain region of the source / drain region of a specific transistor. The high breakdown voltage transistor structure in which the gate end and the high-concentration impurity-doped region are separated from each other brings about a decrease in driving capability. However, as described above, the reduction in driving capability is minimized by increasing the breakdown voltage only in necessary portions. Therefore, the chip area can be reduced.

  Further, according to the present embodiment, since the side wall surface 122 of the dug down portion 121 has an inclination angle θ of about 80 degrees or less with respect to the main surface of the substrate, the side wall surface 122 is perpendicular to the main surface of the substrate. Compared to the case where the inclination angle θ of the side wall surface 122 is 90 degrees, the impurities are reliably and uniformly introduced into the semiconductor substrate 101 in the portion located near the side wall surface 122 by oblique ion implantation. Can do. As a result, the n-type low-concentration drain region 105A2 having a gentle impurity concentration gradient can be formed from the periphery of the n-type high-concentration drain region 109A2 to the lower side of the gate electrode 104A. Since electric field concentration can be relaxed, high breakdown voltage can be realized. Although it is difficult to set the inclination angle θ smaller than about 45 degrees with the current manufacturing technology, the inclination angle θ may be set smaller than about 45 degrees if possible in the future.

  In the high breakdown voltage transistor of this embodiment, the dug portions 121 are formed in the semiconductor substrate 101 on both sides of the gate electrode 104A to increase the breakdown voltage of both the drain region and the source region. However, instead of this, for example, as shown in FIG. 6, in the high breakdown voltage transistor, the semiconductor substrate 101 on the drain region side of the gate electrode 104A is not formed in the semiconductor substrate 101 on the source region side of the gate electrode 104A. Alternatively, the recessed portion 121 may be selectively formed to selectively increase the breakdown voltage of the drain region. In this case, the structure on the drain region side is the same as the structure on the drain region side of the high voltage transistor shown in FIG. 1, but the structure on the source region side is the same as the structure on the source region side of the high voltage transistor shown in FIG. Is different. That is, since the dug-down portion is not formed on the source region side, the respective impurity diffusion depths of the n-type low concentration source region 105A1 and the n-type high concentration source region 109A1 (the portion of the semiconductor substrate 101 in contact with the gate insulating film 103A). The depth of the (active region) with respect to the surface) is shallower by the depth of the digging portion 121 than the respective impurity diffusion depths of the n-type low concentration drain region 105A2 and the n-type high concentration drain region 109A2. . Further, the height of the insulating sidewall spacer 108A covering the side surface of the gate electrode 104A on the source region side is lower than the height of the insulating sidewall spacer 108A covering the side surface of the gate electrode 104A on the drain region side. It becomes lower by the depth of.

  In the present embodiment, the inner side wall spacer 106A and the inner side wall spacer having an L-shaped cross section so as to cover both side surfaces of the gate electrode 104A and part of the side wall surface and bottom surface of each dug portion 121. An insulating sidewall spacer 108A composed of an outer sidewall spacer 107A covering 106A was formed. However, instead of this, for example, as shown in FIG. 7, by removing the outer side wall spacer 107A shown in FIG. 1, the insulating side wall made only of the inner side wall spacer 106A having an L-shaped cross-sectional shape is used. A spacer 108A may be formed so that the surface of the L-shaped inner sidewall spacer 106A is in contact with the liner insulating film 111. That is, a disposable sidewall structure may be used. Similarly, with respect to the insulating sidewall spacer 108B that covers both side surfaces of the gate electrode 104B, by removing the outer sidewall spacer 107B shown in FIG. 1, only from the inner sidewall spacer 106B having an L-shaped cross-sectional shape. It may be configured. In this case, for example, when the liner insulating film 111 is a stressor film that generates stress, the driving capability can be further improved by applying stress to the transistor with a disposable sidewall structure. Note that the semiconductor device according to the modification shown in FIG. 6 may also have a disposable sidewall structure by removing the outer sidewall spacers 107A and 107B, for example, as shown in FIG.

  The outline of the manufacturing method of the semiconductor device according to the modification shown in FIG. 7 is as follows. 3B, the n-type low-concentration source region 105A1 and the n-type low-concentration drain region 105A2 and the n-type source / extension region 105B1 and the n-type drain / drain region shown in FIG. The extension region 105B2 is formed, the insulating sidewall spacers 108A and 108B shown in FIG. 4B are formed, and the n-type high-concentration source region 109A1 and the n-type high-concentration drain region 109A2 and n shown in FIG. After the formation of the n-type source region 109B1 and the n-type drain region 109B2, the outer side wall spacers 107A and 107B out of the insulating side wall spacers 108A and 108B are removed by etching, and then, as shown in FIG. Silicide layers 110A and 11 shown Formation of B, and, to implement the formation of the liner insulating film 111.

  In the present embodiment, the silicide layer 110A is formed on the respective surface portions of the gate electrode 104A, the n-type high concentration source region 109A1, and the n-type high concentration drain region 109A2. However, instead of this, the silicide layer 110A may not be formed. Alternatively, as shown in FIG. 9, for example, a silicide layer 110A is formed on each of the n-type high-concentration source region 109A1 and the n-type high-concentration drain region 109A2 and separated from the insulating sidewall spacer 108A by, for example, about 100 nm to 1000 nm. It may be formed. In other words, between the silicide layer 110A formed on each of the n-type high-concentration source region 109A1 and the n-type high-concentration drain region 109A2 and the insulating sidewall spacer 108A, for example, a length of about 100 nm to 1000 nm. A non-silicided region may be provided. Here, a non-silicided region may be provided in only one of the source region and the drain region. By separating the silicide layer 110A on the n-type heavily doped drain region 109A2 and the insulating sidewall spacer 108A, the silicide layer 110A can be kept away from the electric field concentration region in the vicinity of the gate electrode 104A when a high electric field is applied to the drain region. As a result, it is possible to alleviate the electric field concentration in the drain region and further improve the breakdown voltage.

  Further, in the present embodiment, the gate electrode 104A is formed in the step shown in FIG. 3A, and then the dug portions 121 are formed in the semiconductor substrate 101 on both sides of the gate electrode 104A in the step shown in FIG. Formed. However, instead of this, the following process may be performed. That is, after forming the gate electrodes 104A and 104B in the step shown in FIG. 3A, a thickness of 5 nm or more made of, for example, a TEOS film or a SiN film is formed on the semiconductor substrate 101 including the gate electrodes 104A and 104B. An insulating film with a thickness of about 20 nm is deposited, and then the insulating film is etched back by anisotropic dry etching. As shown in FIG. 10A, on both side surfaces of the gate electrodes 104A and 104B. Insulating offset spacers 115A and 115B are formed. Here, the TEOS film may be formed at a low temperature and low pressure, or the SiN film may be formed by a low temperature ALD method. Next, similarly to the process shown in FIG. 3B, as shown in FIG. 10B, the semiconductor substrate 101 is dry-etched using the resist mask 114 covering the core transistor region. Thus, the dug-down portion 121 is formed in each of the source formation region and the drain formation region of the high breakdown voltage transistor region. Here, each outer surface (the outer side surface as viewed from the gate electrode 104A) of the insulating offset spacer 115A and the side wall surface of each digging portion 121 are substantially continuous. In addition, when performing an etching process for forming the dug-down portion 121, the insulating offset spacer 115A effectively functions as a protective film on the side surface of the gate electrode 104A. Next, after removing the resist mask 114, as shown in FIG. 11A, the n-type low concentration source region 105A1 and the n-type low concentration are formed in the high breakdown voltage transistor region as in the step shown in FIG. The drain region 105A2 is formed, and the n-type source / extension region 105B1 and the n-type drain / extension region 105B2 are formed in the core transistor region. Next, similarly to the step shown in FIG. 4B, as shown in FIG. 11B, the insulating sidewall spacer 108A is formed in the high breakdown voltage transistor region, and the insulating sidewall spacer 108B is formed in the core transistor region. Form. Here, an insulating offset spacer 115A is interposed between the insulating sidewall spacer 108A and the gate electrode 104A, and an insulating offset spacer 115B is interposed between the insulating sidewall spacer 108B and the gate electrode 104B. . The subsequent steps are the same as the steps shown in FIGS. 5 (a) and 5 (b).

  The insulating film to be the insulating offset spacers 115A and 115B can be formed at a low temperature in order to suppress oxidation of the gate electrodes 104A and 104B and the semiconductor substrate 101 in addition to the above-described TEOS film or SiN film. An insulating film, for example, an NSG film formed by the SA-CVD method, a SiC film or a SiON film formed at a low temperature, or the like may be used.

In this embodiment, the material and film thickness of the gate insulating films 103A and 103B are not particularly limited, and the gate length, the EOT (Equivalent Oxide Thickness) allowable value, the leakage current allowable value, and the like are taken into consideration. What is necessary is just to determine suitably. In particular, as the thin gate insulating film 103B, for example, high dielectric constant insulating films (insulating films having a relative dielectric constant of 8 or more) such as HfO ₂ film, HfSi _x O _y film, and HfAl _x O _y film, SiO ₂ film, In addition, a single-layer film selected from an insulating film group composed of films obtained by adding nitrogen to these films, or a laminated film including at least one film selected from the insulating film group may be used.

  In the present embodiment, the materials of the gate electrodes 104A and 104B are not particularly limited, and may be determined as appropriate from the viewpoints of workability and silicide reaction. For example, a film obtained by doping an amorphous silicon film or a non-doped polysilicon film with an impurity such as P (phosphorus), As (arsenic), B (boron), In (indium), or Ge (germanium) by ion implantation is used as a gate electrode material. It may be used. Alternatively, a silicon-containing film such as SiGe, a silicon film doped with carbon or metal, or a porous silicon film may be used as the gate electrode material. The formation method of the gate electrode material film as described above is not particularly limited. For example, a film formation method such as an LP-CVD method, a sputtering method or an ALD method, or a coating method may be used.

  In this embodiment, Ni silicide is formed as the silicide layers 110A and 110B. Instead, silicide using Co, Ti, W, Pt, Mo, an alloy or a laminate of these metals is formed. May be.

  In the present embodiment, a semiconductor device in which a high voltage transistor to which a 5 V power supply voltage is applied and a fine transistor (core transistor) for high speed operation to which a 1.2 V power supply voltage is applied is described as an example. However, it can also be applied to a semiconductor device having a high power supply voltage such as 12V, 24V, or 60V by adjusting the gate insulating film thickness, the gate electrode width, the depth of the digging portion, and the like.

In this embodiment, the case where both the high breakdown voltage transistor and the core transistor are n-type MIS transistors has been described as an example. However, by changing the conductivity type of each impurity layer, the high breakdown voltage transistor and the core transistor The present invention is also applicable when both are p-type MIS transistors. For example, in the case of forming a p-type low-concentration source region and a low-concentration drain region in place of the n-type low-concentration source region 105A1 and the n-type low-concentration drain region 105A2 in the high breakdown voltage transistor region, Ion implantation conditions (boron) ions, implantation energy of about 12 keV to 20 keV, implantation dose of about 3 × 10 ¹² atoms / cm ² to 1 × 10 ¹³ atoms / cm ² , and tilt angle of about 30 to 60 degrees (The condition of each time of the oblique ion implantation performed four times) may be used. In the case of forming a p-type source / extension region and an n-type drain / extension region in the core transistor region instead of the n-type source / extension region 105B1 and the n-type drain / extension region 105B2, for example, B (boron) ions, ions having an implantation energy of about 0.3 keV to 1 keV, an implantation dose of about 2 × 10 ¹⁴ atoms / cm ² to 8 × 10 ¹⁴ atoms / cm ² , and a tilt angle of about 0 to 20 degrees Injection conditions may be used. In the high breakdown voltage transistor region, a p-type high concentration source region and a high concentration drain region are formed instead of the n type high concentration source region 109A1 and the n type high concentration drain region 109A2, and in the core transistor region, In the case where a p-type source region and an n-type drain region are formed instead of the n-type source region 109B1 and the n-type drain region 109B2, for example, the implanted ions are B (boron) ions and the implantation energy is about 1 keV to 3 keV. Ion implantation conditions in which the amount is about 2 × 10 ¹⁵ atoms / cm ² to 8 × 10 ¹⁵ atoms / cm ² may be used. When a high breakdown voltage transistor composed of a p-type MIS transistor is formed as described above, the drain breakdown voltage in the OFF state and the drain breakdown voltage (that is, the sustain breakdown voltage) in the ON state (operation state) of the high breakdown voltage transistor is, for example, about 10V. This can be improved.

  In the present embodiment, the high breakdown voltage transistor and the core transistor need not be limited to either the n-type MIS transistor or the p-type MIS transistor. For example, in order to configure the CMIS structure, the high breakdown voltage transistor and the core transistor Needless to say, the n-type MIS transistor and the p-type MIS transistor may be simultaneously mounted on the same semiconductor substrate.

  Further, in the present embodiment, the semiconductor device in which the high breakdown voltage transistor and the fine transistor (core transistor) are mixedly described has been described as an example. However, each use of the high breakdown voltage transistor and the fine transistor is not particularly limited. However, a high voltage transistor may be used as a transistor in a circuit that uses a relatively high power supply voltage, and a fine transistor may be used as a transistor in a circuit that uses a relatively low power supply voltage. For example, the high breakdown voltage transistor may be an input / output (I / O) circuit transistor, and the fine transistor may be a logic circuit transistor.

  As described above, the present invention relates to a semiconductor device having a high breakdown voltage transistor and a method for manufacturing the same, and realizes a high performance semiconductor device in which a fine transistor and a high breakdown voltage transistor are highly integrated and mounted at low cost. Therefore, it is particularly suitable for high-performance LSI devices and the like for environmental field use and in-vehicle field use with high power supply voltage.

101 Semiconductor substrate 102A, 102B p-type well region 103A, 103B Gate insulating film 104A, 104B Gate electrode 105A1 n-type low concentration source region 105A2 n-type low concentration drain region 105B1 n-type source / extension region 105B2 n-type drain / extension region 106A 106B Inner side wall spacer 107A, 107B Outer side wall spacer 108A, 108B Insulating side wall spacer 109A1 n-type high concentration source region 109A2 n type high concentration drain region 109B1 n type source region 109B2 n type drain region 110A, 110B Silicide layer 111 Liner insulating film 112 Element isolation region 113A, 113B Protective film 114 Resist mask 115A, 115B Inclination angle of the side wall surface of the side wall surfaces θ dug portion of the set spacer 121 dug portion 122 dug portion

Claims (20)

A first gate electrode formed on a first active region in a semiconductor substrate via a first gate insulating film;
A first dug portion formed by removing a surface portion of the first active region in a region located on the lower side of the first side surface of the first gate electrode;
A first insulating sidewall spacer formed so as to cover a part of the first side surface of the first gate electrode and a side wall surface and a bottom surface of the first digging portion;
A high-concentration drain region formed in the first active region in a portion located outside the first insulating sidewall spacer and in the vicinity of the bottom surface of the first digging portion;
The first active region in a portion located near the side wall surface and the bottom surface of the first digging portion is formed so as to surround the high concentration drain region, and more than the high concentration drain region. A semiconductor device comprising a low-concentration drain region having a low impurity concentration. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first insulating side wall spacer is in contact with the side wall surface and the bottom surface of the first digging portion. The semiconductor device according to claim 1 or 2,
An angle formed by the side wall surface of the first dug-down portion with respect to a main surface of the semiconductor substrate is 80 ° or less. The semiconductor device according to any one of claims 1 to 3,
The depth of the first digging portion is not less than 50 nm and not more than 150 nm with reference to the surface of the first active region at a portion in contact with the first gate insulating film. The semiconductor device according to any one of claims 1 to 4,
A second dug-down portion formed by removing a surface portion of the first active region located on a side lower side of the second side surface opposite to the first side surface in the first gate electrode;
A second insulating sidewall spacer formed so as to cover a part of the second side surface of the first gate electrode and a side wall surface and a bottom surface of the second dug down portion;
A high-concentration source region formed in the first active region in a portion located outside the second insulating sidewall spacer and in the vicinity of the bottom surface of the second digging portion;
The second active region is formed so as to surround the high-concentration source region in the first active region at a portion located in the vicinity of the side wall surface and the bottom surface of the second dug-down portion, and more than the high-concentration source region. A semiconductor device, further comprising a low concentration source region having a low impurity concentration. The semiconductor device according to claim 5,
The width in the gate length direction of the portion sandwiched between the first digging portion and the second digging portion in the first active region is directed downward from the surface in contact with the first gate insulating film. A semiconductor device characterized by being larger. The semiconductor device according to any one of claims 1 to 6,
A semiconductor device, wherein a first insulating offset spacer is interposed between the first insulating sidewall spacer and the first side surface of the first gate electrode. In the semiconductor device according to claim 1,
A semiconductor device is characterized in that a silicide layer is formed on the high-concentration drain region so as to be separated from the first insulating sidewall spacer. The semiconductor device according to any one of claims 1 to 8,
A liner insulating film is formed on the semiconductor substrate so as to cover the first gate electrode and the first insulating sidewall,
The first insulating sidewall spacer includes an inner sidewall spacer having an L-shaped cross section and an outer sidewall spacer formed on the inner sidewall spacer. The semiconductor device according to any one of claims 1 to 8,
A liner insulating film is formed on the semiconductor substrate so as to cover the first gate electrode and the first insulating sidewall,
The first insulating sidewall spacer has an L-shaped cross-sectional shape, and a surface of the L-shaped first insulating sidewall spacer is in contact with the liner insulating film. Semiconductor device. The semiconductor device according to claim 1,
A second gate electrode formed on the second active region in the semiconductor substrate via a second gate insulating film;
A drain extension region formed laterally below the second gate electrode in the second active region;
A third insulating sidewall spacer formed on one side of the second gate electrode;
A drain region formed adjacent to the drain extension region below the third insulating sidewall spacer in the second active region and having a higher impurity concentration than the drain extension region; Furthermore, the semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 11,
The semiconductor device according to claim 1, wherein a height of the first insulating sidewall spacer is larger than a height of the third insulating sidewall spacer. The semiconductor device according to claim 11 or 12,
The semiconductor device according to claim 1, wherein an impurity concentration of the drain extension region is higher than an impurity concentration of the low concentration drain region. The semiconductor device according to any one of claims 11 to 13,
The semiconductor device according to claim 1, wherein an impurity concentration of the drain region is substantially the same as an impurity concentration of the high concentration drain region. The semiconductor device according to any one of claims 11 to 14,
The semiconductor device is characterized in that the thickness of the first gate insulating film is larger than the thickness of the second gate insulating film. The semiconductor device according to any one of claims 11 to 15,
The semiconductor device according to claim 1, wherein a gate length of the first gate electrode is larger than a gate length of the second gate electrode. The semiconductor device according to any one of claims 11 to 16,
The semiconductor device, wherein a voltage applied to the first gate electrode is larger than a voltage applied to the second gate electrode. The semiconductor device according to any one of claims 11 to 17,
The first gate electrode is a gate electrode of an input / output circuit transistor;
The semiconductor device, wherein the second gate electrode is a gate electrode of a logic circuit transistor. Forming a first gate electrode on a first active region in a semiconductor substrate via a first gate insulating film;
Forming a first digging portion by removing a surface portion of the first active region in a region located laterally below the first side surface of the first gate electrode;
Forming a low-concentration drain region in the first active region in a portion located in the vicinity of the side wall surface and the bottom surface of the first digging portion;
Forming a first insulating sidewall spacer so as to cover the first side surface of the first gate electrode and a part of the side wall surface and the bottom surface of the first digging portion;
The first active region in a portion located outside the first insulating sidewall spacer and in the vicinity of the bottom surface of the first digging portion is surrounded by the low-concentration drain region. And a step of forming a high concentration drain region having a higher impurity concentration than the low concentration drain region. In the manufacturing method of the semiconductor device according to claim 19,
A method of manufacturing a semiconductor device, wherein oblique ion implantation of impurities is used in the step of forming the low concentration drain region.

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