JPS5951567A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve dielectric resistance by forming the shortest distance between two diffusion regions in a substrate. CONSTITUTION:An epitaxial layer 12 and an isolation region 14 are formed, and a resistance region 16 is formed. A section A, in which the concentration of B is maximized in a section deeper than the surface of the Si substrate and a lateral extent thereof is the largest, is formed in the sectional shape of the end section of the resistance region 16 through heat treatment for approximately thirty min in a nitrogen atmosphere at a temperature such a 950 deg.C. That is, the depth of a section B with the largest lateral extent la of the isolation region 14 represents the surface of the epitaxial layer 12, but the largest lateral extent lb is represented at a position A deeper than B by approximately 0.3mum in the resistance region 16, and a lateral extent in the surface of the epitaxial layer 12 is smaller than lb. Accordingly, the shortest distance between the isolation region 14 and the resistance region 16 is a value g'2 which is larger than a value g2 as a value which can be measured simply on a plane.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and particularly to a semiconductor device with improved breakdown voltage.

Conventional configurations and their problems In recent years, the patterns of semiconductor integrated circuits have become increasingly finer, and the distances within and between elements are also becoming smaller. In other words, advances in fine pattern formation technology have allowed patterns to be reduced in submicron units. However, even though the technology for forming fine patterns has advanced, due to problems with semiconductor materials, a certain amount of spacing is required to ensure a certain degree of withstand voltage, which is the only way to prevent the miniaturization of integrated circuit patterns.

An example of a bipolar integrated circuit will be explained using FIG. The figure is a cross-sectional view of a bipolar integrated circuit, in which a P-type Si substrate 11 is coated with an N-type epitaxial layer 1 with a thickness of approximately 1.5 μm.
2, and a P-type isolation region 14 using an oxide film 13;
A P-type resistance region 15 is formed. in this case,
The isolation region 14 and the resistance region 15 are each, for example, B B
It is formed by a diffusion method using a gas such as R3. The breakdown voltage between the isolation region 14 and the resistance region 15 is determined by the shortest distance G2 between the circular regions. Here, the distance G2 is the distance obtained by subtracting the horizontal spread of the impurity introduced into both regions from the distance G1 between the ends of the windows 13a and 13b for introducing impurities into the separation region 14 and the resistance region 15. Therefore, G2=G1- (La+Lb). Here, La and Lb are the lateral spread 1B of impurities in both the isolation and resistance regions 14 and 15, respectively. In general, expansion i' such as the dregs diffusion method is used.
When impurities are introduced using the i'1 method, the amount of spread xjL in the lateral direction from the end of the diffusion window is maximum at the surface of the St substrate, and the maximum vertical diffusion depth xj■ is 0, 7-0.
, about 8 times, but as the width of the diffusion window becomes smaller than Xj■, this value becomes larger.

Therefore, the thickness te-1,5 of the epitaxially fully grown layer 12
When μm, the diffusion depth of the isolation region 14 is Xj V i
≧166 μm, and the diffusion depth of the resistance region 15
Assuming R= 0.6/J m, La ”:=
0.8 x 1.5 = 1.2 (μm) Lb = o, s
x 0.6 #0.5 (μm), and G 2 > 1
．． When trying to obtain 0 μm, G1≧1.2+0.5+1.
0=2.7 μm is required. At least 1.711 m of the 2.7 μm spacing is consumed to compensate for the impurity diffusion structure.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a semiconductor device that can reduce such unnecessary intervals and prevent a drop in breakdown voltage.

Structure of the Invention The present invention is a semiconductor device characterized in that the depth at which the introduced impurity spreads most laterally, that is, the depth at which the concentration of the introduced impurity becomes maximum, is different between two regions.

DESCRIPTION OF THE EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view showing that after forming the epitaxial layer 12 and isolation region 14, the resistive region 16 is
form. At this time, as a method for forming the resistance region 16, boron B ions are implanted using an ion implantation method under conditions of an acceleration voltage of 100 KeV and a dose of 1×10 14 ions/cJ. When B is ion-implanted under these conditions, the projected range is about 0.3 μm, and the concentration reaches its maximum at a depth of about 0.3 μm from the surface of the epitaxial layer 12.

After that, heat treatment is performed for about 30 minutes in a nitrogen atmosphere at 950°C, for example, and the cross-sectional shape of the end of the resistance region 16 is such that the concentration of B is maximum in a part deeper than the surface of the Si substrate, and the part A has the largest lateral curvature. is formed.

That is, the depth of the portion B of the isolation region 14 having the maximum structural girth ta is at the surface of the epitaxial layer 12, but in the resistance region 16, the maximum structural gravity tb is approximately 0.3 μm deeper at the position A.
, and the construction method on the surface of the epitaxial layer 12 is t
Since the value is smaller than b, isolation region 14 and resistance region 1
The long and short distances with 6 will be a value q/2, which is larger than the value q2, which is a value that can be measured simply on the plane. in fact,
Since the shortest distance q/2 is approximately 0.1 μm larger than the shortest planar distance q2, it contributes to an improvement in breakdown voltage by that much.

Next, as a second embodiment, the present invention will be applied to a short channel type MO
An example of application to an ST7 transistor is shown below. short channel MO
3) When forming a transistor, if the length of the gate is smaller than about 1 μm on a planar pattern, impurities for forming the source and drain will enter from the edge of the gate, shortening the effective channel length and reducing the breakdown voltage. difficult to hold. In this example, such a source is used.

In order to improve breakdown voltage deterioration between the drains, the depth at which impurities for forming the source and drain extend in the maximum lateral direction is different between the source and the drain.

FIG. 3 shows a cross-sectional view of an IVIO8 type transistor. In order to form a P-channel length OS transistor with a gate width Lq of 1 μm, the surface of an N-type Si substrate 17 is oxidized to form a gate oxide film 18. Then, Po1Jsi
After laminating the film 19, the film 19 and the oxide film 18 other than the gate region are sequentially selectively etched. Next, source 20
Then, ion implantation is performed to form the drain 21. At this time, B ions are implanted into the drain 21 at an acceleration voltage of 1oOKeV and a dose of 1×1o15ions/crl. At this time, the source region 20 is masked with photoresist.

Next, the drain region 21 is masked with photoresist, and an acceleration voltage of 30 KeV and a dose of 1×10 15 ion are applied.
BF2 ions of s/ctl are implanted. 900 after this
If heat treatment is performed for approximately 30°C, the diffusion depth of the source region 2o will be approximately 0.3 μm, the depth at which the lateral spread will be maximum will be at the surface of the St substrate 17, and the diffusion depth of the drain region 21 will be approximately 0.3 μm. o, about 65 μm, and the depth at which the lateral spread reaches its maximum is approximately 0.3 μm from the surface of the Si substrate. and,
The maximum distance Ld between the source 2o and the drain 21 is approximately 0.56
It is a MOS (μm) transistor.

Note that if the source and drain are formed at the same depth by one ion implantation, the shortest distance between the source and drain will be about 48 μm, so according to this example, 0.
．． 55-0.48 = about 0.07 μm, that is, 14
(There is a distance margin for rust. Now, let's calculate the improvement rate of the punch-through breakdown voltage. The impurity concentration of the St substrate 17 is ND, the electron charge is q, the relative permittivity of SL is ε., If the critical electric field strength is Ec, the punch-through withstand voltage V is, so ND=IX10 cm,,
Ec=30V/μm.

Then, q=1.602x10 coul, to:
=11.9°ε. =8.854×1O-14coul/
/v,,wa, so when Ld=o, 4sμm, V Mai 1
4.2 When VL d = o, rsrspm V#16
．． 3V, and according to the present invention, the withstand voltage is improved.

Effects of the Invention As described above, according to the present invention, by providing the shortest distance between two diffusion regions inside the substrate, it is possible to improve the resistance and pressure. Moreover, according to the present invention, even when punch-through phenomenon occurs, the proportion of current flowing along the substrate surface and the interface with 5102 is reduced, so damage to the surface and interface due to punch-through phenomenon is reduced, and the element It also contributes to improved stability and reliability.

[Brief explanation of the drawing]

FIG. 1 is a structural sectional view of a conventional semiconductor device, FIG. 2 is a structural sectional view showing an embodiment of the present invention, and FIG. 3 is a structural sectional view of a conventional semiconductor device.
S) It is a sectional view of a structure applied to a transistor. 12...Epitaxial layer, 14...
Separation region, 16...Resistance region, 20...
・Source, 21...Drain. Name of agent: Patent attorney Toshio Nakao and 1 other person2

Claims (1)

[Claims] a semiconductor substrate of one conductivity type; and a first semiconductor substrate of the other conductivity type formed on the semiconductor substrate. a second electrode region, the maximum impurity concentration partial force of the first electrode region (second
A semiconductor device characterized in that the electrode region is formed at a position deeper than the maximum impurity concentration portion of the electrode region.