JPS6197970A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the channel effect by means of forming a channel region in the longitudinal direction while minimizing the same. CONSTITUTION:The distance between a source region 2 and a drain region 3 may be shortened by means of providing N<-> type regions 4, 5 in the longitudinal direction along sidewall of a mesa type channel region. Resultantly the punchthrough voltage between the source region 2 and the drain region 3 may be reduced promoting the short channel effect to be traded off by a P type buried region 11 in the mesa type channel region. In such a constitution, height H of N<-> type regions 4, 5, impurity concentration Nb<-> thereof, another impurity concentration NA of P type region 6, width LP of P type buried region 11 and impurity concentration NA thereof may be specified to reduce the trade off between the short channel effect of element and the hot carrier effect down to the optimum value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device that is effective when applied to a long-length micron MOS LSI, and a method for manufacturing the same.

BACKGROUND OF THE INVENTION As a MOS FET, which is a basic element of a submicron scale MOS LSI, the structure shown in FIG. 1 is known (A, Reisman, “LOW
temperatureProcegging an
d small dlmension DeviceF
165th meeti
ng of Electro-chemical 5
ociety A 199. May, 1984).

In Fig. 1, 1 is a P''-shaped silicon substrate, 2゜3
4 and 5 are o-shaped source regions and drain regions formed on the main flank of the silicon substrate 1, respectively, extending from the source region 2° and the drain region 3 toward the channel region side on the main surface of the silicon substrate 1. 6 is a P-type region formed between regions 4 and 5 on the main surface of silicon substrate 1.
5 formed on the main surface of the silicon substrate 1
If it is from IO2, it is a gate oxide film, 8 is a gate pole made of polysilicon or metal silicide completely formed on the gate oxide film γ, 9 is a gate electrode formed on the gate electrode 8 or made of a fracture metal, and 10 is a gate Electrodes 8, 9
This is a sidewall consisting of SIO formed on both ends of the . The thin P-type region 6 under the gate electrode 8 is formed to control the gate threshold voltage Vth, and serves to reduce the short channel effect of the MOS FET. Still, the r regions 4 and 5 are provided to reduce the hot carrier effect, and N+F P junction diode structures are formed on the source side and the drain side, respectively.

In such a configuration, a voltage V between the source and drain
When D is applied, a high electric field region called a depletion layer spreads from the N-P junction to the N''P-type region 4.5 and the P-type region 6. In this way, the depletion layer spreads over the entire area of regions 4 and 5. For,
The wider the width W1, the lower the N″′P′P junction electric field strength, and the hot carrier effect can be reduced.
Although it would be better to make the width W of areas 4 and 5 wider,
The tangle cannot be increased from another point of view. In other words, when a voltage is applied to the gate electrode to turn on the FET, these regions 4 and 5 act as parasitic resistance to the drain current, so if the width W is wide, a voltage drop will occur and the current efficiency will decrease. There's a problem.

On the other hand, the smaller the channel length L is, the higher the current efficiency is, and the smaller the gate region is, which makes it possible to miniaturize the device, which is preferable. However, when the channel length L reaches the submicron scale (for example, 0.5 μm), a significant short channel effect occurs, and the vth value becomes extremely low and its variation becomes large, making it difficult to maintain stable performance. It becomes difficult to obtain, and there is a limit to how small it can be made.

Therefore, in order to obtain a submicron element, special measures must be taken to simultaneously reduce the hot carrier effect and the short channel effect and still achieve miniaturization.

[Purpose of the invention]

The present invention was conceived in view of these points.
The purpose is to provide a semiconductor device and its manufacturing method that can sufficiently reduce hot carrier effects and short channel effects and maintain high performance even in submicron-scale miniaturized elements. .

[Summary of the invention]

In order to achieve such an object, the present invention provides a first conductivity type, low concentration semiconductor substrate in which a channel region is formed in a convex shape from the main surface, and a second conductivity type, high concentration semiconductor substrate, which serves as a source and a drain. a second conductivity type low concentration region welded to the region and in contact with the sidewalls of the convex channel region, and a first conductivity type region embedded in the channel region and a gate insulating film in the channel region. A region of the first conductivity type is formed below, and a region of the NNPP structure is formed, for example, to lower the maximum electric field strength and reduce the hot carrier effect, and a channel is also formed in the vertical direction to shorten the length of the planar channel. The target channel length is set to a sufficient length to reduce the short channel effect.

Further, a convex channel region is formed on the main surface of the low-degree semiconductor substrate of the first conductivity type using two sidewalls having different widths, and a third semiconductor region is formed inside the convex channel region. A first semiconductor device is formed outside the convex channel region of the semiconductor substrate, a second semiconductor region is formed on the sidewall of the convex channel region, and then a gate electrode is formed on the gate insulating film.

[Embodiments of the invention]

Next, the present invention will be explained in detail based on examples.

FIG. 2 is a sectional view of one embodiment of a semiconductor device according to the present invention, and the same or corresponding parts as in FIG. 1 are given the same reference numerals. In the figure, a silicon substrate 1 has a channel region portion projected from the main surface and formed in a convex shape.
, there is a P-shaped region 6 on the main capsule surface of this convex channel region.
is formed. Further, the N'''-shaped regions 4 and 5 have a width W2 wider than that of the conventional one, and are formed to be long in the vertical direction along the side wall of the convex channel region, and a predetermined portion is formed in the silicon substrate 1 between them. P-type regions 11 are formed at intervals.Furthermore, the gate oxide film 7 is peeled off from the surface of the P-shaded region 6, and side falls 10 are formed along the side walls of the N-type regions 4 and 5. ing.

Note that although the gate electrode is not shown, it is formed on the gate oxide film 7.

In such a configuration, the distance between the source region 2 and the drain region 3 is shortened by providing the N-type region 4.5 vertically along the sidewall of the channel region having a convex shape. Therefore, the punch-through voltage between the source region 2 and the drain region 3 becomes small and the short channel effect is promoted, but this can be offset by the P-type region 11 buried in the channel region having a convex shape.

In this case, the height H of the N-type region 4.5 and its impurity concentration N, the impurity concentration NA of the P-type region 6 and the buried P
The width of the shaped region 11 and its impurity concentration N are determined so as to reduce the trade-off between the short channel effect and the hot carrier effect of the device to an optimum value.

Next, a method for manufacturing such a semiconductor device will be described.

FIGS. 3(a) to 3(2) are cross-sectional views of each step in an embodiment of the method for manufacturing a semiconductor device according to the present invention.

First, as shown in FIG. Relatively thick (approximately 100OA) LPCV
A second 5i8N film 17 formed by the D method is sequentially formed, and then a lithography technique is applied to the first 5i8N film 17 in this portion to form a submicron width groove that will become a gate region.
O818N, film 15, 51o2 film 16 and second 5i8N
, film 17 are removed. Here, the thin 5io2 film 16 is a stress relieving film for the first S i , N film 15 .

Next, a 5 in 2 film is formed using the Q method to a thickness that almost fills the trench (for example, about 1000 A), and then
Directional etching (e.g. RIE (ReactiveI)
On Etching)) is performed to form a side fall 18 having a predetermined width slo on the inner wall of the groove as shown in FIG. 2(b). Next, the first 518N, film 15
A P-type region 11 is formed by ion-implanting B (boron) into the silicon substrate 1 using the .degree. Sin film 16 and the second 5IBN4 film 17 as masks. This region 11 is, for example, about 0.1 μm deep. A degree is 10 to 10 pieces/cm
The optimum values are selected taking into account each condition. After removing the long side wall 18 by acid treatment or the like, a P-type epitaxial layer 19 having an impurity concentration similar to that of the silicon substrate 1 is formed in the groove by epitaxial growth, as shown in FIG. In this case, the thickness of this epitaxial layer 19 may be larger or smaller than the depth of the groove. Next, an oxide film 20 of SiO□ is formed on the surface of the epitaxial layer 19 by thermal oxidation. In this case, the thickness of the thermal oxide film 20 is set so that when A (arsenic) is implanted in a later step, it does not reach the epitaxial layer 1S.

On the other hand, the effective thickness of the epitaxial layer 19 determines the height H of the N region formed in a later step. Next, only the second 5L8N4 film 17 is removed by phosphoric acid treatment, and A,
(arsenic) is implanted to form a P-type source region 2 and drain region 3 on the main surface (FIG. 4(d)). Next, the thermal oxide film 20 and the 5102 film 16 are removed by acid treatment with HF solution, and the first 8,8N film 15 is removed by acid treatment with phosphoric acid solution, and then the entire surface is coated with the G method. A PSG film is formed and directional etching (for example, RIE) is performed to form the sidewall KP of the epitaxial layer 19 as shown in the figure (, ).
SG sidewall 21 is formed. Thereafter, gate oxidation is performed in a wet atmosphere to form a gate oxide film 22 on the surface of the epitaxial layer 19, as shown in FIG.
A 5IO2 film 23, which is thicker than the N-layer source region 2 and drain region 3, is formed on the N-layer type source region 2 and drain region 3. At the same time P
Phosphorus diffuses from the SG sidewall 21 to the sidewall of the epitaxial layer 19, forming an r layer 24. next,
The gate electrode 9 is formed by selectively forming a refractory metal such as W (tungsten) on the gate oxide film 22 using the Q method. In this case, the gate electrode 9 can be patterned in a shape that extends beyond the area of the gate oxide film 22 and covers the PSG mud wall 21, and strict dimensional control is not required. After that, protective PSG was applied to the entire surface.
Needless to say, the device is completed by forming the film using a method and wiring each electrode through the contact holes.

〔Effect of the invention〕

As explained above, according to the semiconductor device according to the present invention,
A low concentration semiconductor substrate of a first conductivity type in which a channel region is formed in a convex shape relative to the main surface, and a high concentration region of a second conductivity type which becomes a source and a drain and in contact with this and on a side wall of the convex channel region. A low concentration region of the second conductivity type is formed in contact, and a region of the first conductivity type buried in the channel region and a region of the first conductivity type under the gate insulating film are formed to form a contact region on the source side and the drain side. For example, by forming a NNP junction diode structure, the maximum electric field strength of the NP junction can be lowered without increasing the width of the N region, thereby reducing the hot carrier effect while achieving miniaturization. By forming the channel region in the vertical direction, it is possible to shorten the planar channel length while maintaining a sufficient effective channel length. It can be reduced.

In addition, a channel region is formed in the semiconductor substrate in a convex shape relative to the main surface by using two sidewalls having different widths, and a third semiconductor region is formed inside the convex channel region, and a third semiconductor region is formed outside the convex channel region of the semiconductor substrate. Since the second semiconductor region is formed on the sidewalls of the first semiconductor region and the convex channel region, and then the gate electrode is formed on the gate insulating film, each region can be formed with high precision in a simple process. It is possible to improve productivity.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional semiconductor device, FIG. 2 is a sectional view of an embodiment of a semiconductor device according to the present invention, and FIGS. It is a sectional view of each process in . 1... Silicon substrate, 2... Source region, 3...
...Drain region, 4,5...N''''-shaped region,
6...P-type region, 1...gate insulating film, 8,
9...Gate electrode, 11...P-type region, 15
...First 518N film, 16...5in2 film, 17...Second 5i8N. Film, 18...Side wall, 19...Epitaxial layer, 20...Thermal oxide film, 21...P
SG side wall, 22...gate oxide film, 23
...5102 film, 24...N layer.

Claims (1)

[Claims] 1. A low concentration semiconductor substrate of a first conductivity type in which a channel region is formed to be more convex than the main surface, and a high concentration semiconductor substrate of a second conductivity type formed on the main surface of the semiconductor substrate. a second semiconductor region of a second conductivity type and a low concentration formed in contact with the first semiconductor region and a sidewall of the channel region; 1
A third conductivity type semiconductor region, a first conductivity type fourth semiconductor region formed on the main surface of the channel region, and a gate electrode formed on the channel region with an insulating film interposed therebetween. A semiconductor device characterized by: 2. Forming a first insulating film having a groove on a low concentration semiconductor substrate of a first conductivity type, and forming a first sidewall inside the groove and using this as a mask, forming a first insulating film on the semiconductor substrate. a step of implanting impurities to form a third semiconductor region of a first conductivity type; a step of forming a semiconductor layer of a first conductivity type in the trench after removing the first sidewall; and a step of forming a semiconductor layer of the first conductivity type in the trench. forming a second insulating film on the surface of the shaped semiconductor layer, and using the second insulating film as a mask, implanting impurities onto the semiconductor substrate to form a highly concentrated first semiconductor region of a second conductivity type; forming a second sidewall on the sidewall of the first conductivity type semiconductor layer after removing the first and second insulating films; forming a third insulating film on the surface of the third semiconductor region, and forming a low concentration second semiconductor region of the second conductivity type on the first conductivity type semiconductor layer side of the second sidewall; a step of forming a gate electrode on the third insulating film so as to cover the semiconductor layer of the first conductivity type, the second semiconductor region, and the second sidewall. manufacturing method.