JPH04287928A - Field effect transistor - Google Patents

Abstract

PURPOSE:To provide an FET of good properties which does not affected by a dark current. CONSTITUTION:Highly doped layers 29, 30 and lightly doped layers 24, 25 adjacent thereto are formed in an Si semiconductor substrate 21. A gate electrode 23 is formed on an insulating film 22 formed on a substrate surface. A drain electrode 31 and a source electrode 32 are formed on the highly doped layers 29, 30, and an MOSFET of LDD structure is constituted. A P<+>-type shield layer 27 is formed in contact with the insulating film 22 in a surface layer part of the lightly doped layer 24 at the side of the drain electrode 31. A dark current generated near a region edge of the highly doped layer 29 is shielded by the shield layer 27.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a field effect transistor (
The present invention relates to a MOSFET having an LDD (Lightly Doped Drain) structure.

0002

2. Description of the Related Art A conventional MOSFET having a single drain structure is shown in FIG. 3(a). N+ type high concentration layers 2 and 3 containing donor impurities at a high concentration are formed on a p-type Si semiconductor substrate 1, and an SiO2 film 4 is formed on the surface of the semiconductor substrate 1. This SiO2
A gate electrode 5 is formed on the film 4, and a drain electrode 6 and a source electrode 7 are formed in ohmic contact with the high concentration layers 2 and 3.

[0003] Furthermore, a MOSF with a conventional LDD structure
ET is shown in Figure 3(b). F with this LDD structure
In ET, lightly doped layers 13 and 14 are formed adjacent to heavily doped layers 11 and 12. The rest of the structure is similar to the single drain structure described above, and the same parts are indicated using the same reference numerals.

0004

[Problems to be Solved by the Invention] However, in the above-mentioned conventional FET having a single drain structure, Si--SiO2
Dark current is generated from the interface, causing drain leakage current. This dark current further increases in the FET having the conventional LDD structure. This is Lightly
This is because the Si--SiO2 interface between the doped layers 13 and 14 becomes depleted, and the dark current increases compared to a single-drain structure FET. This increase in dark current is
This causes deterioration of data retention characteristics of high-resistance SRAM memory cells, and also causes refresh failure of DRAM memory cells.

[0005]

[Means for Solving the Problems] The present invention has been made to solve the above problems, and includes a first conductivity type light redoped layer adjacent to a heavily doped layer on the drain electrode side. A shield layer is formed in contact with an insulating film.

[0006]

[Operation] Dark current generated near the edge of the high concentration layer is shielded by the shield layer.

[0007]

[Example] Next, a MOSFET according to an example of the present invention will be described.
I will explain about it. Figure 1 shows a MOSFET according to this embodiment.
FIG. 2 is a cross-sectional view of each manufacturing process of the FET shown in FIG. First, the MOSFE according to this embodiment
The method for manufacturing T will be explained below.

First, an insulating film 22 made of SiO 2 is formed on the surface of a p-type Si semiconductor substrate 21 . next,
A gate electrode 23 is formed on this insulating film 22, and donor impurities are selectively and lightly ion-implanted using this gate electrode 23 as a mask. By this ion implantation, the lightly doped layer 24,
25 is formed (see FIG. 2(a)). The lightly doped layers 24 and 25 are formed with a low impurity concentration because ion implantation is performed lightly.

Next, a resist layer 26 is formed over the entire surface of the semiconductor substrate 21 on which the gate electrode 23 is formed. The formed resist layer 26 is selectively removed using lithography technology, and an exposed portion of the insulating film 22 having a predetermined length L is formed beside the gate electrode 23. Next, the resist layer 26
Then, using the gate electrode 23 as a mask, BF2 + ions are selectively implanted into the exposed insulating film 22 to form a spacer layer 27 (see FIG. 3B). At this time, the exposed length L of the insulating film 22 depends on the thickness of the LDD spacer, that is, the lightly doped layer 24, the alignment accuracy of the resist, and the difference between the p+ type spacer layer 27 and the n+ type high concentration layer 29, which will be described later. It is determined by the withstand voltage value between.

Next, after the resist layer 26 is removed, an oxide film 28 is selectively formed only on the sidewall portions of the gate electrode 23. Thereafter, donor impurities are ion-implanted at a high concentration using the oxide film 26 and the gate electrode 23 on the sidewall portions as masks, thereby forming n+ type high concentration layers 29 and 30 (see FIG. 3(c)).

Next, the insulating film 2 is formed using lithography technology.
A predetermined area of 2 is selectively removed, and the exposed high concentration layer 2
A drain electrode 31 and a source electrode 32 are formed in ohmic contact with 9 and 30. As a result, a MOSFET having the structure shown in FIG. 1 is completed. MOS like this
The FET generally operates by having the source electrode 32 grounded, a predetermined voltage applied to the drain electrode 31, and a signal voltage applied to the gate electrode 23.

In the MOSFET according to this embodiment,
As described above, the shield layer 27 is formed on the surface layer of the lightly doped layer 24 on the side of the drain electrode 31 in contact with the insulating film 22 . Therefore, even if a dark current occurs near the edge of the heavily doped layer 29 adjacent to the lightly doped layer 24, the dark current is blocked by the shield layer 27. In other words, at least a part of the n-type layer of the LDD-MOSFET, in this embodiment, a part of the surface layer of the n-type lightly doped layer 24 on the drain electrode 31 side.
p+ type shield layer 27 at the same potential as the p type semiconductor substrate 21
By providing this, the Si-SiO2 interface is shielded and dark current is reduced.

[0013]

As explained above, according to the present invention, the dark current generated near the edge of the region of the high concentration layer is blocked by the shield layer. Therefore, conventional problems such as deterioration of data retention characteristics of SRAM memory cells due to increase in dark current and refresh failure of DRAM memory cells are resolved, making it possible to provide FETs with good characteristics. .

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a MOSFET according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of each manufacturing process of the MOSFET shown in FIG. 1;

FIG. 3 is a cross-sectional view showing the structure of a MOSFET according to the prior art.

[Explanation of symbols]

21...Si semiconductor substrate 22...Insulating film 23...Gate electrode 24, 25...Lightly doped layer 27...Shield layer 28...Oxide film 29,30...high concentration layer 31...Drain electrode 32...Source electrode

Claims (1)

[Claims] 1. A high concentration layer of a second conductivity type having a high impurity concentration formed in a surface layer of a first conductivity type semiconductor substrate, and an impurity layer formed in a surface layer of the semiconductor substrate adjacent to the high concentration layer. a lightly redoped layer of a second conductivity type with a low concentration;
an insulating film formed on the surface of the semiconductor substrate; a shield layer of a first conductivity type formed on the surface of the lightly redoped layer in contact with the insulating film; and a gate electrode formed on the insulating film; A drain electrode formed in ohmic contact with the one high concentration layer adjacent to the lightly redoped layer on which the shield layer is formed, and a source electrode formed in ohmic contact with the other high concentration layer. A field effect transistor constructed.