JP2936624B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a fine insulated gate field effect transistor (hereinafter abbreviated as MOS transistor) is formed with a high yield. It relates to a manufacturing method.

[Conventional technology]

As semiconductor devices become more highly integrated, they are used in these devices.
The miniaturization of MOS transistors is urgent. The internal electric field strength of a MOS transistor increases with miniaturization, and this is becoming a problem with respect to device reliability.

FIG. 5 is a longitudinal sectional view showing a conventional example of this type of semiconductor device, and FIGS. 6 (a), (b),..., (E) are longitudinal sectional views showing steps of forming the conventional example of FIG. It is.

As shown in FIG. 6A, a thick oxide film 2 for element isolation is formed on a P-type silicon substrate 1 by a selective oxidation method or the like, and then a gate oxide film 12 is formed on an active region. Subsequently, for example, a polycrystalline silicon film 4 is grown as a conductive film for a gate electrode on the substrate surface, and a gate electrode pattern 5 of a resist film is formed thereon. Although not shown, a P-type high impurity layer for a channel stopper may be formed immediately below the field oxide film 2. An appropriate impurity is added to the surface of the semiconductor substrate in the channel region in order to adjust the threshold value of the transistor.

Next, as shown in FIG. 6 (b), a gate electrode 13 is formed, and for example, phosphorus is ion-implanted into the gate electrode 13 and the field oxide film 2 in a self-aligning manner by about 10 ¹³ cm ⁻² , and n ^- forming the source and drain layer 6. Thereafter, as shown in FIG. 6C, an oxide film 8 is deposited on the substrate by, for example, a vapor growth method. Then, this oxide film is selectively anisotropically etched so as to be left only on the side wall of the gate 4.
Next, as shown in FIG. 6 (d), for example, arsenic is ion-implanted into the gate region including the sidewall oxide film 8 by about 10 ¹⁵ cm ⁻² .
The n ⁺ source / drain layers 9 and 10 are formed. Thereafter, an interlayer insulating film 15 is deposited as shown in FIG. 6 (c), and thereafter, metal wiring is applied by a normal process to obtain the MOS transistor shown in FIG. The MOS transistor having this structure has an advantage that the electric field strength at the drain end is reduced as compared with the conventional single drain structure because the source / drain layer has the n ⁻ layer on the channel region side overlapping the gate. .

[Problems to be solved by the invention]

By the way, for miniaturization of the MOS transistor, it is important to make the gate insulating film thinner at the same time as making the gate length minute.

However, in the above-described conventional manufacturing method, when the gate insulating film is thinned, the following problems occur. First, in the conventional method, high-dose ion implantation is performed after the gate is formed in order to form a source / drain diffusion layer in a self-aligned manner with respect to the formed gate electrode. The ion implantation method is a method in which charged particles are implanted into a semiconductor substrate, and thus essentially involves a charging phenomenon. As the gate insulating film becomes thinner, electrostatic breakdown due to this ion implantation process becomes apparent, and there is a concern that the yield of MOS transistors will be reduced in the conventional method described above.

Also, when shortening the channel of the MOS transistor, it is necessary to increase the surface concentration of the semiconductor substrate in the channel region.
In the conventional method, channel doping is performed on an extra region other than the channel region. For this reason, the diffusion layer capacitance of the source / drain increases, which causes a reduction in the operation speed of the device.

The present invention has been made in view of the above-described drawbacks, and after forming a source / drain diffusion layer, a gate electrode is arranged on a channel region in a self-aligned manner via a thin gate oxide film, so that a manufacturing yield is good and a device is manufactured. It is an object to provide a method for manufacturing a semiconductor device which does not lower the operation speed.

[Means for solving the problem]

A method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation region on a semiconductor substrate, a step of forming a first insulating film in an element formation region separated by the element isolation region, and a step of forming a first insulating film on the substrate. (2) forming a coating and forming a resist pattern on the gate electrode scheduled portion of the second coating; selectively etching the second coating using the resist pattern as a mask; Forming a low-concentration source / drain layer in a self-aligned manner with respect to the second coating, forming a third coating on at least a side wall of the second coating, and forming the second coating on the second coating. Forming a high-concentration source / drain layer in a self-aligned manner with respect to the coating pattern, depositing an insulating coating on the entire surface of the substrate, and forming the insulating coating with the second and third coatings; Selectively etching removed until the top surface of the gate electrode pattern is exposed that,
Selectively removing at least the second film and removing the first insulating film on the exposed gate electrode scheduled portion; and forming a gate insulating film on the semiconductor substrate surface of the gate electrode scheduled portion. Forming a gate electrode by depositing a conductive film on the substrate, and selectively removing the conductive film by etching so that the conductive film remains only in a predetermined portion of the gate electrode.

(Operation)

After performing high-concentration ion implantation for source / drain formation, a thin gate insulating film is formed, and a gate electrode is formed in a self-aligned manner with respect to the source / drain layer. Prevent electrostatic breakdown.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a semiconductor device (MOS transistor) showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention;
2 (a), (b),..., (J) are process diagrams showing the manufacturing process of the embodiment of FIG.

As shown in FIG. 2A, a field oxide film 2 (hereinafter referred to as oxide film 2) is formed on a P-type silicon substrate 1 by selective oxidation.
Is formed, and a thermal oxide film 3 is formed on the element formation region. Further, for example, the phosphorus-doped polycrystalline silicon film 4
From 2000 to 8000Å. Then, a resist film 5 having a gate electrode pattern is formed by, for example, photolithography. Next, the polycrystalline silicon film is selectively anisotropically etched using the resist film 5 as a mask, and as shown in FIG. 10 ¹³ cm ^-2 at 20 KeV or 50 KeV
Ion implantation is performed to a degree to form n ⁻ layers 6 and 7. Then, an oxide film is deposited on the substrate by, for example, about 1000 to 4000 degrees by a vapor deposition method. Next, as shown in FIG. 2 (c), oxide film 8 is anisotropically etched to leave only on the side walls of polycrystalline silicon film 4. Then, the side wall oxide film 8 is self-aligned,
For example, arsenic is ion-implanted at an implantation energy of 50 KeV to 80 KeV at about 10 ¹⁵ cm ⁻² to form n ⁺ layers 9 and 10. Then the second
As shown in FIG. 4D, an insulating film 11, for example, a BPS
G, spin glass or other fusible insulating film is deposited. Then, as shown in FIG. 2 (e), the insulating film 11 is selectively etched until the upper surface of the polycrystalline silicon layer 4 is exposed. Next, as shown in FIG. 2 (f), the exposed polycrystalline silicon layer is selectively removed by wet etching or the like. Then, the exposed oxide film 3 is wet-etched,
As shown in FIG. 2 (g), a gate oxide film having a desired film thickness is formed.
Form 12. Thereafter, a conductive film 13, for example, polycrystalline silicon, is deposited on the surface of the substrate including the planned gate electrode portion, and as shown in FIG. By doing so, the gate electrode 13 is formed. Thereafter, a refractory metal film 14 of, for example, tungsten, titanium or the like is deposited on the entire surface of the substrate as shown in FIG. It may be formed. Thereafter, an interlayer insulating film 15 is formed as shown in FIG. 2 (j), and the MOS transistor shown in FIG. 1 is obtained through the following ordinary steps.

FIG. 3 is a longitudinal sectional view of a MOS transistor showing a second embodiment of the present invention, and FIGS. 4 (a), (b),..., (I) show steps of manufacturing the embodiment of FIG. FIG. In this embodiment, since the n ⁻ layer and the gate electrode overlap, the influence of the parasitic resistance due to the n ⁻ layer of the LDD transistor can be reduced.

An element isolation region is formed, and as shown in FIG.
After growing a thermal oxide film 3 on the element region and forming a polycrystalline silicon pattern 4 covering the intended gate electrode portion, until the n ⁻ layers 6 and 7 are formed in a self-aligned manner with respect to this polycrystalline silicon film. Is the same as in the first embodiment. Next, as shown in FIG. 4 (b), a tungsten film 14 or the like is selectively grown on the surface of the polycrystalline silicon by a vapor phase epitaxy of about 1000 to 3000 degrees. Then, as shown in FIG. 4C, n ⁺ layers 9 and 10 are formed on the tungsten film 14 in a self-aligned manner. Next, as shown in FIG. 4 (d), an insulating film 11, for example, an oxide film, a BPSG film, a coating film or the like is grown by vapor phase growth. Thereafter, as shown in FIG. 4E, the insulating film 11 is selectively etched until the upper surface of the tungsten film 14 is exposed. Next, as shown in FIG. 4 (f), the exposed tungsten film and polycrystalline silicon film are selectively removed sequentially by wet etching or the like. Here, for example, boron is ion-implanted into the exposed silicon substrate surface in the exposed gate region at an acceleration energy of 20 KeV to 200 KeV in an amount of about 10 ¹¹ to 10 ¹² cm ^{−2 in} order to prevent punch-through and adjust the threshold voltage. After removing the oxide film 3 by wet etching or the like, 30
A gate oxide film 12 of about {100} is formed. Then, as shown in FIG. 4 (g), a conductive film 13, for example, a polycrystalline silicon film or a high melting point metal film is formed on the substrate including the gate electrode planned portion. Thereafter, as shown in FIG. 4H, selective etching is performed so that the conductive film 13 remains at least in the gate region. Then, as shown in FIG. 4 (i), an interlayer insulating film 15 is formed.
Obtain MOS transistor.

〔The invention's effect〕

As described above, according to the present invention, after performing high-concentration ion implantation for forming a source / drain, a thin gate insulating film is formed, and a gate electrode is self-aligned with respect to the source / drain layer. The formation of the gate insulating film has the effect of preventing electrostatic breakdown of the gate insulating film due to ion implantation, and the ion implantation method with good process control can be applied as before, so that highly integrated semiconductor devices can be manufactured with high yield and high reproducibility. In addition, since an impurity for preventing punch-through can be added only to the channel region, an increase in diffusion layer capacitance can be suppressed, and a high-speed semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a semiconductor device (MOS transistor) showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIGS. 2 (a), (b),. FIG. 3 is a process diagram showing a manufacturing process of the embodiment shown in FIG. 3, FIG. 3 is a vertical sectional view of a MOS transistor showing a second embodiment of the present invention, and FIG.
6 (a), 6 (a) and 6 (b) are process diagrams showing a manufacturing process of the embodiment of FIG. 3, FIG. 5 is a longitudinal sectional view showing a conventional example of this type of semiconductor, and FIGS. 5) to 5 (e) are longitudinal sectional views showing steps of forming the conventional example of FIG. 1 ... P-type silicon substrate, 2,3,8,12 ... oxide film, 4 ... polycrystalline silicon film, 5 ... resist film, 6,7 ... n ^- layer, 9,10 ... n ⁺ Layer, 11 insulating film, 13 conductive film 16 silicide film, 17 metal film.

Claims (1)

(57) [Claims] A step of forming an element isolation region on a semiconductor substrate; a step of forming a first insulating film in an element formation region separated by the element isolation region; and forming a second film on the substrate. Forming a resist pattern on the gate electrode scheduled portion of the second film, selectively etching the second film using the resist pattern as a mask, and forming the second film having the gate electrode pattern on the second film having the gate electrode pattern. On the other hand, a step of forming a low-concentration source / drain layer in a self-aligning manner, a step of forming a third coating on at least a side wall of the second coating, and a second coating pattern on which the third coating is formed, Forming a high concentration source / drain layer in a self-aligned manner, depositing an insulating film on the entire surface of the substrate, and replacing the insulating film with a gate electrode pattern comprising the second and third films; Selectively removing by etching until the upper surface of the gate electrode is exposed; selectively removing at least the second coating to remove the first insulating film on the exposed portion of the expected gate electrode; Forming a gate insulating film on the surface of a portion of the semiconductor substrate, depositing a conductive film on the substrate, and selectively etching away the conductive film so as to remain only in the intended gate electrode portion to form a gate electrode And a method of manufacturing a semiconductor device.