KR100431306B1 - Method for formig gate of semiconductor device using gate oxide made of double film of aluminium oxide and yttrium oxynitride - Google Patents
Method for formig gate of semiconductor device using gate oxide made of double film of aluminium oxide and yttrium oxynitride Download PDFInfo
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- KR100431306B1 KR100431306B1 KR10-2002-0051776A KR20020051776A KR100431306B1 KR 100431306 B1 KR100431306 B1 KR 100431306B1 KR 20020051776 A KR20020051776 A KR 20020051776A KR 100431306 B1 KR100431306 B1 KR 100431306B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02192—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
Abstract
본 발명은 알루미늄산화막(Al2O3)과 이트륨질산화막(YON)의 이중막으로 이루어진 게이트산화막을 이용한 게이트 형성방법을 개시한다. 개시된 본 발명의 게이트 형성방법은, 실리콘기판 상에 알루미늄산화막(Al2O3)을 증착하는 단계; 상기 알루미늄산화막을 열처리하는 단계; 상기 열처리된 알루미늄산화막 상에 이트륨질산화막(YON)을 증착하는 단계; 상기 이트륨질산화막을 열처리하여 상기 알루미늄산화막과 이트륨질산화막의 이중막으로 이루어진 게이트산화막을 형성하는 단계; 상기 게이트산화막 상에 텅스텐막을 증착하는 단계; 및 상기 텅스텐막 및 게이트산화막을 패터닝하는 단계를 포함한다. 본 발명에 따르면, 실리콘산화막 대신에 상기 실리콘산화막 보다 유전율이 2배 정도 높고 내산화성이 우수한 알루미늄산화막과 고유전율을 갖는 이트륨질산화막의 이중막으로 게이트산화막을 형성하기 때문에 낮은 유효 두께를 갖는 게이트산화막을 구현할 수 있으며, 아울러, 게이트산화막의 누설 전류 특성을 개선시킬 수 있다.The present invention discloses a gate forming method using a gate oxide film composed of a double film of an aluminum oxide film (Al 2 O 3 ) and a yttrium nitride oxide (YON). The method of forming a gate of the present invention includes depositing an aluminum oxide film (Al 2 O 3 ) on a silicon substrate; Heat-treating the aluminum oxide film; Depositing a yttrium oxide film (YON) on the heat treated aluminum oxide film; Heat-treating the yttrium oxide film to form a gate oxide film including a double layer of the aluminum oxide film and the yttrium oxide film; Depositing a tungsten film on the gate oxide film; And patterning the tungsten film and the gate oxide film. According to the present invention, a gate oxide film having a low effective thickness is formed because the gate oxide film is formed of a double layer of an aluminum oxide film having a high dielectric constant and an yttrium nitride oxide film having a high dielectric constant and a high dielectric constant than the silicon oxide film instead of the silicon oxide film. In addition, the leakage current characteristics of the gate oxide film may be improved.
Description
본 발명은 반도체 소자의 게이트 형성방법에 관한 것으로, 보다 상세하게는, 유효 두께 및 누설 전류 특성 모두를 만족시킬 수 있는 알루미늄산화막과 이트륨질산화막의 이중막으로 이루어진 게이트산화막을 이용한 반도체 소자의 게이트 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate of a semiconductor device, and more particularly, to forming a gate of a semiconductor device using a gate oxide film composed of a double layer of an aluminum oxide film and a yttrium nitride oxide film capable of satisfying both effective thickness and leakage current characteristics. It is about a method.
일반적으로 모스펫 소자에서의 게이트산화막은 주로 열산화에 의한 실리콘산화막(이하, SiO2막)이 이용되어져 왔다. 그런데, 반도체 소자의 고집적화가 진행되면서 게이트산화막의 박막화도 요구되고 있는데, 이때, 게이트산화막 물질로 상기 SiO2막을 적용하면서 그 두께를 너무 얇게 하면, 게이트산화막을 통해 다이렉트 터널링(direct tunneling)에 의한 누설 전류(leakage current)가 커지므로 안정된 소자 특성을 얻지 못하게 된다.In general, a silicon oxide film (hereinafter referred to as SiO 2 film) by thermal oxidation has been mainly used as a gate oxide film in a MOSFET device. However, as the integration of semiconductor devices progresses, thinning of the gate oxide film is also required. In this case, if the thickness of the gate oxide film is too thin while the SiO 2 film is applied to the gate oxide material, leakage due to direct tunneling through the gate oxide film is performed. As the leakage current increases, stable device characteristics are not obtained.
특히, 반도체 소자의 고집적화 추세에 따라 SiO2막의 다이렉트 터널링 한계인 30Å 이하의 유효 두께를 갖는 게이트산화막이 요구됨으로써, 상기 SiO2막으로는 고집적 소자에서 요구하는 특성, 즉, 누설 전류 특성을 만족시키는데 어려움을 겪고 있다.In particular, sikineunde as being a gate oxide film having an effective thickness less than the SiO 2 film, direct tunneling limit 30Å required by the higher integration trends in semiconductor devices, the SiO 2 film is satisfying the characteristics, i.e., leakage current characteristics required in highly integrated device I'm having a hard time.
따라서, 최근에는 게이트산화막 물질로서 SiO2막 보다 높은 유전율을 갖는 고유전 물질막을 이용함으로써 게이트산화막의 물리적인 두께 증가를 통해 누설 전류 특성을 개선시키려는 연구가 많이 진행되고 있다.Therefore, in recent years, many studies have been conducted to improve leakage current characteristics by increasing the physical thickness of the gate oxide film by using a high-k dielectric material film having a higher dielectric constant than the SiO 2 film as the gate oxide film material.
한 예로, 상기 SiO2막 보다 유전율이 5∼6배 이상인 이트륨질산화막(Yttrium OxyNitride : 이하, YON막)에 대한 연구가 현재 활발하게 진행되고 있으며, 이와 같은 YON막은 고유전율을 갖는 것과 관련해서 게이트산화막의 유효 두께를 손쉽게 감소시킬 수 있으며, 그래서, 고집적 소자의 제조에 유리하게 적용할 수 있을 것으로 예상된다.As an example, studies on Yttrium Oxy Nitride (YON film) having a dielectric constant of 5 to 6 times or more than that of the SiO 2 film are currently being actively conducted. It is expected that the effective thickness of the oxide film can be easily reduced, so that it can be advantageously applied to the manufacture of highly integrated devices.
그러나, 상기 YON막은 물질 특성상 높은 누설 전류 특성을 가지므로, 게이트산화막 물질로의 적용시 그 증착 후에 막질 개선을 위해 열처리가 필수적으로 수행되어야 하는데, 상기 막질 개선을 위한 후속 열처리시, YON막과 실리콘기판의 계면에 저유전율 물질인 SiOx가 형성되며, 이러한 SiOx가 막 전체의 유효 두께를 증가시키는 요인으로 작용하는 바, 실질적으로 YON막은 낮은 유효 두께를 갖지 못한다.However, since the YON film has a high leakage current characteristic due to the material property, heat treatment must be performed to improve the film quality after the deposition when applied to the gate oxide film material. SiOx, which is a low dielectric constant material, is formed at the interface of the substrate, and since such SiOx acts as a factor of increasing the effective thickness of the entire film, substantially the YON film does not have a low effective thickness.
한편, 상기 SiOx의 형성을 방지하기 위해 후속 열처리를 하지 않을 경우, 누설 전류가 증가하여 소자 특성이 취약해진다.On the other hand, when the subsequent heat treatment is not performed to prevent the formation of the SiOx, leakage current increases and the device characteristics become weak.
결국, 상기 YON막을 게이트산화막 물질로 적용함에 있어서, 종래 기술로는 유효 두께 및 누설 전류 특성 모두를 만족시킬 수 없는 바, 상기 YON막의 게이트산화막 물질로의 적용에 어려움이 있다.As a result, in applying the YON film as a gate oxide film material, it is difficult to apply the YON film to the gate oxide film material because it cannot satisfy both the effective thickness and the leakage current characteristics by the conventional technology.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 유효 두께 및 누설 전류 특성 모두를 만족시킬 수 있는 게이트산화막을 이용한 게이트 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a gate using a gate oxide film capable of satisfying both the effective thickness and the leakage current characteristics, which is devised to solve the above problems.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 게이트 형성방법을 설명하기 위한 공정별 단면도.1A to 1D are cross-sectional views of processes for describing a gate forming method according to an exemplary embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 실리콘기판 2 : 알루미늄산화막1: silicon substrate 2: aluminum oxide film
3 : 이트륨질산화막 4 : 게이트산화막3: yttrium oxide film 4: gate oxide film
5 : 텅스텐막 10 : 게이트5: tungsten film 10: gate
상기와 같은 목적을 달성하기 위하여, 본 발명은, 실리콘기판 상에 알루미늄산화막(이하, Al2O3막)을 증착하는 단계; 상기 Al2O3막을 열처리하는 단계; 상기 열처리된 Al2O3막 상에 YON막을 증착하는 단계; 상기 YON막을 열처리하여 Al2O3과 YON의 이중막으로 이루어진 게이트산화막을 형성하는 단계; 상기 게이트산화막 상에텅스텐막을 증착하는 단계; 및 상기 텅스텐막 및 게이트산화막을 패터닝하는 단계를 포함하는 반도체 소자의 게이트 형성방법을 제공한다.In order to achieve the above object, the present invention, the step of depositing an aluminum oxide film (hereinafter, Al 2 O 3 film) on a silicon substrate; Heat treating the Al 2 O 3 film; Depositing a YON film on the heat-treated Al 2 O 3 film; Heat-treating the YON film to form a gate oxide film including a double film of Al 2 O 3 and YON; Depositing a tungsten film on the gate oxide film; And patterning the tungsten film and the gate oxide film.
여기서, 상기 Al2O3막은 기판 온도를 200∼450℃로 유지하고 반응로의 압력을 0.1∼1torr로 유지하며 RF 파워를 10∼500W로 하는 조건하에서 반응 물질로서 H2O를 10∼500sccm으로 흘려주면서 (CH3)3Al을 소오스로 하여 기화시키는 방식을 이용해서 50∼150Å의 두께로 증착한다.Here, the Al 2 O 3 film maintains the substrate temperature at 200 to 450 ° C., maintains the pressure in the reactor at 0.1 to 1 torr, and changes the H 2 O to 10 to 500 sccm as a reaction material under the condition of RF power at 10 to 500 W. While flowing, it is deposited to a thickness of 50 to 150 kV by using a method of vaporizing (CH 3 ) 3 Al as a source.
상기 Al2O3막을 열처리하는 단계는 막 내의 탄소 및 불순물 제거를 위한 N2O 플라즈마 열처리 단계와 결정화를 위한 N2분위기의 열처리 단계로 구성되며, 상기 N2O 플라즈마 열처리는 300∼400℃의 온도에서 수행하고, 상기 N2분위기의 열처리는 600∼650℃의 온도에서 10∼30분 동안 수행한다.The heat treatment of the Al 2 O 3 film comprises an N 2 O plasma heat treatment step for removing carbon and impurities in the film and an N 2 atmosphere heat treatment step for crystallization, and the N 2 O plasma heat treatment is performed at 300 to 400 ° C. It is carried out at a temperature, the heat treatment of the N 2 atmosphere is carried out for 10 to 30 minutes at a temperature of 600 ~ 650 ℃.
상기 YON막은 챔버 내의 압력을 0.1∼1.2torr로 유지하고, 기판 온도를 250∼500℃로 유지하며, RF 파워를 10∼500W로 하는 조건하에서 챔버 내에 이트륨 가스를 소정 양만큼 흘려주면서 반응가스인 NH3가스 및 O2가스를 각각 10∼100sccm 흘려주는 방식을 이용해서 10∼100Å의 두께로 증착한다.The YON membrane maintains the pressure in the chamber at 0.1 to 1.2 torr, maintains the substrate temperature at 250 to 500 ° C, and flows a predetermined amount of yttrium gas into the chamber under a condition of RF power of 10 to 500 W. 3 gas and O 2 gas are deposited to a thickness of 10 to 100 kPa using a method of flowing 10 to 100 sccm, respectively.
상기 YON막의 열처리는 막 내의 질소(N2) 함량 증가를 위한 열처리 단계와 막 내의 탄소(C) 제거 및 증가된 질소(N2) 함량을 유지하기 위한 열처리 단계로 구성되며, 상기 질소 함량 증가를 위한 열처리는 온도를 700∼850℃로 유지하고 N2O가스의 양을 1∼10slm으로 하는 조건하에서 60∼180초 동안 급속열처리로 수행하고, 상기 탄소 제거 및 증가된 질소 함량을 유지하기 위한 열처리는 500∼650℃의 온도에서 5∼60분 동안 퍼니스 진공(Furnace Vaccum) N2열처리로 수행한다.The heat treatment of the YON film comprises a heat treatment step for increasing the nitrogen (N 2 ) content in the film and a heat treatment step for removing carbon (C) in the film and maintaining the increased nitrogen (N 2 ) content. Heat treatment to maintain the temperature at 700 ~ 850 ℃ and rapid heat treatment for 60 to 180 seconds under the condition of the amount of N 2 O gas of 1 to 10 slm, heat treatment to remove the carbon and maintain the increased nitrogen content Is performed by Furnace Vaccum N 2 heat treatment at a temperature of 500 to 650 ° C. for 5 to 60 minutes.
상기 텅스텐막은 기판 히터의 온도를 300∼500℃로 유지하고, 챔버 내의 압력을 20∼60torr로 유지하는 조건하에서 소오스 가스인 WF6가스를 200∼600sccm으로 흘려주면서 반응 가스인 H2가스를 5∼15slm으로 흘려주는 방식을 이용하여 500∼1500Å 두께로 증착한다.The tungsten film keeps the temperature of the substrate heater at 300 to 500 ° C., and flows the H 2 gas as the reaction gas while flowing the WF 6 gas, which is the source gas, at 200 to 600 sccm under the condition of maintaining the pressure in the chamber at 20 to 60 tor. It is deposited to a thickness of 500 ~ 1500Å by using a flow method of 15slm.
본 발명에 따르면, SiO2막대신에 상기 SiO2막 보다 유전율이 2배 정도 높고 내산화성이 우수한 Al2O3막과 고유전율을 갖는 YON막의 이중막으로 게이트산화막을 형성하기 때문에 낮은 유효 두께를 갖는 게이트산화막을 구현할 수 있으며, 아울러, 게이트산화막의 누설 전류 특성을 개선시킬 수 있다.In accordance with the present invention, a high degree of double dielectric constant than that of the SiO 2 film, instead of SiO 2 film a lower effective thickness due to oxidation to form a gate oxide film with YON film bilayers having a high Al 2 O 3 film with a high dielectric constant The gate oxide film may be implemented, and the leakage current characteristic of the gate oxide film may be improved.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 공정별 단면도이다.1A through 1D are cross-sectional views illustrating processes of forming a gate of a semiconductor device according to an exemplary embodiment of the present invention.
도 1a를 참조하면, 소자분리막 및 웰 등이 형성된 실리콘기판(1) 상에 박막의 Al2O3막(2)을 증착한다. 여기서, 상기 Al2O3막의 증착은 기판 온도를 200∼450℃로 유지하고, 반응로의 압력을 0.1∼1torr로 유지하며, RF 파워를 10∼500W로 하는 조건하에서 반응 물질로서 H2O를 10∼500sccm으로 흘려주면서 (CH3)3Al을 소오스로 하여 기화시키는 방식으로 수행하며, 바람직하게, 50∼150Å의 두께로 증착한다.Referring to FIG. 1A, a thin Al 2 O 3 film 2 is deposited on a silicon substrate 1 on which an isolation layer and a well are formed. In the deposition of the Al 2 O 3 film, the substrate temperature is maintained at 200 to 450 ° C., the pressure in the reactor is maintained at 0.1 to 1 torr, and H 2 O is used as a reactant under the condition that the RF power is 10 to 500 W. It is carried out by evaporating with (CH 3 ) 3 Al as a source while flowing at 10 to 500 sccm, and preferably deposited at a thickness of 50 to 150 kPa.
그 다음, 상기 Al2O3막(2) 내의 탄소(C) 및 불순물을 제거하기 위해 상기 Al2O3막(2)이 증착된 기판 결과물에 대해 300∼400℃의 온도에서 N2O 플라즈마 열처리를 수행하고, 이어서, 상기 Al2O3막(2)을 결정화시키기 위해 600∼650℃의 온도 및 N2분위기에서 10∼30분 동안 재차 열처리를 수행한다.Then, N 2 O plasma at a temperature of 300~400 ℃ for the Al 2 O 3 film (2) carbon (C) and the Al 2 O 3 film with a substrate results (2) is deposited in order to remove the impurities in the The heat treatment is performed, and then heat treatment is performed again for 10 to 30 minutes at a temperature of 600 to 650 ° C. and an N 2 atmosphere to crystallize the Al 2 O 3 film 2.
도 1b를 참조하면, PECVD(Plasma Enhanced Chemcial Vapor Deposition) 공정으로 상기 Al2O3막(2) 상에 25 정도의 고유전율을 갖는 YON막(3)을 증착한다. 여기서, 상기 YON막(3)의 증착은 챔버 내의 압력을 0.1∼1.2torr로 유지하고, 기판 온도를 250∼500℃로 유지하며, RF 파워를 10∼500W로 하는 조건하에서 챔버 내에 이트륨 가스를 소정 양만큼 흘려주면서 반응가스인 NH3가스 및 O2가스를 각각 10∼100sccm 흘려주는 방식으로 수행하며, 바람직하게, 10∼100Å의 두께로 증착한다. 이때, 상기 PECVD 공정 대신에 ALD(Atomic Layer Deposition) 공정 또는 ICE(Ionized Cluster Beam) 증착 공정을 이용하는 것도 가능하다.Referring to FIG. 1B, a YON film 3 having a high dielectric constant of about 25 is deposited on the Al 2 O 3 film 2 by a plasma enhanced chemical vapor deposition (PECVD) process. Here, the deposition of the YON film 3 maintains the pressure in the chamber at 0.1 to 1.2 torr, the substrate temperature at 250 to 500 ° C, and the yttrium gas is predetermined in the chamber under the condition that the RF power is 10 to 500 W. The reaction gas is carried out in a manner of flowing 10 to 100 sccm of NH 3 gas and O 2 gas, respectively, while flowing by an amount, and is preferably deposited to a thickness of 10 to 100 kPa. In this case, it is also possible to use an atomic layer deposition (ALD) process or ionized cluster beam (ICE) deposition process instead of the PECVD process.
그 다음, 상기 YON막(3) 내의 질소(N2) 함량을 증가시키기 위해 기판 결과물에 대해 급속열처리(Rapid Thermal Anneal)를 수행한다. 이때, 상기 급속열처리는 온도를 700∼850℃로 유지하고 N2O 가스의 양을 1∼10slm으로 하는 조건하에서60∼180초 동안 수행한다.Then, Rapid Thermal Anneal is performed on the substrate resultant to increase the nitrogen (N 2 ) content in the YON film 3. At this time, the rapid heat treatment is carried out for 60 to 180 seconds under the condition that the temperature is maintained at 700 ~ 850 ℃ and the amount of N 2 O gas is 1 to 10 slm.
연이어, 상기 YON막(3) 내의 탄소(C) 제거 및 증가된 질소(N2) 함량을 유지하기 위해 기판 결과물에 대해 500∼650℃의 온도에서 5∼60분 동안 퍼니스 진공 N2열처리를 수행하고, 이 결과로서, Al2O3막(2)과 YON막(3)의 이중막으로 이루어진 게이트산화막(4)을 형성한다.Subsequently, furnace vacuum N 2 heat treatment was performed for 5 to 60 minutes at a temperature of 500 to 650 ° C. on the substrate resultant to remove carbon (C) in the YON film 3 and to maintain an increased nitrogen (N 2 ) content. As a result, a gate oxide film 4 composed of a double film of the Al 2 O 3 film 2 and the YON film 3 is formed.
도 1c를 참조하면, Al2O3막(2)과 YON막(3)의 이중막으로 이루어진 게이트산화막(4) 상에 게이트용 도전막, 예컨데, 텅스텐막(5)을 증착한다. 이때, 상기 텅스텐막(5)은 기판 가열을 위한 챔버 내의 히터(heater) 온도를 300∼500℃로 유지하고, 그리고, 챔버 내의 압력을 20∼60torr로 유지하는 조건하에서 소오스 가스인 WF6가스를 200∼600sccm 정도 흘려주면서 반응 가스인 H2가스를 5∼15slm 정도 흘려주는 방식으로 수행하며, 바람직하게, 500∼1500Å 두께로 증착한다.Referring to FIG. 1C, a gate conductive film, for example, a tungsten film 5, is deposited on a gate oxide film 4 including a double film of an Al 2 O 3 film 2 and a YON film 3. At this time, the tungsten film 5 maintains a heater temperature in the chamber for heating the substrate at 300 to 500 ° C., and maintains a WF 6 gas, which is a source gas, under the condition of maintaining the pressure in the chamber at 20 to 60 torr. It is carried out in a manner of flowing about 5 to 15 slm of H 2 gas which is a reaction gas while flowing about 200 to 600 sccm, and is preferably deposited to a thickness of 500 to 1500 kPa.
여기서, 게이트용 도전막으로서 상기 텅스텐막(5) 대신에 텅스텐실리사이드막(WSix) 또는 텅스텐질화막(WN)을 이용할 수 있다.A tungsten silicide film WSix or a tungsten nitride film WN may be used instead of the tungsten film 5 as the gate conductive film.
도 1d를 참조하면, 텅스텐막(5)과 게이트산화막(4)을 공지의 포토리소그라피 공정에 따라 패터닝하고, 이 결과로서, 본 발명에 따른 Al2O3막(2)과 YON막(3)의 이중막으로 이루어진 게이트산화막(4)을 구비한 게이트(10)를 형성한다.Referring to FIG. 1D, the tungsten film 5 and the gate oxide film 4 are patterned according to a known photolithography process, and as a result, the Al 2 O 3 film 2 and the YON film 3 according to the present invention. A gate 10 having a gate oxide film 4 made of a double film of is formed.
본 발명에 따른 게이트에 있어서, 게이트산화막은 유전율이 SiO2막의 2배 정도가 되고 내산화성이 우수한 Al2O3막과 25 정도의 고유전율을 갖는 YON막의 이중막구조로 형성된다.In the gate according to the present invention, the gate oxide film is formed of a double film structure of an Al 2 O 3 film having a dielectric constant of about twice the SiO 2 film and excellent oxidation resistance and a YON film having a high dielectric constant of about 25.
이때, 상기 Al2O3막은 상기 YON막의 후속 열처리시 발생되는 실리콘기판의 산화를 방지하는 기능을 하게 되는 바, 낮은 유효 두께의 게이트산화막을 구현할 수 있다. 또한, 상기 Al2O3막은 우수한 누설 전류 특성을 가지며, 이러한 Al2O3막이 YON막 하부에 배치되는 바, 누설 전류 특성 또한 크게 개선된다.In this case, the Al 2 O 3 film is to prevent the oxidation of the silicon substrate generated during the subsequent heat treatment of the YON film, it is possible to implement a gate oxide film having a low effective thickness. In addition, the Al 2 O 3 film has excellent leakage current characteristics, and since the Al 2 O 3 film is disposed under the YON film, the leakage current characteristic is also greatly improved.
결국, 본 발명의 게이트는 게이트산화막을 Al2O3와 YON의 이중막으로 구성함으로써, 유효 두께 및 누설 전류 특성 모두를 만족시킬 수 있다.As a result, the gate of the present invention can satisfy both the effective thickness and the leakage current characteristics by configuring the gate oxide film as a double film of Al 2 O 3 and YON.
이상에서와 같이, 본 발명은 게이트산화막 물질로서 고유전율의 YON막을 이용하면서 그 하부에 누설 전류 특성이 우수하고 기판 산화를 방지할 수 있는 Al2O3막을 배치시킨 Al2O3와 YON의 이중막으로 형성함으로써, 고집적화 추세에 부합하는 10∼15Å의 낮은 유효 두께를 갖는 게이트산화막을 제공할 수 있으며, 아울러, 누설 전류 특성 또한 1×10-8A/㎠ 정도로 개선시킬 수 있다.As described above, the present invention uses a high dielectric constant YON film as a gate oxide material, and has a double layer of Al 2 O 3 and YON having an Al 2 O 3 film having excellent leakage current characteristics and preventing substrate oxidation. By forming the film, it is possible to provide a gate oxide film having a low effective thickness of 10 to 15 mA in accordance with the trend of high integration, and also to improve the leakage current characteristic to about 1 × 10 -8 A / cm 2.
따라서, 본 발명은 낮은 유효 두께를 가지면서 개선된 누설 전류를 갖는 게이트산화막을 구현할 수 있는 바, 고집적 소자의 제조에 유리하게 적용할 수 있다.Therefore, the present invention can implement a gate oxide film having an improved leakage current while having a low effective thickness, which can be advantageously applied to the fabrication of highly integrated devices.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
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| JPH0374878A (en) * | 1989-08-16 | 1991-03-29 | Hitachi Ltd | Manufacturing method of semiconductor device |
| JPH03234025A (en) * | 1990-02-09 | 1991-10-18 | Fujitsu Ltd | Method of forming insulating thin film |
| KR930003383A (en) * | 1991-07-03 | 1993-02-24 | 김광호 | Semiconductor device and manufacturing method thereof |
| KR970018530A (en) * | 1995-09-11 | 1997-04-30 | 김광호 | Capacitor Manufacturing Method of Semiconductor Memory Device |
| KR20010004969A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Method of forming a gate oxide in a semiconductor device |
| KR20010095838A (en) * | 2000-04-12 | 2001-11-07 | 윤종용 | Method for manufacturing dielectric layer of semiconductor device |
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| JPH0374878A (en) * | 1989-08-16 | 1991-03-29 | Hitachi Ltd | Manufacturing method of semiconductor device |
| JPH03234025A (en) * | 1990-02-09 | 1991-10-18 | Fujitsu Ltd | Method of forming insulating thin film |
| KR930003383A (en) * | 1991-07-03 | 1993-02-24 | 김광호 | Semiconductor device and manufacturing method thereof |
| KR970018530A (en) * | 1995-09-11 | 1997-04-30 | 김광호 | Capacitor Manufacturing Method of Semiconductor Memory Device |
| KR20010004969A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Method of forming a gate oxide in a semiconductor device |
| KR20010095838A (en) * | 2000-04-12 | 2001-11-07 | 윤종용 | Method for manufacturing dielectric layer of semiconductor device |
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