KR100875647B1 - Capacitor Formation Method of Semiconductor Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device, and in particular, a semiconductor device capable of improving the degree of integration by preventing electrical shorts between the upper and lower electrodes by a relatively simple process and making the same size between the two electrodes. In order to provide a method for forming a capacitor, the present invention comprises the steps of: laminating a lower electrode metal film, a dielectric material film and an upper electrode metal film on a substrate; Sequentially depositing a first hard mask material film made of the same material as the lower electrode metal film and a second hard mask material film to be used as an etch mask of the dielectric material film on the upper electrode metal film; Forming a photoresist pattern for forming a capacitor on the second hard mask material layer; By selectively etching the second hard mask material layer, the first hard mask material layer, and the upper electrode metal layer using the photoresist pattern as an etching mask, a stacked structure of an upper electrode, a first hard mask, and a second hard mask is formed. Forming; Selectively etching the dielectric material layer using at least the second hard mask as an etch mask to form a dielectric film; And forming a lower electrode by selectively etching the lower electrode metal layer using at least the first hard mask as an etching mask.

Description

Method for forming capacitor of semiconductor device             

1A to 1C are cross-sectional views showing a capacitor forming process according to the prior art.

FIG. 2 is a SEM photograph showing a cross section of the capacitor of FIG. 1. FIG.

3A to 3D are cross-sectional views illustrating a capacitor forming process of a semiconductor device according to an embodiment of the present invention.

4 and 5 are SEM photographs showing the plane and cross section of Fig. 3d, respectively.

Explanation of symbols on the main parts of the drawings

30 substrate 31 field insulating film

32: gate electrode 33: spacer

34 impurity bonding layer 35 interlayer insulating film

36 plug 37b barrier film

38b: lower electrode 39b: dielectric film

40b: upper electrode 50: capacitor

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device.

As the integration of semiconductor devices is accelerated, capacitors with excellent electrical characteristics are required because they have a high electrode capacitance in a narrower space and less influence of leakage current. For this, ferroelectric materials such as SBT (SrBi ₂ Ta ₂ O ₉ ) or PZT ((Pb, Zr) TiO ₃ ) and high dielectric materials such as Ta ₂ O ₅ are used as the dielectric films. In addition, Pt, Ru, Ir, or Ir / IrO ₂ having excellent electrical properties is used as the electrode material.

1A to 1C are cross-sectional views illustrating a capacitor forming process according to the prior art, and looks at the conventional capacitor forming technique with reference to this.

FIG. 1A is a cross-sectional view illustrating the steps up to the formation of the photoresist pattern for forming the upper electrode to form the capacitor pattern, and specifically looks at the process steps up to this point.

First, the field insulating film 11 for isolation between devices is formed on the substrate 10 on which various elements for forming a semiconductor device are formed. The LOCOS (LOCal Oxidation of Silicon) method or the shallow trench isolation (STI) is shown. ) Method.                         

Subsequently, the gate electrode 12 having the spacers 13 on the sidewalls is formed, and the gate electrode 12 is formed of a gate insulating film (not shown) at the contact interface with the substrate 10, tungsten or polysilicon, or the like. A conductive film for a single or stacked gate electrode and a nitride film-based hard mask thereon are included.

An impurity bonding layer 14 such as a source / drain junction is formed on the substrate 10 between the gate electrodes 12 by a method such as ion implantation.

Subsequently, after forming the interlayer insulating film 15 having its top planarized, and then selectively etching the interlayer insulating film 15 to form a capacitor contact hole (not shown) exposing the impurity bonding layer 14, The plug 16 is formed to contact the exposed impurity bonding layer 14, and the plug 16 includes conventional polysilicon or tungsten or the like.

Subsequently, in order to prevent damage to the plug 16 and the substrate 10 due to diffusion of impurities according to a subsequent process, the barrier material film 17a, for example, a diffusion barrier using Ir, IrO ₂ , Ir / IrO ₂ , or the like, may be used. After the deposition of the material film, the lower electrode metal film 18a such as Pt, the dielectric material film 19a, and the upper electrode metal film 20a such as Pt / TiN are sequentially stacked.

Subsequently, the photoresist pattern 21 for forming the upper electrode is formed through a process such as coating, exposing and developing the photoresist.

Subsequently, the upper electrode metal film 20a is etched using the photoresist pattern 21 as an etching mask to form the upper electrode 20b pattern, and then the photoresist pattern 21 is formed on a photoresist strip. After removal through the process, as shown in FIG. 1B, the photoresist pattern 22 for etching the dielectric material film 19a, the lower electrode metal film 18a, and the barrier material film 17a to form a capacitor is formed. To form.

In this case, when the lower electrode pattern forming photoresist pattern 22 is smaller than or equal to the upper electrode forming photoresist pattern 21, an electrical short may be caused between the upper electrode 20b and the lower electrode, as shown. The width of the lower electrode photoresist pattern 22 is made larger.

Next, the dielectric material film 19a, the lower electrode metal film 18a, and the barrier material film 17a are selectively etched using the photoresist pattern 22 as an etch mask, and then a photoresist strip, a cleaning process, or the like. As shown in FIG. 1C, the process of forming a capacitor having a stack structure in which the lower electrode 18b, the dielectric film 19b and the upper electrode 20b are stacked on the barrier film 17b is completed. do.

Subsequently, metallization and a passivation process are performed, and the drawings are omitted for simplicity.

FIG. 2 is a SEM (Scanning Electron Microscopy) photograph showing a cross section of the capacitor of FIG. 1.

On the other hand, in the conventional capacitor formation technique as described above, the following problems occur.

First, different photolithography processes are applied to prevent electrical shorts between the upper and lower electrodes, thereby increasing the complexity of the manufacturing process.

Second, since the lower electrode and the dielectric film are exposed to the plasma by two different etching processes, the possibility of each characteristic deterioration is increased.

Third, in order to prevent the electrical short between the upper and lower electrodes, the size of the lower electrode should be larger than that of the upper electrode, so the actual effective capacitance is proportional to the size of the upper electrode. This, in turn, may be considered to be inferior in density compared to the same device having the same capacitance. 2 illustrates a typical stacked capacitor having a different size between the upper and lower electrodes.

The present invention is to solve the conventional problems as described above, a semiconductor that can improve the degree of integration by preventing the electrical short between the upper electrode and the lower electrode by the relatively simple process and at the same time the size between the two electrodes It is an object of the present invention to provide a method for forming a capacitor of a device.

In order to achieve the above object, the present invention comprises the steps of laminating a metal film for the lower electrode, a dielectric material film and a metal film for the upper electrode on the substrate; Sequentially depositing a first hard mask material film made of the same material as the lower electrode metal film and a second hard mask material film to be used as an etch mask of the dielectric material film on the upper electrode metal film; Forming a photoresist pattern for forming a capacitor on the second hard mask material layer; By selectively etching the second hard mask material layer, the first hard mask material layer, and the upper electrode metal layer using the photoresist pattern as an etching mask, a stacked structure of an upper electrode, a first hard mask, and a second hard mask is formed. Forming; Selectively etching the dielectric material layer using at least the second hard mask as an etch mask to form a dielectric film; And forming a lower electrode by selectively etching the lower electrode metal layer using at least the first hard mask as an etching mask.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings in order that the present invention may be easily implemented by those skilled in the art. 3A to 3D are cross-sectional views illustrating a capacitor forming process of a semiconductor device according to an embodiment of the present invention, and FIGS. 4 and 5 are SEM photographs showing the plane and the cross-section of FIG. 3D, respectively.

FIG. 3A is a cross-sectional view illustrating the steps up to the step of forming a photoresist pattern for forming an upper electrode to form a capacitor pattern, and specifically looks at the process steps up to this point.

First, the field insulating film 31 for isolation between devices is formed on the substrate 30 on which various elements for forming a semiconductor device are formed. The LOCOS method or the STI method is illustrated.

Subsequently, the gate electrode 32 having the spacers 33 is formed on the sidewalls. The gate electrode 32 is formed of a gate insulating film (not shown) at the contact interface with the substrate 30, tungsten or polysilicon, or the like. A conductive film (not shown) for a single or stacked gate electrode and a nitride mask-based hard mask (not shown) thereon.

An impurity bonding layer 34 such as a source / drain junction is formed on the substrate 30 between the gate electrodes 32 by a method such as ion implantation.

Subsequently, an interlayer insulating film 35 having a flattened upper portion thereof is formed using a conventional oxide film-based material film or a flowable oxide film, and then the interlayer insulating film 35 is selectively etched to form an impurity bonding layer ( After forming a capacitor contact hole (not shown) exposing 34, the plug 36 is formed to contact the exposed impurity bonding layer 34. The plug 36 is formed of conventional polysilicon, tungsten, or the like. It includes.

Subsequently, in order to prevent damage to the plug 36 and the substrate 30 due to diffusion of impurities according to a subsequent process, the barrier material film 37a, for example, a diffusion barrier, may be formed using Ir, IrO ₂ , Ir / IrO ₂ , or the like. After depositing the material film, the dielectric material film 39a and Pt / TiN including the lower electrode metal film 38a such as Pt, and Ta ₂ O ₅ SBT, BST, PZT, or BLT in the form of a single or combination thereof. The upper electrode metal film 40a is laminated in this order.

Subsequently, on the upper electrode metal film 40a, the second hard metal used as an etching mask of the first hard mask material film 42a and the dielectric material film 39a made of the same material as the lower electrode metal film 38a is formed. The mask material film 43a is sequentially deposited.

Specifically, the first hard mask material layer 42a includes at least one selected from the group consisting of Ti, Ta, Ti oxide, Ti nitride Ta nitride, TiAlN, TiSiN, and TaON, and includes Ti or Ta. Refractory metal nitrides, oxides or tertiary materials are used.

The second hard mask material layer 43a is preferably deposited to a thickness such that the second dielectric material layer 39a is etched and removed during the subsequent etching of the dielectric material layer 39a. The second hard mask material layer 43a may be formed from a group including Pt, Ir, Ru, Ir oxide, and Ru oxide. At least one selected.

Subsequently, a photoresist pattern 41 for forming a capacitor is formed on the second hard mask material film 43a through a process such as application, exposure and development of the photoresist.

3B, the second hard mask material layer 43a, the first hard mask material layer 42a, and the upper electrode metal layer 40a are selectively selected using the photoresist pattern 41 as an etching mask. By etching to form a stacked structure of the upper electrode 40b / the first hard mask 42b / the second hard mask 43b.

Next, as illustrated in FIG. 3C, the dielectric material layer 39a is selectively etched using at least the second hard mask 43b as an etch mask to form the dielectric layer 39b.

At this time, as described above, the second hard mask 43b is deposited to a thickness that can be completely removed during the etching of the dielectric material layer 39a. In this case, it is also important to appropriately control the etching conditions.

In this case, a dry etching process using a plasma containing carbon-based and fluorine-based gases is used, and representative examples thereof include CF ₄ , C ₂ F ₆ , C ₄ F ₈ , C ₃ F ₆ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ or CH ₃ F and the like.

On the other hand, to etch the dielectric material layer (39a) to further suppress the formation of the fence (fence) to further include an oxygen-based gas within the range that does not rapidly decrease the etch rate during the etching progress, which oxygen-based gas removes the photoresist As a result, the fence can be reduced by reducing the area where redeposition of etched metals such as Pt and dielectric materials occurs.

Continue. By selectively etching the lower electrode material film 38a and the barrier material film 37a using at least the first hard mask 42b as an etch mask to form a lower structure of the barrier film 37b / lower electrode 38b structure. As shown in FIG. 3D, the stacked capacitor 50 is formed.

Here, when etching the lower electrode material film 38a and the barrier material film 37a, a plasma containing an oxygen-based gas and a chlorine-based gas is used. As a representative example, a combination of O ₂ / HBr, O ₂ / Cl _2, or O ₂ / Ar may be considered.

On the other hand, the first hard mask 42b is used as an etching mask and then removed through a separate etching step. As described above, the first hard mask 42b is excessively oxidized by an oxygen-based plasma as a eutectic metal. Since the plate-based plasma is not removed, the surface of the oxide film is gently removed with a plasma containing fluorine-based and carbon-based gas, and then removed using a chlorine-based plasma. At this time, in the case where the first hard mask 42b is Ti nitride, it is preferable not to mix BCl ₃ which is generally used, particularly because of a severe attack on Pt and the like.

For the remaining layers except the etching of the barrier material layer 37a during the above-described etching process, it is preferable to use end pont detection (EPD) to stably accomplish the process.

Subsequently, metallization and a passivation process are performed, and the drawings are omitted for simplicity.

Referring to the planar SEM photograph of FIG. 4, an interlayer insulating film 35 is disposed around the capacitor, and a capacitor 50 having substantially the same size as the upper electrode 40b and the lower electrode 38b is formed at the center thereof. It can be confirmed, it can also be confirmed in the cross-sectional SEM photograph of FIG. In addition, it may be confirmed that almost no loss of the interlayer insulating layer 35 occurs as shown in FIG. 51.

In the present invention as described above, by performing a single photolithography process using a double hard mask to form a capacitor, the process can be simplified, the production cost can be reduced, and the plasma exposure to the lower electrode is 1 By reducing the circuit, damage by plasma can be reduced, the density of the lower electrode can be reduced, and the degree of integration can be improved. By using a hard mask, fence generation can be minimized, thereby improving the reproducibility of the process. I tried to find out.

Although the technical spirit of the present invention has been described in detail according to a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above can expect the following effects.

1. Capacitor pattern formation can be done by one photo etching process, which can be expected to reduce production cost due to process simplicity.

2. Damage to the plasma can be reduced by one plasma exposure in forming the capacitor pattern.

3. The degree of integration can be improved by reducing the area of the lower electrode.

4. Fence can be suppressed by using hard mask.

Claims (7)

Stacking a lower electrode metal film, a dielectric material film, and an upper electrode metal film on a substrate; Sequentially depositing a first hard mask material film made of the same material as the lower electrode metal film and a second hard mask material film to be used as an etch mask of the dielectric material film on the upper electrode metal film; Forming a photoresist pattern for forming a capacitor on the second hard mask material layer; By selectively etching the second hard mask material layer, the first hard mask material layer, and the upper electrode metal layer using the photoresist pattern as an etching mask, a stacked structure of an upper electrode, a first hard mask, and a second hard mask is formed. Forming; Selectively etching the dielectric material layer using at least the second hard mask as an etch mask to form a dielectric film; And Selectively etching the lower electrode metal layer using at least the first hard mask as an etching mask to form a lower electrode Capacitor formation method of a semiconductor device comprising a. The method of claim 1, And depositing the second hard mask material layer to a thickness such that the second hard mask material layer is etched and removed when the dielectric material layer is etched. The method of claim 2, And the second hard mask material layer comprises at least one selected from the group consisting of Pt, Ir, Ru, Ir oxide, and Ru oxide. The method of claim 3, wherein Forming a dielectric film by etching the plasma containing carbon-based gas and fluorine-based gas. The method of claim 1, And the first hard mask material film comprises at least one selected from the group consisting of Ti, Ta, Ti oxide, Ti nitride, Ta nitride, TiAlN, TiSiN, and TaON. The method of claim 1, And forming a lower electrode to etch using a plasma containing an oxygen gas and a chlorine gas. The method of claim 4, wherein Forming the dielectric film, A method of forming a capacitor of a semiconductor device, characterized in that the etching further comprises an oxygen-based gas.

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