KR100721626B1 - Method for forming MIM capacitor of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a MIM capacitor of a semiconductor device, and has an effect of improving the characteristics of a MIM capacitor by removing a metallic polymer generated in an etching process for forming a MIM capacitor.

According to an aspect of the present invention, there is provided a method of forming a MIM capacitor of a semiconductor device, the method including: providing a semiconductor substrate having a conductive plug; Sequentially forming a first metal film, a dielectric film, a second metal film, a hard mask film, and a photoresist pattern covering the MIM capacitor formation region on the semiconductor substrate; Forming a MIM capacitor electrically connected to the conductive plug by patterning the hard mask film, the second metal film, the dielectric film, and the first metal film by an etching process using the photoresist pattern as a mask; Removing the photoresist pattern; And performing a dry etching process on the entire surface of the substrate including the MIM capacitor to remove the metallic polymer generated when the MIM capacitor is formed.

Here, before or after the step of removing the photosensitive film pattern, performing a cleaning process; includes.

Metal-insulator-metal (MIM), polymer

Description

Method for forming MIM capacitor of semiconductor device

1 is a planar photograph showing a state where a metallic polymer remains in a MIM capacitor formed according to the prior art.

2A to 2G are cross-sectional views illustrating processes for forming a MIM capacitor in a semiconductor device according to a first embodiment of the present invention.

3 is a top plan view of a MIM capacitor formed in accordance with an embodiment of the present invention.

4A to 4C are cross-sectional views illustrating processes of forming MIM capacitors of a semiconductor device in accordance with a second embodiment of the present invention.

5A to 5C are cross-sectional views illustrating processes of forming MIM capacitors of a semiconductor device in accordance with a third embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

200: semiconductor substrate 201: first interlayer insulating film

202: lower metal wiring 203: diffusion barrier

204: second interlayer insulating film 205: first photosensitive film pattern

206: trench 207: conductive plug

208: first metal film 208a: lower electrode

209: dielectric film 209a: patterned dielectric film

210: second metal film 210a: upper electrode

211: Hard Mask Film 211a: Patterned Hard Mask Film

212: second photosensitive film pattern 213: MIM capacitor

The present invention relates to a method of forming a MIM capacitor of a semiconductor device, and more particularly, to a method of forming a MIM capacitor of a semiconductor device capable of improving the characteristics of a MIM capacitor by removing a metallic polymer generated in an etching process for forming a MIM capacitor. .

As semiconductor devices are becoming highly integrated, analog devices among semiconductor devices are required to have high precision. Accordingly, capacitors used in analog devices require capacitors with more stable capacitance. The capacitor is generally composed of an upper electrode, a dielectric film, and a lower electrode, and its capacitance may change as external factors change. Here, the change of the external factors may include a change in the voltage supplied or a change in heat applied to the device.

When the lower or upper electrode of the capacitor is formed of a doped polysilicon film, the capacitance is severely changed according to the change of external factors, which may not be suitable for analog devices requiring high precision. Therefore, it is necessary to use a metal plate having little depletion and low resistance as the electrode of the capacitor.

In accordance with this trend, the structure of capacitors is being changed from metal-insulator-silicon (MIS) to metal-insulator-metal (MIM), among which MIM capacitors have a small resistivity and parasitic capacitance due to depletion therein. It is mainly used for a high performance semiconductor device because there is no.

The electrodes of the MIM capacitor are formed by patterning a metal film such as a TaN film or a TiN film. That is, after the lower electrode forming metal film, the dielectric film and the upper electrode forming metal film are sequentially formed, the upper electrode forming metal film, the dielectric film and the lower electrode forming metal film are etched using the photoresist pattern as an etching mask. The photoresist pattern is removed to form a MIM capacitor. However, when the metal film is etched using the photoresist pattern, the elements constituting the photoresist film and the metal film react with each other to generate a large amount of metallic polymer on the surface of the MIM capacitor.

1 is a planar photograph showing a state in which a metallic polymer remains in a MIM capacitor formed according to the prior art. The photograph shown on the left shows that the metallic polymer is thickly stacked inside the upper portion of the MIM capacitor. The photo shows a thick metal polymer deposit on the top edge of the MIM capacitor.

Here, in FIG. 1, only the thickly stacked metallic polymers can be visually confirmed, but in fact, when these photographs are enlarged, the metallic polymers are generally generated on the upper portion of the MIM capacitor. These metallic polymers are not easily removed by a general cleaning method, which acts as a leakage current component of the capacitor, degrading the characteristics of the MIM capacitor and subsequently causing a lifting phenomenon of a film deposited on the MIM capacitor. There is a problem. Accordingly, a method of removing the photoresist pattern with CF ₄ gas has been attempted to remove the polymer, but this method is effective in removing the polymer, but the electrode is etched.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to remove the metallic polymer generated in the etching process for forming the MIM capacitor, thereby improving the characteristics of the MIM capacitor, and improving the characteristics of the film deposited on the MIM capacitor. The present invention provides a method of forming a MIM capacitor of a semiconductor device capable of preventing a lifting phenomenon.

Method of forming a MIM capacitor of a semiconductor device according to an embodiment of the present invention for achieving the above object,

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Providing a semiconductor substrate provided with a conductive plug;

Sequentially forming a first metal film, a dielectric film, a second metal film, a hard mask film, and a photoresist pattern covering the MIM capacitor formation region on the semiconductor substrate;

Forming a MIM capacitor electrically connected to the conductive plug by patterning the hard mask film, the second metal film, the dielectric film, and the first metal film by an etching process using the photoresist pattern as a mask;

Removing the photoresist pattern; And

And performing a dry etching process on the entire surface of the substrate including the MIM capacitor to remove the metallic polymer generated when the MIM capacitor is formed.

Here, before or after the step of removing the photosensitive film pattern,

Performing a cleaning process; characterized in that it further comprises.

In addition, the first metal film is formed using a thickness of 50 to 2,000 kPa using TaN or TiN.

In addition, the dielectric film is formed using a thickness of 50 to 1,000 내지 by using any one of SiN, SiC and Ta ₂ O ₅ .

In addition, the second metal film is formed using a thickness of 100 to 3,000 kPa using TaN or TiN.

In addition, the hard mask film is characterized in that it is formed to a thickness of 100 to 3,000 kPa using SiN or SiC.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, and a description of overlapping parts will be omitted.

Example 1

2A to 2G are cross-sectional views illustrating processes of forming a MIM capacitor in a semiconductor device according to a first embodiment of the present invention.

A method of forming a MIM capacitor of a semiconductor device according to a first embodiment of the present invention first provides a semiconductor substrate 200 having a predetermined substructure (not shown) including a transistor or the like, as shown in FIG. 2A. Next, a first interlayer insulating film 201 is formed on the semiconductor substrate 200. The first interlayer insulating film 201 is formed of an insulating material of an oxide type, in particular, an insulating material having a low dielectric constant (low k). Next, a trench (not shown) for forming a lower metal wiring in the first interlayer insulating film 201 is formed. Subsequently, a metal material, for example, copper (Cu), is embedded in the trench to form the first metal wire 202.

Next, a diffusion barrier film 203 and a second interlayer insulating film 204 are successively formed on the first interlayer insulating film 201 including the first metal wiring 202. The diffusion barrier 203 is formed to a thickness of 100 to 1,000 Å using SiC or SiN. In addition, the second interlayer insulating film 204 is formed to a thickness of 100 to 5,000 kW using an insulating material of an oxide type, in particular, an insulating material having a low dielectric constant (low k).

Although not shown in the drawings, a photoresist pattern (not shown) is formed on the second interlayer insulating layer 204 to expose an alignment key forming region, and the photoresist pattern is used as an etching mask. The two interlayer insulating film 204, the diffusion barrier 203 and the first interlayer insulating film 201 are etched by a predetermined thickness to form an alignment key (not shown), and then the photosensitive film pattern is removed. The etching process for forming the alignment key is performed under conditions in which the selectivity between the nitride film and the oxide film is reduced by using CHF ₃ , CF ₄ , O _2, and Ar gas, and the like, so that the etching of the diffusion barrier 203 is not stopped and the lower portion thereof is not stopped. Etching is performed to a predetermined depth of the first interlayer insulating film 201.

Next, as shown in FIG. 2B, a first photosensitive film pattern 205 is formed on the second interlayer insulating film 204 to expose a portion corresponding to a portion of the first metal wire 202. Next, the second interlayer insulating layer 204 is etched using the first photoresist pattern 205 as an etching mask to expose a portion of the diffusion barrier 203. The etching process of the second interlayer insulating film 204 is performed using CHF ₃ , CF ₄ , O _2, and Ar gas.

Then, as shown in FIG. 2C, the first photoresist pattern 205 is removed. In this case, the first photoresist pattern 205 is removed using O ₂ plasma or O ₃ . In the state in which the first photoresist layer pattern 205 is removed, the diffusion barrier layer 203 exposed by the second interlayer dielectric layer 204 remaining after the etching using CHF ₃ , CF ₄ , O _2, and Ar gas or the like. The portion is etched to form a trench 206 that exposes a portion of the first metallization 202. In this case, since the diffusion barrier 203 is etched while the first photoresist layer pattern 205 is removed, the upper portion of the second interlayer dielectric layer 204 is partially etched to have a thickness smaller than the initial thickness. Subsequently, a wet cleaning process is performed to remove Cu polymer or the like generated on the surface of the first metal wire 202 exposed by the trench 206.

Next, although not shown in the drawings, a barrier film (not shown) and a seed layer (not shown) are formed over the entire structure including the trench 206, and then a copper film is embedded to fill the trench 206. Not shown). In this case, the barrier film is formed by depositing Ta or TaN by physical vapor deposition (PVD).

Subsequently, the copper film is chemical mechanically polished (CMP) until the second interlayer insulating film 204 is exposed, and as shown in FIG. 2D, the first metal wiring ( A conductive plug 207 is electrically connected to a portion of 202.

Thereafter, as shown in FIG. 2E, the first metal film 208, the dielectric film 209, and the upper electrode for forming the lower electrode of the MIM capacitor on the second interlayer insulating film 204 including the conductive plug 207. The second metal film 210 and the hard mask film 211 are sequentially formed. Here, the first metal film 208 is formed to a thickness of 50 to 2,000 GPa using TaN or TiN, the dielectric film 209 is 50 to 1,000 GPa using a thickness of SiN, SiC or Ta ₂ O ₅ The second metal film 210 is formed to have a thickness of 100 to 3,000 Å using TaN or TiN. In addition, the hard mask film 211 is formed to a thickness of 100 to 3,000 kPa using SiN or SiC.

Next, a second photoresist layer pattern 212 covering a MIM capacitor formation region (not shown) is formed on the hard mask layer 211.

Next, as shown in FIG. 2F, the hard mask layer 211, the second metal layer 210, and the dielectric layer 209 are patterned by an etching process using the second photoresist layer pattern 212 as a mask. The etching process of the hard mask layer 211, the second metal layer 210, and the dielectric layer 209 is performed by combining CF ₄ , CHF ₃ , Ar, and O ₂ gases. In FIG. 2F, reference numeral 209a not shown in FIG. 2F denotes a patterned dielectric film, 210a denotes a patterned second metal film (hereinafter referred to as an “upper electrode”), and 211a denotes a patterned hard mask film, respectively.

Next, the second photosensitive film pattern 212 is removed using O ₂ plasma or O ₃ , and then a cleaning process is performed. In this case, the cleaning process may be performed before removing the second photoresist layer pattern 212.

Although not illustrated in the drawing, when the second metal film 210 is etched using the second photoresist film pattern 212, the elements forming the photoresist film and the metal film react with each other to form the patterned films 209a and 210a. , A large amount of metallic polymer is generated on the surface of 211a), and the metallic polymer is not completely removed even after the cleaning process is performed.

Next, as illustrated in FIG. 2G, the first metal layer 208 is patterned and electrically connected to the conductive plug 207 by an etching process using the patterned hard mask layer 211a as a mask. The MIM capacitor 213 including the lower electrode 208a, the dielectric film 209a, and the upper electrode 210a is formed.

Here, in the etching process of the first metal film 208, the etching selectivity of the first metal film 208 and the hard mask film 211 using a mixed gas of Cl ₂ and BCl ₃ is 1: 1 to 1: It is carried out under the condition of about 15 degrees. Accordingly, when the first metal layer 208 is etched, an upper portion of the patterned hard mask layer 211a is etched by a predetermined thickness so that the final thickness thereof is smaller than the initial formation thickness, such as 500 to 2,000 mm 3. do.

In addition, as the etching process of the first metal layer 208 proceeds, the metallic polymer generated in the previous step is removed. That is, the second photoresist layer pattern 212 causing the generation of the metallic polymer is removed, and then the etching process of the first metal layer 208 is performed using the patterned hard mask layer 211a. While removing the metallic polymer, it is possible to further prevent the metallic polymer from being generated.

3 is a plan view photograph of a MIM capacitor formed according to an embodiment of the present invention, and it can be seen that no metallic polymer remains on the surface of the MIM capacitor. Therefore, leakage current generation of the MIM capacitor 213 by the metallic polymer can be prevented, and the characteristics of the MIM capacitor 213 can be improved. In addition, a film (not shown) subsequently deposited on the MIM capacitor 213 can be prevented from being lifted by the metallic polymer.

Example 2

4A to 4C are cross-sectional views illustrating processes of forming a MIM capacitor of a semiconductor device according to a second exemplary embodiment of the present invention.

In the method of forming a MIM capacitor of a semiconductor device according to the second embodiment of the present invention, as shown in FIG. 4A, the first metal film 308, the dielectric film 309, and the upper electrode for forming the lower electrode of the MIM capacitor are first shown in FIG. 4A. The steps up to forming the second metal film 310, the hard mask film 311, and the second photosensitive film pattern 312 are applied in the same manner as in the above-described first embodiment. Therefore, the description of the same parts as the first embodiment in the configuration of the second embodiment will be omitted.

Next, as shown in FIG. 4B, after the hard mask layer 311 is patterned by an etching process using the second photoresist layer pattern 312 as a mask, the second photoresist layer pattern 312 is removed. . Here, a cleaning process is performed before or after removing the second photoresist pattern 312. Meanwhile, reference numeral 311a not described in FIG. 4B denotes a patterned hard mask film.

Next, as shown in FIG. 4C, the second metal film 310, the dielectric film 309, and the first metal film 308 are patterned by an etching process using the patterned hard mask film 311 a as a mask. The MIM capacitor 313 is electrically connected to the conductive plug 307 and includes a lower electrode 308a, a dielectric film 309a, and an upper electrode 310a.

As described above, after patterning only the hard mask film 210 with the second photoresist pattern 312 causing the generation of the metallic polymer and removing the second photoresist pattern 312, the patterned hard mask layer 211a is removed. By etching the second metal film 310, the dielectric film 309, and the first metal film 308 using a mask, it is possible to prevent the elements of the photosensitive film and the metal film from reacting with each other. Therefore, it is possible to prevent the generation of the metallic polymer on the surface of the MIM capacitor 313.

Example 3

5A through 5C are cross-sectional views illustrating processes of forming a MIM capacitor of a semiconductor device according to a third exemplary embodiment of the present invention.

In the method of forming a MIM capacitor of a semiconductor device according to the third embodiment of the present invention, as shown in FIG. 5A, the first metal film 408, the dielectric film 409, and the upper electrode for forming the lower electrode of the MIM capacitor are first shown in FIG. 5A. The steps up to forming the second metal film 410, the hard mask film 411, and the second photosensitive film pattern 412 are applied in the same manner as in the above-described first and second embodiments. Therefore, the description of the same parts as those of the first and second embodiments in the configuration of the third embodiment will be omitted.

Next, as shown in FIG. 5B, the hard mask layer 411, the second metal layer 410, the dielectric layer 409, and the first metal may be etched using the second photoresist layer pattern 412 as a mask. The film 408 is patterned to form the MIM capacitor 413. The MIM capacitor 413 is electrically connected to the conductive plug 407 and includes a lower electrode 408a, a dielectric film 409a, and an upper electrode 410a. In this case, reference numeral 411a which is not described in FIG. 5B denotes a patterned hard mask layer. Subsequently, the second photoresist layer pattern 412 is removed. Here, the cleaning process is performed before or after removing the second photoresist pattern 412.

Although not shown in the drawing, as described above, when the second and first metal films 410 and 408 are etched using the second photoresist film pattern 412, the respective components constituting the photoresist film and the metal film are etched. The elements react with each other to generate a large amount of metallic polymer on the surface of the MIM capacitor 413, and the metallic polymer remains completely removed even after the cleaning process is performed.

Next, as shown in FIG. 5C, a dry etching process is performed on the entire surface of the substrate including the MIM capacitor 413 to remove the remaining metallic polymer.

As described above, after forming the MIM capacitor 413, removing the second photoresist pattern 412, and further performing a dry etching process, the metallic polymer remaining on the surface of the MIM capacitor 413 may be removed. have.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

As described above, according to the method for forming a MIM capacitor of a semiconductor device according to the present invention, after etching the hard mask film, the second metal film for forming the upper electrode, and the dielectric film using the photoresist pattern as a mask, the photoresist pattern is After the removal, the etching process of the first metal film for forming the lower electrode is performed without using the photoresist pattern, thereby removing the metallic polymer generated during the etching process up to the dielectric layer using the photoresist pattern and preventing the occurrence of additional metallic polymer. Can be.

In addition, only the hard mask film is etched using the photoresist pattern as a mask, and after the photoresist pattern is removed, the second metal film, the dielectric film, and the first metal film are etched without using the photoresist pattern, thereby forming the photoresist film and the metal film. Each element can be prevented from reacting with each other to prevent the generation of metallic polymers.

In addition, the hard mask film, the second metal film, the dielectric film, and the first metal film are etched using the photoresist pattern as a mask to form a MIM capacitor, and then additionally performed a dry etching process to generate the MIM capacitor. Metallic polymers can be removed.

As a result, the present invention can prevent the leakage current of the MIM capacitor due to the metallic polymer to improve the characteristics of the MIM capacitor, and can prevent the phenomenon of the subsequent deposition of the film deposited on the MIM capacitor.

Claims (9)

delete delete Providing a semiconductor substrate provided with a conductive plug; Sequentially forming a first metal film, a dielectric film, a second metal film, a hard mask film, and a photoresist pattern covering the MIM capacitor formation region on the semiconductor substrate; Forming a MIM capacitor electrically connected to the conductive plug by patterning the hard mask film, the second metal film, the dielectric film, and the first metal film by an etching process using the photoresist pattern as a mask; Removing the photoresist pattern; And And performing a dry etching process on the entire surface of the substrate including the MIM capacitor to remove the metallic polymer generated during the formation of the MIM capacitor. delete The method of claim 3, wherein Before or after removing the photoresist pattern, A method of forming a MIM capacitor of a semiconductor device, characterized in that it further comprises the step of performing a cleaning process. The method of claim 3, wherein The first metal film is formed using a TaN or TiN to a thickness of 50 to 2,000 Å MIM capacitor forming method of a semiconductor device. The method of claim 3, wherein The dielectric film is formed using a SiN, SiC and Ta ₂ O ₅ to a thickness of 50 to 1,000 Å MIM capacitor forming method of a semiconductor device. The method of claim 3, wherein The second metal film is formed using a TaN or TiN to a thickness of 100 to 3,000 kPa MIM capacitor forming method of a semiconductor device. The method of claim 3, wherein The hard mask film is formed using a SiN or SiC to a thickness of 100 to 3,000 kPa MIM capacitor formation method of a semiconductor device.

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