JP2008053264A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor structure wherein high electric field stress can be reduced in a capacitor structure that is provided with a dielectric film made of high dielectric and a ferroelectric material, in a plasma process including contact etching. <P>SOLUTION: A method includes a step of forming a first electrode 111; a step of forming a dielectric layer 113 constituting a charge capacity element on the first electrode 111; a step of forming a second electrode 114 on the dielectric layer 113; a step of covering the charge capacity element with an insulation film 118; a step of forming contact holes 120 and 121 that reach either of the first and second electrodes, in the insulation film 118 by plasma etching; a step of forming a dummy hole that reaches the other of the first and second electrodes, simultaneously when the contact holes 120 and 121 are formed; and a step of forming wiring 122 that is electrically connected with either thereof by means of the contact hole. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a structure and a manufacturing method of a semiconductor device, and more particularly, a semiconductor integrated circuit device including a high dielectric material and a ferroelectric material as a charge capacitance element.

There are the following documents on the general remarks regarding a method of manufacturing a ferroelectric memory device (FeRAM: Ferroelectric Random Access Memory) that uses a ferroelectric material as a charge capacitance element (capacitor).
Kinam kim and Yoon J. Song: “Integration technology for ferroelectric memory devices”, Microelectronics Reliability, Vol.43, pp.385-398 (2003).

  In the above document, the capacitor element has a structure in which a thin dielectric material layer is inserted between an upper electrode and a lower electrode made of a conductive material. It utilizes dielectric polarization generated when a voltage is applied between both electrodes, and is applied to an electronic device having various functions by utilizing a phenomenon that charges are accumulated in an element due to dielectric polarization. In a capacitor using a ferroelectric material, the direction of spontaneous polarization can be arbitrarily changed according to the polarity of the applied voltage, and the polarization state is maintained even when the applied voltage is removed. Therefore, FeRAM which is a nonvolatile memory device It is used for.

There are many kinds of ferroelectric materials depending on the purpose of application. As materials applied to FeRAM, PZT (Pb (Zr _1−x Ti _x ) O ₃ ), SBT (SrBi ₂ Ta ₂ O) are used. ₉ ), BLT ((Bi _1−x La _x ) ₄ Ti ₃ O ₁₂ ) and the like have been used or studied. These ferroelectric thin films are formed by sputtering deposition, application of dissolved organic solvent such as sol-gel method, MOCVD (metal organic chemical vapor deposition), etc., but in any case, good spontaneous polarization is possible. In order to obtain the ideal crystal structure, high temperature treatment at about 450 ° C. to 850 ° C. is required.

As the electrode material, Pt (platinum), which is resistant to high-temperature processes and chemically stable, is often used, but for the purpose of suppressing the generation of oxygen vacancies in the ferroelectric crystal that cause deterioration of polarization characteristics. Metal oxides such as IrO ₂ and SrRuO ₃ may be used. In FeRAM, a ferroelectric capacitor is connected to a MOS-FET (Metal-Oxide-Semiconductor Field Effect Transistor) serving as a switching device to constitute a memory cell. The conventional CMOS structure / process can be used as it is for the portion excluding the ferroelectric capacitor serving as the storage node. In this case, an element structure and a manufacturing process that are consistent with the inherent process such as the high-temperature film formation described above are required.

  Although the circuit of FeRAM is composed of a MOS-FET element layer and a number of wiring layers, a ferroelectric capacitor may be arranged in any layer in terms of the circuit configuration. As a circuit of FeRAM, a CUB (capacitor-under-bitline) type in which a capacitor is arranged below a bit line connecting two-dimensionally integrated memory cell arrays, or a COB (capacitor-over) arranged in an upper layer of a bit line is used. -bitline) type. Furthermore, recently, it has changed along with the development of FeRAM, such as a CMVP (capacitor-on-metal / via-stacked-plug) in which capacitor elements are arranged in an upper layer after all wiring layers are fabricated.

  In the CUB type structure, a capacitor is formed on an insulating film having no connection (contact plug) to a MOS-FET, a contact hole is opened, local wiring is performed, and a plug (poly-Si, W, etc.) is embedded. For this reason, there is no oxidation of the plug in the high temperature treatment and the process is relatively easy, but there is a problem that the area of the memory cell becomes large and the integration is difficult.

From the viewpoint of miniaturization and integration of the memory cell, the COB type (stacked structure) laminated directly on the contact plug connected to the terminal (diffusion layer) of the MOS-FET is advantageous. However, it is necessary to lay a barrier metal such as Ir / IrO ₂ / TiAlN under the capacitor to prevent plug oxidation during high-temperature processing during the formation of the ferroelectric film. In addition, the ferroelectric crystal, which is a metal oxide containing a transition metal, has a remarkable characteristic deterioration due to generation of oxygen vacancies due to a reaction with a reducing element, particularly hydrogen. For this reason, in order to protect the ferroelectric film from hydrogen diffusion in subsequent processes such as film deposition and etching after capacitor formation, a sealed structure that wraps the capacitor with a protective layer such as TiO ₂ , SiON, or Al ₂ O ₃ is essential. It is. As a result, miniaturization can be achieved, but processing difficulty increases.

  Since the CMVP type has a stack structure similar to the COB type, it is advantageous for miniaturization of memory cells, and in addition to forming a ferroelectric capacitor after forming all the structures up to the multilayer wiring layer, it depends on the process. It is characterized by little deterioration of the ferroelectric material.

  The element structure as described above is formed by depositing various layers of various thin films, transferring elements and wiring patterns by lithography (resist pattern formation), and various materials based on the resist pattern, This is done by plasma etching of the structure. Well-known techniques can be adopted as methods and detailed conditions of these various manufacturing processes.

  In a ferroelectric capacitor using the above structure and manufacturing method, dry etching using plasma is generally used to form an element structure. For this reason, a ferroelectric film which is a chemically structurally fragile material may cause a problem of plasma-induced damage, particularly film quality deterioration or dielectric breakdown due to charge-up. In particular, in the future high integration and low operating voltage, it is essential to reduce the thickness of the ferroelectric capacitor film, and film quality deterioration and dielectric breakdown due to charge-up will become more serious.

  The principle of this problem will be described with reference to FIG. FIG. 1 shows a ferroelectric capacitor structure having a COB type structure. Furthermore, the charge-up state in the plasma etching apparatus in the contact hole etching process to the upper electrode is schematically shown.

  The ferroelectric capacitor 301 is processed by plasma etching, and a resist mask pattern 306 of a contact hole is formed by photolithography on an interlayer insulating film (silicon oxide film) 305 that covers the ferroelectric capacitor 301. Thereafter, contact hole etching is performed by plasma etching. FIG. 1 shows a state at the time of overetching after the etching end point.

  The plasma is generated and maintained by ionization caused by collision between electrons accelerated by input power and gas atoms / molecules in the gas phase, so that ions 307 having positive charges and electrons 308 having negative charges are mixed. It has become. At this time, the electrons 308 having a much smaller mass than the positive ions 307 diffuse immediately. For this reason, the wall surface is automatically biased to a negative potential as seen from the plasma so that the positive and negative charge inflows into the wall surface (boundary surface in contact with the plasma) in the steady state are equal. An acceleration electric field is generated for deceleration and positive ions (self-bias voltage). In plasma etching, positive ions are incident on a substrate perpendicularly by a self-bias voltage, so that anisotropic etching is achieved, enabling fine processing in a semiconductor manufacturing process.

In order to obtain higher anisotropy and etch rate, it is general to apply RF bias power to the electrode 309 holding the substrate to obtain a higher self-bias voltage. The silicon oxide film material as in the example of FIG. 1 is processed by plasma using CF ₃ ⁺ ions generated by using fluorocarbon (CxFy) gas plasma, CF ₂ radicals, or the like. In this system, since the etching reaction rate greatly depends on the incident energy of CF ₃ ⁺ ions, a condition that induces a high self-bias voltage of about 100 V to several hundreds V is used. For this reason, the sample substrate in contact with the plasma has a potential difference of about 100 V to several hundreds V with respect to the plasma. At this time, if the in-plane distribution of the plasma in contact with the substrate is uniform, the entire substrate is almost at the same potential, and there is no problem of charge-up. However, if a large potential difference is locally generated depending on the structure and material of the element, there is a problem.

  In the case of the COB type or the CMVP type shown in FIG. 1, the ferroelectric capacitor lower electrode 304 is in electrical contact with the silicon substrate (MOS transistor diffusion layer) 311 through the contact plug 310, so that it is almost equal to the substrate potential. Will be equal. On the other hand, since the upper electrode 302 is in contact with the plasma 313 through the contact hole 312, the potential is different from the substrate potential. In the narrow contact hole, the positive ions accelerated by the self-bias voltage are incident vertically, and thus reach the hole bottom (that is, the upper electrode). On the other hand, since electrons having a negative charge are incident in a random direction against the self-bias voltage, it is difficult to reach the bottom of the hole.

  For this reason, positive / negative charge separation, that is, charge-up occurs, and the hole bottom (upper electrode 302) has a positive voltage compared to the substrate potential (lower electrode 304). As a result, voltage stress is applied to the ferroelectric capacitor film 303. This is called charge-up due to the electron shielding effect, but this value has a larger effect as the hole width is narrower and deeper. In calculations that focus only on the motion of charged particles, the charge-up potential due to the electron shielding effect may rise up to the same level as the self-bias voltage. In actual plasma etching, there is a leakage of accumulated charges on the substrate surface, so that the charge-up potential is about one digit lower than the self-bias voltage. However, even if the stress voltage is estimated at a value of about 50 V, if the ferroelectric film is thinned to a thickness of 50 nm, a high electric field of 10 MV / cm is applied.

  As described above, in the ferroelectric capacitor structure 301 formed by stacking on the contact plug 310, a high electric field is generated between the upper and lower electrodes during overetching of the contact hole etching, and a high density leak current flows in the film. In addition, the film quality is deteriorated, or a significant crystal structure defect is caused by dielectric breakdown. In addition, in FIG. 1, the state at the time of over-etching of the contact hole is shown for the sake of simplicity, but a leak current is generated as the insulating film thickness at the bottom of the hole is reduced during the progress of etching. Similar problems occur from the stage before the etching end point. When the degree of such film quality deterioration is small, the crystal structure is recovered by heat treatment after etching, but when the degree of defects is significant, complete recovery becomes difficult and the polarization characteristics of the ferroelectric capacitor are greatly deteriorated. This causes a decrease in yield in device manufacturing, deterioration of product reliability, and deterioration of device performance.

  The present invention has been made in view of the above situation, and reduces high electric field stress in a capacitor structure using a high dielectric material and a ferroelectric material as a dielectric film in a plasma process such as contact etching. The object is to provide a possible capacitor structure.

  Another object of the present invention is to provide a method of manufacturing a capacitor structure capable of reducing high electric field stress of a capacitor structure using a high dielectric material and a ferroelectric material as a dielectric film in a plasma process such as contact etching. To do.

  In order to solve the above problems, a method of manufacturing a semiconductor device according to a first aspect of the present invention includes a step of forming a first electrode constituting a charge capacitance element; and the charge capacitance on the first electrode. Forming a dielectric layer constituting the element; forming a second electrode constituting the charge capacitance element on the dielectric layer; and covering the charge capacitance element with an insulating film; Forming a contact hole reaching one of the first and second electrodes in the insulating film by plasma etching; forming a dummy contact hole reaching the other electrode of the first and second electrodes; Forming simultaneously with the formation of the contact hole; and forming a wiring electrically connected to the one electrode through the contact hole.

  According to a second aspect of the present invention, there is provided a semiconductor device comprising: an integrated element region layer comprising a transistor and an element isolation region on a semiconductor substrate; an insulating film layer formed on the integrated element region layer; A charge capacitance element formed on the film layer; and an interlayer insulating film deposited on the charge capacitance element formation surface. The charge capacitance element includes a lower electrode, an upper electrode, and a dielectric layer sandwiched between these two electrodes. In addition, a part of the lower electrode protrudes outside the charge capacitance element and is formed to have a height equal to or higher than the upper surface of the upper electrode. Further, a contact hole penetrating the upper electrode surface and a dummy contact hole penetrating the raised portion of the lower electrode are simultaneously formed by plasma etching with the same inner diameter. Furthermore, a wiring material is embedded in the contact hole and the dummy contact hole, and a wiring pattern is formed by plasma etching after the wiring material is deposited on the interlayer insulating film.

  According to the present invention, a part of the lower electrode is raised and the height of the surface of the protrusion is made equal to the height of the surface of the upper electrode, and the same shape is formed on the protrusion when plasma etching the upper electrode contact hole. The dummy contact holes are simultaneously opened. For this reason, the upper and lower electrodes come into contact with the plasma in the same state after the end of the contact hole etching. Further, with this structure, when plasma etching is performed on the plate line connected to the upper electrode, the upper electrode and the lower electrode are short-circuited until the unnecessary part of the plate line material is etched. Furthermore, at the time of overetching removal after the plate line material is removed by etching, the surface of the lower electrode protrusion and the upper electrode are short-circuited via plasma.

  Since the etching proceeds simultaneously with the dummy contact hole connected to the lower electrode during the plasma etching of the upper electrode contact hole, the charge-up potential due to the electron shielding effect in the fine hole is balanced between the upper and lower electrodes. As a result, the electric field applied to the capacitor insulating film is remarkably reduced, and deterioration of the capacitor insulating film due to high electric field stress can be prevented. In plasma etching of the wiring connected to the upper electrode, the upper electrode is connected to the plasma via the wiring material, and the lower electrode is in contact with the plasma via the dummy contact hole. Therefore, the charge-up potential during plasma etching is reduced as compared with the case where there is no dummy contact, and it is possible to reduce deterioration of the capacitor insulating film due to electric field stress.

  The present invention can be applied to a structure of a CMVP (capacitor-on-metal / via-stacked-plug) type. Here, CMVP is a structure in which capacitor elements are arranged in an upper layer after all wiring layers are formed. Since the CMVP type adopts a stack structure, it is advantageous for miniaturization of the memory cell, and in addition to forming the ferroelectric capacitor after forming all the structures up to the multilayer wiring layer, There is little deterioration.

  2A to 6K show the structure of a ferroelectric capacitor and its manufacturing process according to an embodiment of the present invention. In this embodiment, the ferroelectric capacitor structure and the manufacturing process are characteristic, and the details of other structures and processes in the fabrication of the FeRAM device can employ well-known structures and processes, which hinder the explanation. Many are omitted unless otherwise noted.

FIG. 2A shows a state where an interlayer insulating film (silicon oxide film: SiO ₂ ) 104 thicker than usual is deposited after the formation of the MOS transistor constituting the FeRAM device, and the surface is flattened. In the figure, reference numeral 101 denotes a gate electrode, 102 denotes a source / drain diffusion layer, and 103 denotes an element isolation region. In this embodiment, the SiO ₂ film 104 is deposited by low pressure chemical vapor deposition (LP-CVD) using O ₃ gas and TEOS (tetraethoxysilane). After the formation of the SiO ₂ film 104, an annealing process is performed. Surface planarization is performed by chemical mechanical polishing (CMP).
Mechanical Polishing).

Next, a photoresist pattern 105 is formed by i-line lithography, and using this as a mask, a step 106 is formed in the interlayer insulating film 104 by plasma etching mainly using CHF ₃ and CF ₄ gases (FIG. 2B )). At this time, the step 106 is processed by adjusting the etching time so that the step 106 is deeper than the total thickness of the upper electrode film thickness and the ferroelectric film thickness of the ferroelectric capacitor multilayer structure described later. . 2 to 6 show only a cross section in one direction, the raised shape by the step 106 has a rail-like structure extending in a direction perpendicular to the drawing.

  Next, a contact hole is opened in a region where a capacitor is formed, and a contact plug 107 is embedded (FIG. 2C). In forming the contact plug 107, first, a resist pattern is formed by KrF excimer laser lithography, and a contact hole is opened in the interlayer insulating film 104 by plasma etching. Next, after performing contact implantation and activation annealing, a Ti / TiN (titanium / titanium nitride) laminated film is deposited by plasma CVD. Next, W (tungsten) is deposited on the entire surface of the substrate by CVD, and then the entire surface is etched (etched back) by plasma etching so as to leave the W plug only in the contact hole.

Thereafter, the multilayer barrier metal 108-110 and the lower electrode 111 of the ferroelectric capacitor are stacked and deposited (FIG. 3D). First, after TiAlN (titanium nitride aluminum) 108, Ir (iridium) 109, and IrO ₂ (iridium oxide) 110 are sequentially stacked by reactive sputtering, a Pt (platinum) 111 film serving as a lower electrode is formed.

Next, a thick film resist pattern 112 is formed, and using this as an etching mask, the lower electrode 111 is processed by plasma etching using Cl ₂ gas (FIG. 3E). Regarding the etching for forming the lower electrode 111, an ECR plasma etching apparatus is used, and a Cl ₂ gas flow rate of 20 to 50 sccm, a gas pressure of 1 to 3 mTorr, and an ECR discharge power of 0.5 for a wafer (substrate) having a diameter of 5 inches. Conditions of ˜1.5 kW, bias power applied to the wafer stage of 600 kHz, 50 to 150 W, wafer stage temperature of about 30 ° C., chamber inner wall temperature of about 150 ° C. are suitable. At this time, since the etch rate selection ratio between Pt, which is the lower electrode 111, and the resist pattern 112 is about 1/5, it is preferable to use a thick film resist 112 that is about 10 times the electrode film thickness. Further, since the etch rate between the Pt electrode 111 and the underlying barrier film IrO ₂ film 110 has a selection ratio of about 3, the etching can be stopped at the IrO ₂ layer. If the over-etching is set to a small amount in order to stop the etching on the IrO ₂ film 110, a thick deposited film remains on the resist 112 and the Pt pattern side wall, and this deposited film is removed by cleaning with 30% concentration hydrochloric acid. . Thereafter, the resist pattern 112 is removed by ashing with oxygen plasma (not shown).

  Next, an SBT film 113 to be a ferroelectric film is deposited by metal organic chemical vapor deposition (MO), crystallization annealing is performed, and then a Pt film 114 to be an upper electrode is formed by sputtering. Deposited (FIG. 4F).

Next, TiN (titanium nitride) 115 is formed by reactive sputtering. Thereafter, a SiO ₂ film 116 is laminated by plasma TEOS-CVD, and an etching mask for the upper electrode pattern is formed by photolithography and plasma etching (FIG. 4G). The SiO ₂ film 116 is etched by plasma using a mixed gas of C ₄ F ₈ , CO, and Ar. On the other hand, the TiN film 115 is etched by plasma using a BCl ₃ and Cl ₂ mixed gas.

Next, the upper electrode Pt film 114 and the ferroelectric SBT film 113 are processed using the structure (115, 116) as a mask. In this step, the IrO ₂ layer 110 and the Ir layer 109 under the lower electrode are further removed (FIG. 5H). In this etching step, the wafer stage is heated to 300 to 450 ° C. using a magnetic field application type two-frequency excitation parallel plate type reactive ion etching apparatus. In the etching of the upper electrode Pt layer 114, a mixed gas of Cl ₂ , O ₂ , and Ar is used, the ratio of Cl ₂ gas to O ₂ gas is 1: 3 to 1: 1, the total gas flow rate is 10 to 50 sccm, and the total gas flow rate The dilution ratio of Ar with respect to is preferably set to about 10 to 50%. The gas pressure is 1 to 3 mTorr, plasma excitation power 0.5 to 1.5 kW, and substrate bias power 50 to 150 W.

In the etching of the ferroelectric SBT layer 113, the etching is continuously performed while changing only the gas ratio of the etching conditions. In this case, lowering the flow rate ratio of _{O 2,} the flow ratio of Cl ₂ and _{O 2} 3: 1 or less or is etched under a condition excluding the _{O 2} gas. Simultaneously with the completion of the etching of the SBT layer 113, the gas flow ratio is again returned to the same as the etching condition of the upper electrode 114, and the lower IrO ₂ layer 110 and the Ir layer 109 are continuously etched. Switching of these gas flow conditions can be performed automatically while monitoring the material to be etched by an end point detector using spontaneous emission spectroscopy of plasma.

In the continuous etching of the laminated structure of the Pt film 114, the SBT film 113, the IrO ₂ film 110, and the Ir film 109, most of the film thickness of the SiO ₂ film 116 as the upper layer of the laminated mask is removed by etching at the etching end point of the Pt film 114, It is necessary to adjust the film thickness so that it is completely removed during the next etching step of the SBT film 113. After the etching step of the SBT film 113, the TiN film 115 serving as a mask and the lowermost TiAlN film 108 undergo an oxidation reaction in a gas plasma containing O ₂ at a high temperature, and serve as a mask and an etching stopper having a very high etching resistance. Works. Therefore, the stacked structure etching can be finished on the thin TiAlN film.

Thereafter, the mask TiN film 115 and the barrier metal TiAlN film 108 are removed by plasma using Cl ₂ gas (not shown). At this point, the ferroelectric capacitor structure is completed, but the capacitor has a structure in which a part of the lower electrode 111 is raised and the upper surface of the protruding portion 117 is almost the same height as the upper electrode 114. Although the upper surface of the protruding portion 117 may be deformed by etching, there is usually no functional problem. After the capacitor multilayer structure is etched, annealing is performed for a short time at a temperature of 750 ° C. or higher in an O ₂ atmosphere in order to recover the etching damage that has entered the SBT film 113.

Next, an SiO ₂ interlayer insulating film 118 is formed by plasma TEOS-CVD, and the surface is flattened by CMP. Thereafter, a resist pattern 119 for opening the upper electrode contact hole is formed by KrF lithography, and the contact hole is etched using this resist pattern as a mask. The contact holes are laid out so that both the upper electrode surface 120 becomes the bottom surface and the projection surface 121 raised from the lower electrode 111 becomes the bottom surface (FIG. 5I). It is preferable that the hole and the contact hole reaching the lower electrode 111 have the same inner diameter.

  As described above, when the contact hole reaching the lower electrode 111 is formed in addition to the contact hole reaching the upper electrode 114, the etching rate in both the contact holes is equal, and the projection surface 121 Since the height is equal to or higher than the electrode surface 120, only the upper electrode 114 is not exposed to the plasma alone during the overetching step from just before the etching end point.

Next, after the resist mask 119 is removed by the ashing principle using O ₂ plasma, an annealing process is performed for a short time at a temperature of 750 ° C. or higher in an O ₂ atmosphere in order to recover etching damage that has entered the SBT film 113 (FIG. Not shown).

  Next, in order to form a wiring (plate line), an aluminum layer 122a is deposited by sputtering (FIG. 6J). Thereafter, a wiring pattern 122 is formed by KrF lithography and plasma etching (FIG. 6K).

  When the aluminum layer 122a is deposited, aluminum is buried in both the contact holes opened in the upper electrode surface 120 and the lower electrode projection surface 121, so that the upper electrode 114 and the lower electrode 111 are electrically short-circuited. Further, when the plate line 122 is etched (molded), electric charge flows from the plate line 122 exposed to plasma, but the upper and lower electrodes 111 and 114 are short-circuited, so that an electric field is applied to the ferroelectric capacitor. First, the stress current flowing through the ferroelectric material 113 during etching is very small. At the time of over-etching after the etching progresses and the plate line 122 is separated, the connection between the upper and lower electrodes 111 and 114 is separated, but since it is electrically connected via plasma, it is not completely insulated, The electric field applied to the ferroelectric capacitor is not so large.

  After the process described in detail above, processes such as a multilayer wiring process, passivation film deposition, pad formation, etc. are continued. Note that a known method can be adopted for such a process, and a description thereof is omitted here.

  In the present embodiment described above, as shown in FIG. 5I, a part of the lower electrode 111 is raised and the height of the surface 121 of the projection 117 is equal to the height of the surface 120 of the upper electrode 114. I have to. Then, when plasma etching the upper electrode contact hole, a dummy contact hole having the same shape is simultaneously opened in the protrusion 117. Therefore, the upper and lower electrodes 111 and 114 come into contact with the plasma in the same state after the contact hole etching end point.

  Further, as shown in FIG. 6K, when plasma etching is performed on the plate line 122 connected to the upper electrode 114 by this structure, the upper electrode 114 and the lower electrode 111 are etched with an unnecessary portion of the plate line material 122a. It becomes the structure which short-circuits until. Further, at the time of overetching removal after the plate line material 122a is removed by etching, the projection surface 121 of the lower electrode 111 and the upper electrode 114 are short-circuited via plasma.

  According to this embodiment, since the dummy contact hole connected to the lower electrode 111 is etched at the same time during the plasma etching of the contact hole of the upper electrode 114, the charge-up potential due to the electron shielding effect in the fine hole is between the upper and lower electrodes. Will be balanced. As a result, the electric field applied to the capacitor insulating film 113 is remarkably reduced, and deterioration of the capacitor insulating film 113 due to high electric field stress can be prevented. Further, at the time of plasma etching of the wiring 122 connected to the upper electrode 114, the upper electrode 114 is connected to the plasma through the wiring material 122a, and the lower electrode 111 is in contact with the plasma through the dummy contact hole. For this reason, the charge-up potential during plasma etching is reduced as compared with the case where there is no dummy contact, and deterioration of the capacitor insulating film 113 due to electric field stress can be reduced.

In the embodiments of the present invention, the structure and manufacturing method of FeRAM having a ferroelectric capacitor using SBT have been described. However, the present invention is not limited to this, and other ferroelectrics such as PZT and BLT are used. It is also effective for FeRAM using materials. In addition to FeRAM, it is effective for devices such as DRAM using a high dielectric material and many other electronic devices having a capacitor structure. Dielectric materials are known to have a reduced dielectric strength due to a negative correlation with their dielectric constant, and the present invention is expected to be effective in many new material devices to be developed in the future.

FIG. 1 is an explanatory diagram used to illustrate problems with the prior art. 2A to 2C are cross-sectional views illustrating a part of the manufacturing process of the FeRAM according to the embodiment of the present invention. 3D and 3E are cross-sectional views showing a part of the manufacturing process of the FeRAM according to the embodiment of the present invention. 4F and 4G are cross-sectional views illustrating a part of the manufacturing process of the FeRAM according to the embodiment of the present invention. 5H and 5I are cross-sectional views illustrating a part of the manufacturing process of the FeRAM according to the embodiment of the present invention. 6J and 6K are cross-sectional views showing a part of the manufacturing process of the FeRAM according to the embodiment of the present invention.

Explanation of symbols

108, 109, 110 Barrier metal 111 Lower electrode 113 SBT film 114 Upper electrode 122 Plate line

Claims (9)

Forming a first electrode constituting the charge capacitance element;
Forming a dielectric layer constituting the charge capacitance element on the first electrode;
Forming a second electrode constituting the charge capacitance element on the dielectric layer;
Coating the charge capacitance element with an insulating film;
Forming a contact hole reaching one of the first and second electrodes in the insulating film by plasma etching;
Forming a dummy contact hole reaching the other of the first and second electrodes simultaneously with the formation of the contact hole;
And a step of forming a wiring electrically connected to the one electrode through the contact hole. In the step of forming the wiring,
After filling both the contact hole and the dummy contact hole with a wiring material and electrically shorting the first and second electrodes into which the dielectric layer is inserted,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring is formed by plasma etching and the short circuit is cut. Forming an integrated element region layer composed of a transistor and an element isolation region on a semiconductor substrate, and sequentially forming one or more insulating film layers, a wiring layer, and a contact hole connecting the transistor and the interconnection; ;
In order to raise a part of the lower electrode of the charge capacitance element to be formed later on any one of the insulating film layers so that the raised part of the lower electrode is equal to or higher than the upper surface of the upper electrode. Forming a step of
Depositing the lower electrode material to form an electrode shape, then sequentially laminating a dielectric material and an upper electrode material, and then processing the upper electrode and the dielectric material to form a charge capacitance element structure;
After depositing an interlayer insulating film on the charge capacitor element formation surface and performing surface planarization, contact holes that penetrate the upper electrode surface and dummy contact holes that penetrate the raised portion of the lower electrode have the same inner diameter. Simultaneously opening by plasma etching;
A method of manufacturing a semiconductor device, comprising: embedding a wiring material in the contact hole and the dummy contact hole, and depositing the wiring material on an insulating film, and then forming a wiring pattern by plasma etching. Method.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the step is formed on a final insulating film in the insulating film layer. As the electrode material, a single layer film of Pt, IrO ₂ , SrRuO ₃ or a laminated film thereof is used.
5. The method of manufacturing a semiconductor device according to claim 1, wherein a ferroelectric material of any one of PZT, SBT, and BLT film is used as the dielectric material. Using conductive polycrystalline silicon and refractory metal as the electrode material,
5. The method of manufacturing a semiconductor device according to claim 1, wherein a transition metal oxide is used as the dielectric material. An integrated element region layer comprising a transistor and an element isolation region on a semiconductor substrate;
An insulating film layer formed on the integrated element region layer;
A charge capacitance element formed on the insulating film layer;
An interlayer insulating film deposited on the charge capacitance element forming surface,
The charge capacitance element includes a lower electrode, an upper electrode, and a dielectric layer sandwiched between the two electrodes.
A portion of the lower electrode is raised outside the charge capacitance element, and is shaped to have a height equal to or higher than the upper surface of the upper electrode,
A contact hole penetrating the surface of the upper electrode and a dummy contact hole penetrating the raised portion of the lower electrode are simultaneously formed by plasma etching with the same inner diameter,
A semiconductor device having a wiring pattern formed by plasma etching after a wiring material is embedded in the contact hole and the dummy contact hole, and the wiring material is deposited on the interlayer insulating film. As the electrode material, a single layer film of Pt, IrO ₂ , SrRuO ₃ or a laminated film thereof is used.
8. The semiconductor device according to claim 7, wherein a ferroelectric material of any one of PZT, SBT, and BLT film is used as the dielectric material. Using conductive polycrystalline silicon and refractory metal as the electrode material,
The semiconductor device according to claim 7, wherein a transition metal oxide is used as the dielectric material.

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