KR100329784B1 - Method for preventing degradation of ferroelectric layer in metal wire formation process by using polymer - Google Patents
Method for preventing degradation of ferroelectric layer in metal wire formation process by using polymer Download PDFInfo
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 63
- 239000002184 metal Substances 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims abstract description 57
- 230000008569 process Effects 0.000 title claims abstract description 35
- 229920000642 polymer Polymers 0.000 title claims abstract description 21
- 230000015556 catabolic process Effects 0.000 title abstract description 5
- 238000006731 degradation reaction Methods 0.000 title abstract description 5
- 230000015572 biosynthetic process Effects 0.000 title description 5
- 238000005530 etching Methods 0.000 claims abstract description 27
- 239000003990 capacitor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 230000001052 transient effect Effects 0.000 claims description 3
- 230000006866 deterioration Effects 0.000 abstract description 9
- 230000010287 polarization Effects 0.000 abstract description 8
- 238000001465 metallisation Methods 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- 230000001965 increasing effect Effects 0.000 abstract description 4
- 229910052721 tungsten Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010937 tungsten Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 41
- 239000011229 interlayer Substances 0.000 description 7
- 239000010410 layer Substances 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 description 1
- 229910001260 Pt alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000011232 storage material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
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Abstract
본 발명은 강유전체 메모리 소자의 금속 배선 형성 공정에서 플라즈마에 의한 강유전체 캐패시터의 특성 열화를 방지할 수 있는, 강유전체 메모리 소자의 금속배선 형성 방법에 관한 것으로, 폴리머를 이용하여 금속배선 형성 공정 중의 강유전체 캐패시터 특성 열화를 방지하는 방법을 제공하는데 그 특징이 있다. 즉, 알루미늄 또는 텅스텐 등과 같은 금속막 식각시 폴리머를 다량 발생시켜 플라즈마에 의한 강유전체의 잔류분극, 임프린트 등의 특성 열화를 방지하는 방법이다. 금속배선 형성 공정을 위한 식각 과정에서 다량의 폴리머를 발생시키기 위하여 다음과 같은 방법을 이용한다. 첫째, 식각 조건중 기판에 인가되는 전력 즉 바이어스 전력을 증가시킨다. 둘째, 과도식각 타겟을 증가시킨다. 셋째, 공정 진행 온도를 낮춘다. 이에 따라, 금속 배선 공정 중에 발생하는 강유전 캐패시터의 전기적 특성이 열화를 방지하여 FeRAM의 경제성을 증가시키고, 전위 이동을 최소로 감소시킴으로써 FeRAM 소자의 수명을 10년 이상으로 증가시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a ferroelectric memory device that can prevent deterioration of characteristics of a ferroelectric capacitor by plasma in a metal wiring forming process of a ferroelectric memory device. It is characterized by providing a method for preventing deterioration. That is, a large amount of polymer is generated during etching of a metal film such as aluminum or tungsten to prevent deterioration of characteristics such as residual polarization and imprint of the ferroelectric by plasma. The following method is used to generate a large amount of polymer in the etching process for the metallization process. First, the power applied to the substrate during the etching condition, that is, the bias power is increased. Second, increase the overetch target. Third, lower the process run temperature. Accordingly, the electrical characteristics of the ferroelectric capacitors generated during the metal wiring process prevent degradation, thereby increasing the economic efficiency of FeRAM, and by reducing the potential shift to a minimum, it is possible to increase the life of the FeRAM device to 10 years or more.
Description
본 발명은 강유전체 메모리 소자 제조 방법에 관한 것으로, 특히 금속배선 형성을 위한 플라즈마 식각 공정에서 강유전체 특성이 저하되는 것을 방지할 수 있는 강유전체 메모리 소자 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a ferroelectric memory device, and more particularly, to a method of manufacturing a ferroelectric memory device capable of preventing degradation of the ferroelectric properties in a plasma etching process for forming metal wiring.
반도체 메모리 소자에서 강유전체(ferroelectric) 재료를 캐패시터에 사용함으로써 기존 DRAM(Dynamic Random Access Memory) 소자에서 필요한 리프레쉬(refresh)의 한계를 극복하고 대용량의 메모리를 이용할 수 있는 소자의 개발이 진행되어왔다. FeRAM(ferroelectric random access memory) 소자는 비휘발성 메모리 소자의 일종으로 전원이 끊어진 상태에서도 저장 정보를 기억하는 장점이 있을 뿐만 아니라 동작 속도도 기존의 DRAM에 필적하여 차세대 기억소자로 각광받고 있다.By using a ferroelectric material in a capacitor in a semiconductor memory device, development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a conventional dynamic random access memory (DRAM) device has been in progress. A ferroelectric random access memory (FeRAM) device is a nonvolatile memory device that not only stores stored information even when a power supply is cut off, but also has an operation speed comparable to that of a conventional DRAM.
강유전체 기억소자의 축전물질로는 SrBi2Ta2O9(이하 SBT)와 Pb(Zr,Ti)O3(이하 PZT) 박막이 주로 사용된다. 강유전체는 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remnant polarization) 상태를 갖고 있어 이를 박막화하여 비휘발성(nonvolatile) 메모리 소자로의 응용이 실현되고 있다. 강유전체 박막을 이용하는 비휘발성 메모리 소자는, 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호 1과 0을 저장하는 원리를 이용한다.SrBi 2 Ta 2 O 9 (hereinafter referred to as SBT) and Pb (Zr, Ti) O 3 (hereinafter referred to as PZT) thin films are mainly used as storage materials for ferroelectric memory devices. Ferroelectrics have dielectric constants ranging from hundreds to thousands at room temperature, and have two stable remnant polarization states, making them thinner and enabling their application to nonvolatile memory devices. Nonvolatile memory devices using a ferroelectric thin film use the principle of inputting a signal by adjusting the direction of polarization in the direction of an applied electric field and storing digital signals 1 and 0 by the direction of residual polarization remaining when the electric field is removed. .
FeRAM 소자에서 캐패시터의 강유전체 재료로서 PZT, SBT, SrxBiy(TaiNbj)2O9(이하 SBTN) 등의 페롭스카이트(perovskite) 구조를 갖는 강유전체를 사용하는 경우 통상적으로 Pt, Ir, Ru, Pt 합금 등의 금속으로 상부전극을 형성한다.As the ferroelectric material of the capacitor in the FeRAM element PZT, SBT, Sr x Bi y (Ta i Nb j) 2 O 9 in the conventional case of using a ferroelectric having a perovskite (perovskite) structure, such as (the SBTN) Pt, Ir The upper electrode is formed of a metal such as Ru, Pt alloy, or the like.
FeRAM 소자 제조 공정 중 증착 또는 식각 등을 위한 플라즈마 공정 이후에 강유전체 캐패시터의 잔류분극(remnant polarization, Pr)이 감소하고 전위가 이동(ΔVc, │+Vc│-│-Vc│)되는 등 전기적 특성이 열화되는 문제점 있다.Residual polarization (Pr) of the ferroelectric capacitor is reduced and the potential shifts (ΔV c , │ + V c │-│-V c │) after the plasma process for deposition or etching during the FeRAM device manufacturing process. There is a problem that the electrical characteristics are deteriorated.
도1은 금속배선 공정 이후의 전형적인 전위 이동을 보이는 그래프이다. 이와 같이 전위 이동이 일어나면 FeRAM 소자의 읽기(Reading)와 쓰기(Writing) 횟수를 감소시켜 소자의 수명이 단축된다.1 is a graph showing a typical potential shift after a metallization process. As such, when the potential shift occurs, the lifetime of the device is reduced by reducing the number of reading and writing of the FeRAM device.
플라즈마 공정에 의한 강유전체 캐패시터의 열화는 플라즈마에 의해 형성된 전자들이 금속 배선을 통해 SrBi2Ta209(SBT) 등과 같은 강유전체 박막에 포획(trapping)되어 캐패시터 내부 전기장을 형성시키기 때문에 발생하는 것으로 보고되어 있다.The deterioration of the ferroelectric capacitor by the plasma process is reported to occur because electrons formed by the plasma are trapped in the ferroelectric thin film such as SrBi 2 Ta 2 0 9 (SBT) through metal wiring to form an electric field inside the capacitor. have.
플라즈마 공정으로 인한 캐패시터의 전기적 특성 열화는 600 ℃ 이상의 고온의 산소 분위기에서 열처리(Annealing) 함으로써 복구될 수 있다. 그러나, 금속 배선을 이루는 Al 등은 녹는점이 낮기 때문에 열처리로써 강유전체 캐패시터의 특성을 복구할 수 없다. 따라서, 플라즈마 공정 중에 캐패시터의 특성 열화를 최소화시켜야 한다.The deterioration of the electrical characteristics of the capacitor due to the plasma process can be recovered by annealing in an oxygen atmosphere of 600 ° C. or higher. However, since Al and the metal constituting the wiring have a low melting point, the characteristics of the ferroelectric capacitor cannot be recovered by heat treatment. Therefore, it is necessary to minimize the deterioration of the characteristics of the capacitor during the plasma process.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 강유전체 메모리 소자의 금속 배선 형성 공정에서 플라즈마에 의한 강유전체 캐패시터의 특성 열화를 방지할 수 있는, 강유전체 메모리 소자의 금속배선 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method for forming a metal wiring of the ferroelectric memory device, which can prevent the degradation of the characteristics of the ferroelectric capacitor by the plasma in the metal wiring forming process of the ferroelectric memory device. have.
도1은 종래 기술에 따른 금속배선 형성 공정 후 전형적인 전위 이동을 보이는 그래프,1 is a graph showing a typical potential shift after a metallization process according to the prior art;
도2는 본 발명의 일실시예에 따른 FeRAM 소자 제조 공정 단면도,2 is a cross-sectional view of the FeRAM device manufacturing process according to an embodiment of the present invention;
도3a는 종래 기술에 따라 형성된 금속배선의 SEM 사진,Figure 3a is a SEM photograph of a metal wiring formed according to the prior art,
도3b는 본 발명의 일실시예에 따라 형성된 금속배선의 SEM 사진,3b is a SEM photograph of a metallization formed in accordance with one embodiment of the present invention;
도4는 폴리머 양의 변화에 따른 이동 전위의 정도를 보이는 그래프.4 is a graph showing the degree of transfer potential according to the change of polymer amount.
* 도면의 주요 부분에 대한 도면부호의 설명* Explanation of the reference numerals for the main parts of the drawings
16: 하부전극 17: 강유전체막16: lower electrode 17: ferroelectric film
18: 상부전극 21: 금속배선18: upper electrode 21: metal wiring
상기와 같은 목적을 달성하기 위한 본 발명은, 강유전체 캐패시터 형성이 완료된 전체 구조 상에 금속배선 형성을 위한 금속막을 형성하는 제1 단계; 및 플라즈마를 이용한 건식식각으로 상기 금속막을 선택적으로 식각해서 금속배선을 형성하면서, 상기 강유전체 캐패시터 내부로 전자가 축적되는 것을 방지하기 위하여 폴리머를 발생시키는 제2 단계를 포함하는 강유전체 메모리 소자의 금속배선 형성 방법을 제공한다.The present invention for achieving the above object, the first step of forming a metal film for forming metal wiring on the entire structure of the ferroelectric capacitor formation is completed; And forming a metal wiring by selectively etching the metal film by dry etching using plasma, and generating a polymer to prevent electrons from accumulating inside the ferroelectric capacitor. Provide a method.
또한, 상기 목적을 달성하기 위한 본 발명은, 강유전체 캐패시터 형성이 완료된 전체 구조 상에 금속배선 형성을 위한 금속막을 형성하는 제1 단계; 상기 금속막 상에 하드마스크층을 형성하는 제2 단계; 상기 하드마스크층 상에 금속배선을 정의하는 포토레지스트 패턴을 형성하는 제3 단계; 상기 포토레지스트 패턴을 식각마스크로 이용하여 상기 하드마스크층을 식각하여 하드마스크 패턴을 형성하는 제4 단계; 상기 하드마스크 및 상기 포토레지스트 패턴을 식각마스크로 이용하여, 플라즈마를 이용한 건식식각으로 상기 금속막을 식각해서 금속배선을 형성하면서, 상기 강유전체 캐패시터 내부로 전자가 축적되는 것을 방지하기 위하여 폴리머를 발생시키는 제5 단계; 및 상기 포토레지스트를 제거하는 제6 단계를 포함하는 강유전체 메모리 소자의 금속배선 형성 방법을 제공한다.In addition, the present invention for achieving the above object, the first step of forming a metal film for forming a metal wiring on the entire structure of the ferroelectric capacitor formation is completed; Forming a hard mask layer on the metal film; Forming a photoresist pattern defining metal wiring on the hard mask layer; A fourth step of forming a hard mask pattern by etching the hard mask layer by using the photoresist pattern as an etching mask; The hard mask and the photoresist pattern as an etch mask, the metal film is etched by dry etching using plasma to form a metal wiring, while generating a polymer to prevent electrons from accumulating inside the ferroelectric capacitor. 5 steps; And a sixth step of removing the photoresist.
본 발명은 폴리머를 이용하여 금속배선 형성 공정 중의 강유전체 캐패시터 특성 열화를 방지하는 방법을 제공하는데 그 특징이 있다. 즉, 알루미늄 또는 텅스텐 등과 같은 금속막 식각시 폴리머를 다량 발생시켜 플라즈마에 의한 강유전체의 잔류분극, 임프린트(Imprint) 등의 특성 열화를 방지하는 방법이다.The present invention is characterized by providing a method of preventing degradation of ferroelectric capacitor characteristics during a metallization forming process using a polymer. In other words, a large amount of polymer is generated when etching a metal film such as aluminum or tungsten to prevent deterioration of characteristics such as residual polarization and imprint of the ferroelectric due to plasma.
즉, 금속배선 형성을 위한 플라즈마 식각 공정에서 SBT 등과 같은 강유전체 박막에 축적되는 전자의 양을 감소시키기 위하여 식각 폴리머를 이용한다. 또한, 산소 하드마스크를 이용하여 금속배선의 식각시 금속막의 노출을 최소화시켜 플라즈마 공정에서 발생하는 전자가 강유전체 박막에 축적되는 것을 효과적으로 억제한다.That is, an etching polymer is used to reduce the amount of electrons accumulated in the ferroelectric thin film such as SBT in the plasma etching process for forming metal wiring. In addition, by minimizing the exposure of the metal film during the etching of the metal wiring by using an oxygen hard mask to effectively suppress the accumulation of electrons generated in the plasma process in the ferroelectric thin film.
금속 배선 형성을 위해서는 플라즈마를 이용하여 금속막 식각을 식각하고, O2와 N2플라즈마를 이용하여 포토레지스트를 제거하여야 하는데, 이와 같은 플라즈마 공정 이후, 전위 이동과 잔류 분극의 감소 등의 강유전 캐패시터의 전기적 특성이 열화된다. 이중 포토레지스트 제거 공정이 식각공정보다 강유전 캐패시터의 특성을 보다 심하게 열화시킨다. 이는 식각 공정에서는 포토레지스트와 식각 폴리머가 SBT 박막의 표면에 전자가 축적되는 것을 막아주나 포토레지스트 제거 공정에서는 전자의 축적을 방지할 수 없기 때문이다.In order to form the metal lines, the metal film is etched using plasma and the photoresist is removed by using O 2 and N 2 plasma. After the plasma process, ferroelectric capacitors such as dislocation shift and reduction of residual polarization are removed. Electrical characteristics deteriorate. The double photoresist removal process degrades the ferroelectric capacitor more severely than the etching process. This is because the photoresist and the etching polymer prevent electrons from accumulating on the surface of the SBT thin film in the etching process, but electron accumulation cannot be prevented in the photoresist removing process.
본 발명은 금속배선 형성 공정을 위한 식각 과정에서 다량의 폴리머를 발생시키기 위하여 다음과 같은 방법을 이용한다. 첫째, 식각 조건중 기판에 인가되는 전력 즉 바이어스(Bias Power)를 증가시킨다. 둘째, 과도식각 타겟(over etch target)을 증가시킨다. 셋째, 공정 진행 온도를 낮춘다.The present invention uses the following method to generate a large amount of polymer in the etching process for the metallization process. First, the power applied to the substrate during the etching condition, that is, bias power is increased. Second, increase the over etch target. Third, lower the process run temperature.
한편, 하드마스크(hard mask)를 사용하여 식각 폴리머를 증가시킴과 동시에 포토레지스트 제거를 위한 플라즈마 공정시 금속 배선의 표면을 덮음으로써 하부 강유전체막에 전자가 축적되는 것을 방지한다. 하드마스크는 BPSG, PSG(phospho silicate glass), 실리콘이 풍부한 산화막, 실리콘산화질화막(SiON) 또는 질화막(SiNx)으로 형성한다.On the other hand, by using a hard mask to increase the etching polymer and at the same time to cover the surface of the metal wiring during the plasma process for removing the photoresist to prevent the accumulation of electrons in the lower ferroelectric film. The hard mask is formed of BPSG, PSG (phospho silicate glass), silicon rich oxide film, silicon oxynitride film (SiON) or nitride film (SiN x ).
이하, 첨부된 도면 도2를 참조하여 본 발명의 일실시예에 따른 FeRAM 소자 제조 방법을 상세히 설명한다.Hereinafter, a method of manufacturing a FeRAM device according to an embodiment of the present invention will be described in detail with reference to FIG. 2.
먼저, 게이트 절연막(도시하지 않음), 게이트 전극(12), 소오스 ·드레인(14)으로 이루어지는 트랜지스터 형성이 완료된 반도체 기판(10) 상부에 BPSG(borophospho silicate glass) 등으로 제1 층간절연막(15)을 형성한다.First, the first interlayer insulating film 15 is made of borophospho silicate glass (BPSG) or the like on the semiconductor substrate 10 on which the transistor formation including the gate insulating film (not shown), the gate electrode 12, and the source and drain 14 is completed. To form.
이어서, 제1 층간절연막(15) 상에 Ti막 등의 접착막(도시하지 않음)을 형성하고, Pt 하부전극막(16), 강유전체막(17) 및 상부전극(18)으로 이루어지는 캐패시터를 형성한다.Subsequently, an adhesive film (not shown) such as a Ti film is formed on the first interlayer insulating film 15, and a capacitor including the Pt lower electrode film 16, the ferroelectric film 17, and the upper electrode 18 is formed. do.
캐패시터 형성은 다음과 같은 과정으로 이루어진다. 하부전극막 증착, 강유전체막 증착 및 상부전극막 증착 공정을 차례로 실시하고, 제1 식각마스크를 이용하여 상부전극막을 식각한 다음, 제2 식각마스크를 이용하여 강유전체막 및 하부전극막을 식각한다. 이후, 강유전체막을 선택적으로 식각하여 배선과 연결될 하부전극 부분을 노출시킨다.Capacitor formation consists of the following process. Lower electrode film deposition, ferroelectric film deposition and upper electrode film deposition processes are sequentially performed, the upper electrode film is etched using the first etching mask, and the ferroelectric film and the lower electrode film are etched using the second etching mask. Thereafter, the ferroelectric film is selectively etched to expose the lower electrode portion to be connected to the wiring.
다음으로, 전체 구조 상에 제2 층간절연막(19)을 형성하고, 제2 층간절연막(19)을 선택적으로 식각하여 금속배선과 연결될 상부전극막(18) 및 하부전극막(16)을 노출시키고, 제2 층간절연막(19) 및 제1 층간절연막(15)을 선택적으로 식각하여 반도체 기판(10)을 노출시키는 콘택홀을 형성한 다음, 상부전극 상에 TiN 등으로 확산방지막(20)을 형성한다.Next, a second interlayer insulating film 19 is formed on the entire structure, and the second interlayer insulating film 19 is selectively etched to expose the upper electrode film 18 and the lower electrode film 16 to be connected to the metal wiring. And selectively etching the second interlayer insulating film 19 and the first interlayer insulating film 15 to form a contact hole exposing the semiconductor substrate 10, and then forming a diffusion barrier film 20 using TiN or the like on the upper electrode. do.
이어서, 금속배선 형성을 위해 Al 또는 W 등으로 이루어지는 적층구조의 금속막(21)을 형성하고, 금속막(21) 상에 산화막 또는 질화막 등으로 하드마스크층(22)을 형성한 다음, 포토레지스트 패턴(도시하지 않음)을 식각마스크로 이용하여 하드마스크층(22) 및 금속막(21)을 식각한다. 이때, 다량의 폴리머 형성을 위해 0.1 ㎾ 내지 1 ㎾의 바이어스 전력을 인가하고, 기판을 고정시키는 척(Chuck)의 온도는 -50 ℃ 내지 50 ℃가 되도록 하며, 주식각 공정 시간의 50 % 내지 200 % 시간 동안 과도식각을 실시한다.구체적으로, ECR(Electron Cyclotron Resonance), ICP(Inductive Coupled Plasma), 헬리컨(Helicon) 또는 반응성이온식각(Reactive Ion Etching) 장비 등을 이용하여 플라즈마 소스를 제공하며, Cl2/BCl3가스를 그 반응가스로 이용하는 바, 그 비율이 100/0 내지 50/50이 되도록 하며, 소스파워는 1000W 내지 3000W, 압력은 0.5Torr 내지 50Torr를 유지한다.따라서, 상기한 조건에 의해 금속막(21) 식각에 따라 Cl2/BCl3와 Al 또는 W 등의 금속 성분이 함유된 다량의 폴리머가 금속배선(21) 주변에 형성된다.Subsequently, in order to form metal wirings, a metal film 21 having a laminated structure made of Al, W, or the like is formed, and a hard mask layer 22 is formed on the metal film 21 by using an oxide film or a nitride film, and then a photoresist. The hard mask layer 22 and the metal film 21 are etched using a pattern (not shown) as an etching mask. At this time, in order to form a large amount of polymer, a bias power of 0.1 kW to 1 kW is applied, and the temperature of the chuck fixing the substrate is -50 ° C to 50 ° C, and 50% to 200% of each stock process time. Transient etching is performed for% time. Specifically, the plasma source is provided using ECR (Electron Cyclotron Resonance), Inductive Coupled Plasma (ICP), Helicon, or Reactive Ion Etching (IC) equipment. , Using the Cl 2 / BCl 3 gas as the reaction gas, the ratio is 100/0 to 50/50, the source power is 1000W to 3000W, the pressure is 0.5 Torr to 50 Torr. By the etching of the metal film 21, a large amount of polymer containing metal components such as Cl 2 / BCl 3 and Al or W is formed around the metal wiring 21 under the conditions.
이러한 공정에 따라 금속배선(21)을 형성한 다음 제2 층간절연막(22)을 형성한다. 도2에서 미설명 도면부호 '11'은 소자분리막, '13'은 절연막 스페이서를 나타낸다.According to this process, the metal wiring 21 is formed, and then the second interlayer insulating film 22 is formed. In FIG. 2, reference numeral '11' denotes an isolation layer and '13' denotes an insulating film spacer.
도3a 및 도3b는 각각 종래 기술과 본 발명에 따라 형성된 금속배선을 보이는 SEM 사진으로서, 본 발명에 따른 금속배선 형성의 경우(도3b)의 금속배선 주변에 폴리머가 다량 형성된 것을 보이고 있다.3A and 3B are SEM photographs showing metal wirings formed according to the prior art and the present invention, respectively, in which a large amount of polymer is formed around the metal wirings in the case of forming the metal wirings according to the present invention (Fig. 3B).
도4는 폴리머 양의 변화에 따른 이동전위의 정도를 보이는 그래프로서, 'A'는 상대적으로 다량의 폴리머를 형성하고 습식세정 공정을 실시하기 전의 전압이동 결과를 나타내고, 'B'는 상대적으로 소량의 폴리머를 형성하고 습식세정 공정을 실시하기 전의 전압이동 결과를 나타내며, 'C'는 폴리머를 형성없이 습식세정 공정을 실시한 경우 전압이동 결과를 나타낸다.4 is a graph showing the degree of shift potential according to the change of polymer amount, 'A' shows the result of voltage shift before forming a relatively large amount of polymer and performing the wet cleaning process, and 'B' is a relatively small amount The voltage shift results before forming the polymer and performing the wet cleaning process, and 'C' indicates the voltage shift result when the wet cleaning process is performed without forming the polymer.
전술한 FeRAM 소자의 금속배선 형성 방법에 따라 잔류분극의 열화 없이 전위 이동을 200%에서 300%정도 감소시킬 수 있다. 또한, 하드마스크 형성으로 금속 배선의 두께를 증가시켜 메모리 소자의 동작 속도를 증가시킬 수 있다.According to the above-described method of forming the metal wiring of the FeRAM device, the potential shift can be reduced by 200% to 300% without deterioration of residual polarization. In addition, the hard mask may be formed to increase the thickness of the metal wire, thereby increasing the operating speed of the memory device.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은, 금속 배선 공정 중에 발생하는 강유전 캐패시터의 전기적 특성이 열화를 방지하여 FeRAM의 경제성을 증가시키고, 전위 이동을 최소로 감소시킴으로써 FeRAM 소자의 수명을 10년 이상으로 증가시킬 수 있다.According to the present invention as described above, the electrical characteristics of the ferroelectric capacitor generated during the metal wiring process can prevent the deterioration, increase the economic efficiency of FeRAM, and reduce the potential shift to a minimum can increase the life of the FeRAM device to 10 years or more. have.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06125057A (en) * | 1992-10-12 | 1994-05-06 | Olympus Optical Co Ltd | Semiconductor memory containing ferroelectric film |
| JPH07297364A (en) * | 1994-04-25 | 1995-11-10 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
| JPH09172150A (en) * | 1995-12-19 | 1997-06-30 | Matsushita Electron Corp | Fabrication of semiconductor device |
| KR19990085671A (en) * | 1998-05-20 | 1999-12-15 | 윤종용 | Etching method of metal wiring to prevent damage of ferroelectric capacitor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06125057A (en) * | 1992-10-12 | 1994-05-06 | Olympus Optical Co Ltd | Semiconductor memory containing ferroelectric film |
| JPH07297364A (en) * | 1994-04-25 | 1995-11-10 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
| JPH09172150A (en) * | 1995-12-19 | 1997-06-30 | Matsushita Electron Corp | Fabrication of semiconductor device |
| KR19990085671A (en) * | 1998-05-20 | 1999-12-15 | 윤종용 | Etching method of metal wiring to prevent damage of ferroelectric capacitor |
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