KR20020002570A - Method for forming ferroelectric memory device capable of preventing generation of ferroelectric capacitor degradation caused by reactive ion etching - Google Patents
Method for forming ferroelectric memory device capable of preventing generation of ferroelectric capacitor degradation caused by reactive ion etching Download PDFInfo
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- 239000003990 capacitor Substances 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000001020 plasma etching Methods 0.000 title claims abstract description 19
- 230000015556 catabolic process Effects 0.000 title 1
- 238000006731 degradation reaction Methods 0.000 title 1
- 230000000903 blocking effect Effects 0.000 claims abstract description 32
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims description 23
- 239000001257 hydrogen Substances 0.000 claims description 19
- 229910052739 hydrogen Inorganic materials 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 14
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000002265 prevention Effects 0.000 claims description 5
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 239000010408 film Substances 0.000 description 50
- 150000002431 hydrogen Chemical class 0.000 description 13
- 238000005530 etching Methods 0.000 description 9
- 230000006866 deterioration Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011232 storage material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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Abstract
Description
본 발명은 비휘발성 메모리 소자 제조 분야에 관한 것으로, 특히 반응성 이온식각에 의한 강유전체 캐패시터의 특성 저하를 방지할 수 있는 강유전체 메모리 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of manufacturing nonvolatile memory devices, and more particularly, to a method of manufacturing a ferroelectric memory device capable of preventing the deterioration of characteristics of a ferroelectric capacitor by reactive ion etching.
반도체 메모리 소자에서 강유전체(ferroelectric) 재료를 캐패시터에 사용함으로써 기존 DRAM(Dynamic Random Access Memory) 소자에서 필요한 리프레쉬(refresh)의 한계를 극복하고 대용량의 메모리를 이용할 수 있는 소자의 개발이 진행되어왔다. FeRAM(ferroelectric random access memory) 소자는 비휘발성 메모리 소자의 일종으로 전원이 끊어진 상태에서도 저장 정보를 기억하는 장점이 있을 뿐만 아니라 동작 속도도 기존의 DRAM에 필적하여 차세대 기억소자로 각광받고 있다.By using a ferroelectric material in a capacitor in a semiconductor memory device, development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a conventional dynamic random access memory (DRAM) device has been in progress. A ferroelectric random access memory (FeRAM) device is a nonvolatile memory device that not only stores stored information even when a power supply is cut off, but also has an operation speed comparable to that of a conventional DRAM.
FeRAM의 축전물질로는 SriBijTa2O9(이하 SBT)와 Pb(Zr,Ti)O3(이하 PZT) 박막이 주로 사용된다. 강유전체는 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remnant polarization) 상태를 갖고 있어 이를 박막화하여 비휘발성(nonvolatile) 메모리 소자로의 응용이 실현되고 있다. 강유전체 박막을 이용하는 비휘발성 메모리 소자는, 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호 1과 0을 저장하는 원리를 이용한다.As the storage material of FeRAM, Sr i Bi j Ta 2 O 9 (hereinafter SBT) and Pb (Zr, Ti) O 3 (hereinafter PZT) thin films are mainly used. Ferroelectrics have dielectric constants ranging from hundreds to thousands at room temperature, and have two stable remnant polarization states, making them thinner and enabling their application to nonvolatile memory devices. Nonvolatile memory devices using a ferroelectric thin film use the principle of inputting a signal by adjusting the direction of polarization in the direction of an applied electric field and storing digital signals 1 and 0 by the direction of residual polarization remaining when the electric field is removed. .
첨부된 도면 도1 a 및 도 1b를 참조하여 종래 FeRAM 소자 제조 공정을 설명한다.A conventional FeRAM device manufacturing process will be described with reference to the accompanying drawings, FIGS. 1A and 1B.
도 1a는 트랜지스터, 비트라인 그리고 강유전체 캐패시터 형성이 완료된 상태를 보이는 공정 단면도이다. 즉, 소자분리막(21) 그리고 게이트 절연막(12), 게이트 전극(13) 및 소오스·드레인(14)으로 이루어지는 트랜지스터 형성이 완료된 반도체 기판(10)을 덮는 제1 층간절연막(15) 내에 제1 콘택홀(C1)을 형성하고, 상기 제1 콘택홀을 통하여 트랜지스터의 소오스·드레인(14)과 연결되는 비트라인(16)을 형성한 다음, 비트라인(16) 형성이 완료된 전체 구조 상에 제2 층간절연막(17)을 형성하고, 제2 층간절연막(17)과 제1 층간절연막(15)을 선택적으로 식각하여 트랜지스터의 또 다른 소오스·드레인(14)과 연결되는 제2 콘택홀(C2)을 형성하고, 제2 콘택홀(C2) 내에 폴리실리콘 플러그(18), 실리사이드층(19) 및 확산방지막(20)을 형성하고, 하부전극(21), 강유전체막(22) 및 상부전극(23)으로 이루어지는 강유전체 캐패시터를 형성하여 상기 제2 콘택홀(C2)을 통하여 트랜지스터와 연결시킨 상태를 보이고 있다.FIG. 1A is a cross-sectional view illustrating a state in which transistors, bit lines, and ferroelectric capacitors are formed. In other words, a first contact is formed in the first interlayer insulating film 15 covering the semiconductor substrate 10 on which the transistor isolation film 21 and the gate insulating film 12, the gate electrode 13, and the source and drain 14 are formed. A hole C1 is formed, and a bit line 16 connected to the source and drain 14 of the transistor is formed through the first contact hole, and then a second structure is formed on the entire structure in which the bit line 16 is formed. A second contact hole C2 connected to another source and drain 14 of the transistor is formed by selectively etching the second interlayer insulating film 17 and the first interlayer insulating film 15. The polysilicon plug 18, the silicide layer 19, and the diffusion barrier 20 are formed in the second contact hole C2, and the lower electrode 21, the ferroelectric layer 22, and the upper electrode 23 are formed. A ferroelectric capacitor formed of the at least one ferroelectric capacitor and connected to the transistor through the second contact hole C2. It is showing a state.
도 1b는 상기와 같은 강유전체 캐패시터 형성이 완료된 전체 구조 상에 수소 확산방지막(24) 및 제3 층간절연막(25)을 형성하고, 제3 층간절연막(25)과 수소 확산방지막(24)을 선택적으로 식각하여 강유전체 캐패시터의 상부전극(23)을 노출시키는 제3 콘택홀(C3)을 형성한 다음, 금속배선(26)을 형성한 것을 나타내고 있다.FIG. 1B shows a hydrogen diffusion barrier 24 and a third interlayer dielectric 25 on the entire structure of the ferroelectric capacitor formation as described above, and selectively forms a third interlayer dielectric 25 and a hydrogen diffusion barrier 24. The third contact hole C3 exposing the upper electrode 23 of the ferroelectric capacitor is formed by etching, and then the metal wiring 26 is formed.
전술한 바와 같이 이루어지는 종래 강유전체 메모리 소자 과정에서 식각은 통상적으로 RIE(reactive ion etching) 공정으로 진행된다. RIE 공정은 기판에 바이어스(bias) 전압이 인가되고 플라즈마로부터 발생하는 UV 광이 기판에 조사되는 환경에서 진행되는데, 이런 환경에서 상기 제3 콘택홀(C3)을 형성할 경우 강유전체캐패시터 특성의 열화를 유발한다.In the conventional ferroelectric memory device process as described above, etching is typically performed by a reactive ion etching (RIE) process. The RIE process is performed in an environment in which a bias voltage is applied to the substrate and UV light generated from the plasma is irradiated onto the substrate. In this environment, when the third contact hole C3 is formed, deterioration of ferroelectric capacitor characteristics is prevented. cause.
상기와 같은 문제점을 해결하기 위한 본 발명은 강유전체 캐패시터 형성 후 실시되는 RIE 식각공정에 의해 강유전체 캐패시터의 특성이 저하되는 것을 효과적으로 방지할 수 있는 강유전체 메모리 소자 제조 방법을 제공하는데 그 목적이 있다.The present invention for solving the above problems is to provide a method of manufacturing a ferroelectric memory device that can effectively prevent the deterioration of the characteristics of the ferroelectric capacitor by the RIE etching process after the formation of the ferroelectric capacitor.
도 1a 및 도 1b는 종래 기술에 따른 강유전체 메모리 소자 제조 공정 단면도,1A and 1B are cross-sectional views of a ferroelectric memory device manufacturing process according to the prior art;
도 2a 및 도 2b는 본 발명의 실시 예에 따른 강유전체 메모리 소자 제조 공정 단면도.2A and 2B are cross-sectional views of a ferroelectric memory device fabrication process according to an embodiment of the present invention.
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *
41: 하부전극 42: 강유전체막41: lower electrode 42: ferroelectric film
43: 상부전극 44: 수소확산방지막43: upper electrode 44: hydrogen diffusion prevention film
45: UV 차단막45: UV barrier
상기와 같은 목적을 달성하기 위한 본 발명은 강유전체 캐패시터 형성이 완료된 상태에서 반응성 이온식각 공정을 진행하는 강유전체 메모리 소자 제조 방법에 있어서, 상기 강유전체 캐패시터를 덮는 UV광 차단막을 형성하는 단계; 및 반응성 이온식각 공정을 진행하는 단계를 포함하는 강유전체 메모리 소자 제조 방법을 제공한다.According to an aspect of the present invention, there is provided a method of manufacturing a ferroelectric memory device in which a reactive ion etching process is performed in a state where a ferroelectric capacitor is formed, forming a UV light blocking film covering the ferroelectric capacitor; And it provides a ferroelectric memory device manufacturing method comprising the step of performing a reactive ion etching process.
또한 상기와 같은 목적을 달성하기 위한 본 발명은, 반도체 기판 상부에 하부전극, 강유전체막 및 상부전극으로 이루어지는 강유전체 캐패시터를 형성하는 제1 단계; 상기 제1 단계가 완료된 전체 구조 상에 UV광 차단막을 형성하는 제2 단계; 상기 UV광 차단막 상에 층간절연막을 형성하는 제3 단계; 및 반응성 이온식각 공정으로 상기 층간절연막 및 상기 UV광 차단막을 선택적으로 제거하여 상기 강유전체 캐패시터의 상기 상부전극을 노출시키는 콘택홀을 형성하는 제4 단계를 포함하는 강유전체 캐패시터 형성 방법을 제공한다.In addition, the present invention for achieving the above object, the first step of forming a ferroelectric capacitor consisting of a lower electrode, a ferroelectric film and an upper electrode on a semiconductor substrate; A second step of forming a UV light blocking film on the entire structure in which the first step is completed; Forming an interlayer insulating film on the UV light blocking film; And selectively removing the interlayer insulating layer and the UV light blocking layer by a reactive ion etching process to form a contact hole exposing the upper electrode of the ferroelectric capacitor.
또한 상기와 같은 목적을 달성하기 위한 본 발명은, 반도체 기판 상부에 하부전극, 강유전체막 및 상부전극으로 이루어지는 강유전체 캐패시터를 형성하는 제1 단계; 상기 제1 단계가 완료된 전체 구조 상에 수소확산방지막을 형성하는 제2 단계; 상기 수소확산방지막 상에 UV광 차단막을 형성하는 제3 단계; 상기 UV광 차단막 상에 층간절연막을 형성하는 제4 단계; 및 반응성 이온식각 공정으로 상기 층간절연막, 상기 UV광 차단막 및 상기 수소확산방지막을 선택적으로 제거하여 상기 강유전체 캐패시터의 상기 상부전극을 노출시키는 콘택홀을 형성하는 제5 단계를 포함하는 강유전체 캐패시터 형성 방법을 제공한다.In addition, the present invention for achieving the above object, the first step of forming a ferroelectric capacitor consisting of a lower electrode, a ferroelectric film and an upper electrode on a semiconductor substrate; A second step of forming a hydrogen diffusion barrier on the entire structure in which the first step is completed; Forming a UV light blocking film on the hydrogen diffusion preventing film; Forming an interlayer insulating film on the UV light blocking film; And forming a contact hole exposing the upper electrode of the ferroelectric capacitor by selectively removing the interlayer insulating film, the UV light blocking film, and the hydrogen diffusion preventing film by a reactive ion etching process. to provide.
RIE 공정시 강유전체 캐패시터의 특성 열화를 방지하기 위해서 강유전체 캐패시터에 인가되는 바이어스 전압 또는 강유전체 캐패시터에 조사되는 UV 광을 차단하여야 한다. 바이어스 전압이 인가되는 것을 차단하기 위해서는 강유전체 캐패시터를 전도막으로 덮어야 하는데, 이는 강유전체 캐패시터간의 단락을 유발하므로 불가능하다. 본 발명은 강유전체 캐패시터에 조사되는 UV 광을 차단하기 위해 강유전체막 상부에 UV 차단막(blocking layer)을 형성한 상태에서 식각공정을 실시하는데 그 특징이 있다.In order to prevent deterioration of the characteristics of the ferroelectric capacitor during the RIE process, the bias voltage applied to the ferroelectric capacitor or the UV light emitted to the ferroelectric capacitor should be blocked. In order to prevent the bias voltage from being applied, the ferroelectric capacitor must be covered with a conductive film, which is impossible because it causes a short circuit between the ferroelectric capacitors. The present invention is characterized in that an etching process is performed in a state in which a UV blocking layer is formed on the ferroelectric layer to block UV light irradiated to the ferroelectric capacitor.
UV 차단막은 UV 광흡수(absorption) 특성이 우수해야할 뿐만 아니라 캐패시터의 누설전류 증가를 방지하기 위해서 절연 특성이 우수하여야 한다. 이러한 두 가지 요건을 동시에 만족시키는 재료로는 SiN 또는 SiON 등이 있는데, UV 광흡수특성은 막 내부의 Si-H 결합 농도와 N 농도가 증가할수록 향상된다. 한편, SiN 또는 SiON 증착 공정은 강유전체 내부로 수소원자 및 이온 확산을 유발하여 강유전체 특성 저하를 야기시킨다. 따라서 SiN 또는 SiON 등으로 UV 차단막을 형성할 경우에는 Al2O3등과 같은 수소확산방지막 형성 공정이 선행되어야 한다.The UV blocking film should not only have excellent UV absorption characteristics, but also have excellent insulation properties in order to prevent an increase in the leakage current of the capacitor. Materials that satisfy these two requirements simultaneously include SiN or SiON, and the UV light absorption characteristics are improved as the Si-H bond concentration and N concentration in the film increase. On the other hand, the SiN or SiON deposition process causes hydrogen atoms and ion diffusion into the ferroelectric, causing ferroelectric properties to be degraded. Therefore, when forming a UV blocking film of SiN or SiON, a hydrogen diffusion prevention film forming process such as Al 2 O 3 should be preceded.
이하, 첨부된 도면 도 2a 및 도 2b를 참조하여 본 발명의 실시 예에 따른 FeRAM 소자 제조 방법을 상세하게 설명한다.Hereinafter, a method of manufacturing a FeRAM device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2A and 2B.
먼저 도 2a에 도시한 바와 같이, 소자분리막(31) 그리고 게이트 절연막(32), 게이트 전극(33) 및 소오스·드레인(34)으로 이루어지는 트랜지스터 형성이 완료된 반도체 기판(30) 상에 제1 층간절연막(35)을 형성하고, 제1 층간절연막(35) 내에 형성된 제1 콘택홀(C1)을 통하여 트랜지스터의 소오스·드레인(34)과 연결되는 비트라인(36)을 형성한 다음, 비트라인(36) 형성이 완료된 전체 구조 상에 제2 층간절연막(37)을 형성하고, 제2 층간절연막(37)과 제1 층간절연막(35)을 선택적으로 식각하여 트랜지스터의 또 다른 소오스·드레인(34)과 연결되는 제2 콘택홀(C2)을 형성한 다음, 제2 콘택홀(C2) 내에 폴리실리콘 플러그(38), 실리사이드층(39) 및 확산방지막(40)을 형성하고, 하부전극(41), 강유전체막(42) 및 상부전극(43)으로 이루어지는 강유전체 캐패시터를 형성하여 상기 제2 콘택홀(C2)을 통하여 트랜지스터와 연결시킨다.First, as shown in FIG. 2A, a first interlayer insulating film is formed on a semiconductor substrate 30 on which a transistor is formed of the device isolation film 31 and the gate insulating film 32, the gate electrode 33, and the source and drain 34. And a bit line 36 connected to the source and drain 34 of the transistor through the first contact hole C1 formed in the first interlayer insulating film 35, and then the bit line 36. ) The second interlayer insulating film 37 is formed on the entire structure of the formed structure, and the second interlayer insulating film 37 and the first interlayer insulating film 35 are selectively etched to form another source and drain 34 of the transistor. After forming the second contact hole C2 to be connected, the polysilicon plug 38, the silicide layer 39, and the diffusion barrier layer 40 are formed in the second contact hole C2, and the lower electrode 41, A second ferroelectric capacitor including the ferroelectric layer 42 and the upper electrode 43 is formed. It is connected to the transistor through the contact hole C2.
상기 제1 층간절연막(35)은 HTO(high temperature oxide)와 BPSG(borophosphosilicate glass)를 적층하여 형성하고, 상기 실리사이드층(39)은 폴리실리콘 플러그(38) 상에 Ti, Co 등을 형성하여 후열처리를 실시하여 형성한다.그리고, 상기 확산방지막은 TiN, TiAlN 또는 TiSiN 등으로 형성한다. 상기 강유전체 캐패시터의 하부전극(41)은 Pt/IrOx/Ir 및 IrOx/Ir의 적층구조 또는 Pt/RuOx/Ru 및 RuOx/Ru의 적층구조로 형성하고, 상기 강유전체막(42)은 페로브스카이트(perovskite) 구조를 갖는 PZT(Pb(ZrxTi1-x)O3, x는 0.4 내지 0.6) 또는 SBT(SrxBiyTa2O9, x는 0.7 내지 1.0, y는 2.0 내지 2.6), SBTN(SrxBiy(TaiNbj)2O9, x는 0.7 내지 1.0, y는 2.0 내지 2.6, i는 0.7 내지 0.9, j는 0.1 내지 0.3), BLT(Bi4-xLaxTi3O12, x는 0.6 내지 0.9) 등과 같은 Bi-레이어드(Bi-layered) 페로브스카이트 구조를 갖는 강유전체막으로 형성하며, 상부전극(43)은 Pt막 또는 IrOx, RuOx등으로 형성한다.The first interlayer insulating layer 35 is formed by stacking high temperature oxide (HTO) and borophosphosilicate glass (BPSG), and the silicide layer 39 forms Ti, Co, or the like on the polysilicon plug 38. The diffusion barrier is formed of TiN, TiAlN, TiSiN, or the like. The lower electrode 41 of the ferroelectric capacitor has a stacked structure of Pt / IrO x / Ir and IrO x / Ir or a stacked structure of Pt / RuO x / Ru and RuO x / Ru, and the ferroelectric film 42 is PZT having a perovskite structure (Pb (Zr x Ti 1-x ) O 3 , x is 0.4 to 0.6) or SBT (Sr x Bi y Ta 2 O 9 , x is 0.7 to 1.0, y is 2.0 to 2.6), SBTN (Sr x Bi y (Ta i Nb j ) 2 O 9 , x is 0.7 to 1.0, y is 2.0 to 2.6, i is 0.7 to 0.9, j is 0.1 to 0.3), BLT (Bi 4 -x La x Ti 3 O 12 , where x is 0.6 to 0.9), and the like is formed of a ferroelectric film having a Bi-layered perovskite structure, and the upper electrode 43 is formed of a Pt film or an IrO x , It is formed by RuO x and the like.
다음으로 도 2b에 보이는 바와 같이, 강유전체 캐패시터 형성이 완료된 전체 구조 상에 수소 확산방지막(44), UV 차단막(45) 및 제3 층간절연막(46)을 형성하고, 제3 층간절연막(46), UV 차단막(45) 및 수소 확산방지막(44)을 선택적으로 식각하여 강유전체 캐패시터의 상부전극(43)을 노출시키는 제3 콘택홀(C3)을 형성한 다음, 금속배선(47)을 형성한다. 한편, UV 광은 금속에 잘 흡수되어 투과하지 못 하는 특성을 갖으므로 UV 광이 강유전체 막에 조사되기 위한 경로는 상부전극이 없는 캐패시터의 옆면(side-wall)이다. 따라서 UV 차단막은 캐패시터의 옆면에 조사되는 UV 광을 차단하는데 주 목적이 있다. 또한 층간절연막, UV 차단막 및 수소확산방지막은 동시에 식각하는데, 수소확산방지막(약 100Å), 층간절연막(약 5000Å)비해 매우 얇기 때문에 이를 식각하는 시간은 층간절연막 식각하는 시간에 비해 매우 짧아서 수소확산방지막 식각하는 동안 UV 광 조사에 의한 캐패시터의 특성 저하는 무시할 정도이다.Next, as shown in FIG. 2B, the hydrogen diffusion barrier 44, the UV blocking layer 45, and the third interlayer dielectric layer 46 are formed on the entire structure where the ferroelectric capacitor is formed, and the third interlayer dielectric layer 46, The UV blocking layer 45 and the hydrogen diffusion barrier layer 44 are selectively etched to form a third contact hole C3 exposing the upper electrode 43 of the ferroelectric capacitor, and then a metal wiring 47 is formed. On the other hand, since the UV light is well absorbed by the metal and does not transmit, the path for irradiating the UV light to the ferroelectric film is a side-wall of a capacitor without an upper electrode. Therefore, the UV blocking film has a main purpose to block the UV light irradiated on the side of the capacitor. In addition, the interlayer insulating film, UV blocking film, and hydrogen diffusion prevention film are simultaneously etched, but since they are much thinner than the hydrogen diffusion prevention film (about 100Å) and the interlayer insulation film (about 5000Å ), the etching time is very short compared to the time for etching the interlayer insulation film. During etching, the deterioration of the capacitor due to UV light irradiation is negligible.
상기 수소 확산방지막은 상기 UV 차단막(45) 및 제3 층간절연막(46) 형성 과정에서 발생하는 수소가 강유전체 캐패시터 내부로 확산하는 것을 방지하기 위한 것으로서, 본 발명의 실시 예에서는 수소확산방지막(44) 형성을 위하여 MOCVD(metal organic chemical vapor deposition) 또는 ALD(atomic layer deposition) 방법으로 50 Å 내지 100 Å 두께의 Al2O3막을 증착한다. 상기 UV 차단막(45)은 SiH4및 NH3를 사용하여 형성한 SiN 또는 SiH4, NH3및 N2O를 사용하여 형성한 SiON으로 이루어진다. UV 차단막(45)은 플라즈마를 이용한 화학기상증착방법 또는 저압(low pressure) 화학기상증착방법으로 형성하며, 그 두께는 1000 Å 내지 3000 Å가 되도록 한다. 상기 제3 층간절연막(46)은 SiOx와 SOG(spin on glass)를 적층하여 형성한다. 그리고 상기 금속배선(47)은 TiN 확산방지막, Al막 및 TiN 반사방지막을 적층하고 패터닝하여 형성한다.The hydrogen diffusion barrier layer is to prevent hydrogen generated in the process of forming the UV blocking layer 45 and the third interlayer dielectric layer 46 from being diffused into the ferroelectric capacitor. In the embodiment of the present invention, the hydrogen diffusion barrier layer 44 For the formation, an Al 2 O 3 film having a thickness of 50 kV to 100 kV is deposited by metal organic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD). The UV blocking layer 45 is formed of SiN formed using SiH 4 and NH 3 or SiON formed using SiH 4 , NH 3 and N 2 O. UV blocking film 45 is formed by a chemical vapor deposition method or a low pressure chemical vapor deposition method using a plasma, the thickness is to be 1000 kPa to 3000 kPa. The third interlayer insulating film 46 is formed by stacking SiO x and spin on glass (SOG). The metal wiring 47 is formed by stacking and patterning a TiN diffusion barrier film, an Al film, and a TiN antireflection film.
전술한 본 발명의 실시예에서는 폴리실리콘 플러그(38)를 형성하여 트랜지스터와 캐패시터를 연결하는 경우를 예로서 설명하였지만, 폴리실리콘 플러그를 이용하지 않는 NPP(non-poly-silicon plug) 구조를 갖는 저밀도 FeRAM 소자에도 적용가능하다.In the above-described embodiment of the present invention, a case in which a polysilicon plug 38 is formed to connect a transistor and a capacitor has been described as an example, but has a low density having a non-poly-silicon plug (NPP) structure that does not use a polysilicon plug. It is also applicable to FeRAM devices.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 강유전체 캐패시터를 덮는 UV 차단막을 형성함으로써, 강유전체 캐패시터 형성 후 실시되는 RIE 식각공정에 의해 강유전체 캐패시터의 특성이 저하되는 것을 효과적으로 방지할 수 있다.According to the present invention as described above, by forming a UV blocking film covering the ferroelectric capacitor, it is possible to effectively prevent the deterioration of the characteristics of the ferroelectric capacitor by the RIE etching process performed after the formation of the ferroelectric capacitor.
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| US7078241B2 (en) | 2003-03-27 | 2006-07-18 | Samsung Electronics Co., Ltd. | Methods of forming ferroelectric capacitors using separate polishing processes |
| KR100703971B1 (en) * | 2005-06-08 | 2007-04-06 | 삼성전자주식회사 | Semiconductor integrated circuit device and method for fabricating the same |
| KR100729267B1 (en) * | 2006-03-08 | 2007-06-15 | 삼성전자주식회사 | Chemical mechanical polishing method, method of manufacturing a ferro-electric capacitor using the chemical mechanical polishing method and method of manufacturing a ferro-electric memory device using the chemical mechanical polishing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7078241B2 (en) | 2003-03-27 | 2006-07-18 | Samsung Electronics Co., Ltd. | Methods of forming ferroelectric capacitors using separate polishing processes |
| KR100703971B1 (en) * | 2005-06-08 | 2007-04-06 | 삼성전자주식회사 | Semiconductor integrated circuit device and method for fabricating the same |
| KR100729267B1 (en) * | 2006-03-08 | 2007-06-15 | 삼성전자주식회사 | Chemical mechanical polishing method, method of manufacturing a ferro-electric capacitor using the chemical mechanical polishing method and method of manufacturing a ferro-electric memory device using the chemical mechanical polishing method |
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